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CDN Live Allegro / IC Packaging Customer Day

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Published on Jun 20, 2012

Testimonials from customers that attended the Allegro Customer Day

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  1. 1

    Cadence showcases Sigrity™ 2015 technology portfolio at DesignCon

  2. 2

    IC-driven ball map design and optimization with OrbitIO

  3. 3

    Standalone ball map design and optimization with OrbitIO

  4. 4

    Allegro Tool Setup and Configuration

  5. 5

    Cadence Allegro Sigrity for Automotive Ethernet Design

  6. 6

    Multi-Fabric Interconnect Planning and Optimization with OrbitIO System Planner and SIP Layout

  7. 7

    DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

  8. 8

    Allegro TimingVision Environment

  9. 9

    Allegro Sigrity OptimizePI - Automated Decap Design

  10. 10

    Signal Integrity Analysis of Serial Data Channels

  11. 11

    Why does signal integrity analysis need to be power-aware?

  12. 12

    Create optimum pin assignments for FPGAs on PCBs

  13. 13

    Multi-Board Electrical and Thermal Co-simulation using PowerDC

  14. 14

    IC Package Assessment Demo_ Allegro Sigrity SI 16.61

  15. 15

    Allegro Sigrity SI Virtual Prototyping

  16. 16

    Allegro PCB Editor v16.6 Etch Editing Improvements

  17. 17

    Advanced Miniaturization Techniques using Allegro PCB Editor v16.6

  18. 18

    Productivity Improvements in Allegro PCB Editor in version 16.6

  19. 19

    Allegro Auto-interactive Delay Tuning in version 16.6

  20. CDN Live Allegro / IC Packaging Customer Day

  21. 21

    Cadence PCB Signal and Power Integrity 3-Day Event Featuring Robert Hanson

  22. 22

    Allegro PDN Analysis Technology

  23. 23

    Favorite Features of an IC Package Designer: Wirebonding

  24. 24

    Favorite Features of an IC Package Designer: Assembly Rule Checks

  25. 25

    Cadence FPGA System Planner with Xilinx ISE

  26. 26

    Managing architectural changes with Allegro FPGA System Planner

  27. 27

    Favorite Features of an IC Package Designer: Rich and Diverse Set of Import and Export file formats

  28. 28

    Favorite Features of an IC Package Designer: Flexible 3D Viewing

  29. 29

    Allegro FPGA System Planner using patented pin assignment synthesis technology PART 2

  30. 30

    Allegro FPGA System Planner using patented pin assignment synthesis technology PART 1

  31. 31

    TeamAllegro Spices Up SNUG with Allegro PCB SI

  32. 32

    Breakout routing for Intel's latest Mobile CPUs

  33. 33

    CADENCE Allegro and OrCAD PCB virtual event

  34. 34

    CADENCE Allegro and OrCAD PCB virtual event

  35. 35

    CADENCE Allegro and OrCAD PCB virtual event

  36. 36

    Cadence Allegro & OrCAD 16.3 Virtual Conference Launch

  37. 37

    CADENCE Allegro and OrCAD PCB virtual event introduction

  38. 38

    Cadence Allegro Signal Integrity virtual conference introduction

  39. 39

    Cadence Allegro & OrCAD Virtual Launch

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