 Hello everyone, myself Sanjay Udge, Assistant Professor, Department of Electronics Engineering, Valchand Institute of Technology, Solapur. Today we are going to discuss earth synchronous counters. Learning outcomes. At the end of this session, students will be able to design different earth synchronous counters. Outline. Introduction to counters. Types of counters. Earth synchronous counters. Earth synchronous up counters. Earth synchronous down counters. Design of mod 3 ripple counter and references. Counters. It is a digital circuit used for counting pulses. It is a sequential circuit. It is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Classification. There is a great variety of counter based on clock. Whether it is a synchronous or earth synchronous. In synchronous, the clock is applied simultaneously to all the flip-flops. Whereas in earth synchronous counter, clock signal is not applied simultaneously. Clock trigger. Whether it is a positive edge triggered or negative edge triggered. Counts. Whether it is a binary counter or decayed counter. Count direction. Up counters, down counters or up down counters. Flip-flop used. Whether JK or T or D type. Earth synchronous synchronous counters. Classified depending upon the way in which clock signal is applied to flip-flops in the circuit. Earth synchronous counters and synchronous counters. Now we are going to discuss earth synchronous counters. External clock pulse is applied to one flip-flop and then the output of the preceding flip-flop is up. Connected as a clock to the next flip-flop. Ripple counter. The clock input or the information ripples through the consecutive flip-flops in earth synchronous counters. That is the clock input to a flip-flop is the output of the preceding flip-flop. Hence they are also termed as ripple counters. This a two bit earth synchronous counter. You will see these two counters. They are flip-flops. They are of JK and JK flip-flops. This is FF0 and FF1. The J and K inputs of both the flip-flops are permanently connected to logic one level. So this can be treated as a T flip-flops. Here the clock signal is given to the first flip-flop FF0. Output Q0 is connected by inverting it as a clock input to the next flip-flop. So this is earth synchronous flip-flop in which output of the previous flip-flop is connected as a clock signal to the next flip-flop. At the arrival of the first clock pulse, this will toggle Q0 from 0 to 1. Initially Q0 and Q1 are reset. So at the arrival of the first clock pulse, Q0 will toggle from 0 to 1. This is 1. This is 0. This is a positive edge triggered flip-flop. So 0 it will be inactive. Q1 will remain 0. In the next clock pulse, the count is 0, 1. In the next clock pulse, it will toggle from 1 to 0. This is 0. This will come 1. So this is active. This will become 1. So the count is 1, 1, 0. In the next clock, third clock pulse, this will toggle from 0 to 1. So this will be 0. This will be inactive. This will remain to 1. So the count will be 1, 1. In the fourth clock pulse, this will toggle from 1 to 0. This is 0. This is 1. This will also toggle from 1 to 0. So the count will be 0, 0. So this is the sequence. Initially resetting, it will be 0, 0. At the arrival of the first clock pulse, it is 0, 1, 1, 0, 1, 1 and 0, 0. Modules of a counter. The number of states or counting sequences through which a particular counter advances before returning once again back to its original first state is called the modulus. In other words, the modulus is the number of states the counter counts. Updown counter. The job of a counter is to count by advancing the contents of the counter by one count with each clock pulse. Counters which advances their sequence of numbers or states when activated by a clock input are said to operate in a count up mode. Likewise, counters which decrease their sequence of numbers or states when activated by a clock input are said to operate in a count down mode. Counters that operate in both the up and down modes are called as bi-directional counters. This is the 3-bit asynchronous counter. Requires 3 flip-flops or the clock are active low or negative edge triggered flip-flops. So the signal available, it must be 0 at the over here. So Q, it must be 0 to activate this flip-flop. Here also Q must be 0 to activate this flip-flop. Now again the connection, this JK inputs of all these 3 flip-flops are connected permanently logic 1, that is at high level. Initially all these 3 flip-flops are reseted. So Q2, Q1, Q0 will have the output 0, 0, 0. At the arrival of the first clock pulse, this Q0 will toggle to 1. This 1 is connected as a clock input, so Q1 will be 0, Q2 will be 0. So the count will be 0, 0, 1. Next, at the arrival of the second clock pulse, this will toggle from 1 to 0. This is 0, this will toggle to 1. This is 1, this will be 0. So the count is 0, 1, 1, 0. Next, at the arrival of the third clock pulse, this will toggle from 0 to 1. This 1, this will be inactive, it will remain at the previous state 1. This will be again 0. So the count is 0, 1, 1. At the arrival of the fourth clock pulse, this will toggle from 1 to 0. This is 0, this will be active, this will also toggle from 1 to 0. This will be active, this will, the count will be 1. So the, so the count will be 1, 0, 0. In this way, the count will proceed as 1, 0, 1. Next, 1, 1, 0. And finally, 1, 1, 1. After the last maximum count 1, 1, 1, this will get, this will get reseted as 0, 0, 0 at the arrival of the next clock pulse. This is the timing diagram. Q0 output will change at the every transition of every clock pulse. Whereas Q1 will toggle only when, Q1 will toggle only when change when Q0 changes from 1 to 0. In similar manner, Q2 will change only when Q0 and Q1 will changes their states from 1 to 0. There is a summary of operation starting from 0, 0, 0, then 0, 0, 1 up to 1, 1, 1. And finally, they will get reseted after 8th clock pulse that is 0, 0, 0. This three bits are synchronous down counter. Again, we are using three flip-flops. JK inputs of all these flip-flops are connected to logic 1 that is high. So this, this can be treated as a T-flip-flops. The only difference is in up contours we are connecting Q0 output as a clock to the next flip-flop. Here also Q1 as an a Q1 output as a clock to the this flip-flop. In down contours the only difference is Q bar output is connected as a clock to the next flip-flop. Now initially all these flip-flop are in the reset condition. So Q2, Q1, Q0 will be at 0, 0, 0. At the arrival of the first clock pulse this will Q0 will toggle from 0 to 1. This is 1. This is 0. So this will be also active. This will become 1. This is 1. This Q bar, Q1 bar is 0. So this will enable this flip-flop. So Q2 will be 1. So the output will be 1, 1, 1 at the arrival of the first clock pulse. Next. In the second clock pulse this Q0 will toggle from 1 to 0. 1 to this Q0 is 0. This will be 1. These two will be disabled. So the output will be 1, 1, 0. Next. See at the arrival of the third clock pulse this will toggle from 0 to 1. This is 1. This is 0. This will become 0. This will become 1. So output will be 1, 0, 1. In this manner the counter will progress to 1, 0, 0. Then 1, 1, 0. Then 0, 1, 0, 1, 0. Then 0, 0, 1. And finally it will be 0, 0, 0. So this is how the counter advances in the in down condor from the maximum count 1, 1, 1 to 0, 0. This is the timing diagram. Q0 will change at the arrival of the each clock pulse. This Q1 will change when output of Q0 changes from 0 to 1. This also for Q2. Q2 will toggle or changes state when the Q1 changes from 0 to 1. This is the summary of operation. It will start from the maximum count 1, 1, 1 and it will go down to 0, 0, 0. This is a down counter. What is the difference between up counter and down counter? Answer. In up counter Q output of preceding flip-flop is connected as a clock signal to the next stage flip-flop. In down counters Q bar output of the preceding flip-flop is connected as a clock signal to the next state flip-flop. Design of mod 3 counter modulus. It is the number of states through which a counter progresses during its operation. We can design a mod 3 counter using 2 flip-flops. So the states will be 0, 0, 0, 1, 1, 0, 1, 1. The fourth state when Q0 equal to 1 and Q1 equal to 1 is prohibited. So this is how we can design a mod 3 counter. This 2 flip-flops are required here. This is a combination logic circuit. The truth table for the reset logic. 0, 0, output logic must be 1, 0, 1, output logic 1, 1, 0, the output logic equals 1. So we don't want this state 1, 1. As soon as the Q0 and Q1 becomes 1, the flip-flop outputs must be reset using this reset logic. So reset logic being active low input. So once Q0 and Q1 becomes 1, the output logic must be equal to 0. So from this we prepared a K-map. For 0, Q0, Q1, 0, logic is 1. Q0, 0, Q1, 1, again output logic will be at high state. Q0, 1, Q1, 1, again the reset logic will be at high state. Now since we don't want Q0 and Q1 equals to 1, we must have reset logic equals to 0. Using a K-map, we got the equation as Z. That is the output logic must be Q0 and Q0.Q1 bar, which is a NAND gate. So with this we implemented a mod3 counter with two JK flip-flops of Q0, Q1 output given to a reset logic which is nothing but a NAND gate. So when Q0, Q1 will become 1, the output of this logic will be 0. That will clear the flip-flop and will reset. So Q0, Q1 will be 1. These are the references. Thank you.