 Today's lecture the plan is to discuss briefly sketchily role of so called timing analysis in the context of physical design flow, physical design automation flow. Most of you would be already aware of the timing analysis in particular. In fact, static timing analysis you would have used in while using the tools FPG CAD tools or ASIC tools cadence tools. Just this lecture would aim to give you some brief idea behind like at about the core techniques core algorithmic idea used in this timing analysis. The concepts notions of so called directed acyclic graph topological sort couple of notions which are only present in the algorithms of this kind. So, first of all I mean physical design as I said it is about layout right. So, what is the connection with timing analysis I mean what is the connection of timing analysis with physical design. First of all most importantly you see recall that we I mean I mentioned that in the automated process of layout generation lot of importance is given to minimizing the wire length right. So, why I mean first of all yes might I remark that must I remark that if wire length number of wires or length of wires is very large that would kind of lead to more complexity for routing. That is if route if you have want to route within some limited area then of course, it becomes harder to route if you have very long wires if wires are running very long from I mean and so on. Of course, number of wires is going to be same as number of nets, but like you know if you have done a poor placement then it could possibly mean that a lot of wires are running very long from one side of the chip to other side. So, that is why while doing placement one like one of the primary goals of good placement is to ensure as low as possible total wire length. Of course, until one does one does routing one does not really exactly know accurately know what wire length is, but after placement one can get some estimates of how much the wire length would be and based on the estimates the placement heuristics would be would be guided to like to sort of make a better placement and so on. Yeah, so why was this wire length crucial? So, in particular suppose this interconnect delays the wire delays were insignificant or negligible then would be would be have been worrying so much about the wire length. Of course, wire length would mean like you know complexity of router it will be more headaches for the router, but the in terms of delay of timing the wires the length of the wires would not matter if the delays of interconnects were extremely insignificant compared to the delays of the gates themselves or the modules or cells themselves. So, in this case wire length would not be so crucial, but definitely that is not a situation of course, to some extent it will be crucial in terms of area optimization, but not in terms of timing, but like reality is that this wire delays are significant right are becoming increasingly more significant. So, they have to be kind of given good attention to. So, in this sense like because timing is very important and estimates of timings are important one would get an idea of what would be the acceptable wire length how I mean like we should not kind of I mean and so on so forth. So, also like certain tools or the so called static timing analysis would let it would tell you about would tell a designer about or that like automation tool about what is the timing critical portion of the net list and if one gets an idea about that then one the in a manual or automated fashion that timing critical portion which could involve some gates or which could involve some wires those gates could be upsized resized to improve the delays the inertia or the wires could be widened. So, as to reduce it the resistance or some appropriate buffer insertion would be done to reduce the delays along the long wires in the critical timing critical portion of the net list. So, net list restructuring can be done in case one gets a timing estimate. So, time like as accurately as possible or like as quickly as possible. So, one would have to kind of this will not be one step procedure because every time you make some tentative placement or routing layout decisions you have one like you know feasible kind of routing, but then you might want to improve upon it and then you look at a timing and identify the critical portions try to improve their hoping to get overall improvement in the timing and so on so forth. So, this is how the timing analysis tools will be interacting with the layout generation tools. So, many of this route placement routing algorithms would actually be getting a bit of feed quite a bit of feedback from the timing analysis every now and then. So, we aim to look at some core notions in this timing analysis with the help of examples illustration. So, since as I mentioned since wire delays are significant therefore, it is you know interest to have a high performance or optimum or close to optimum wire length or appropriate sizing. And other point I mentioned is that the timing analysis helps identify the critical portions of net list and this can be improved in various ways as I said like by upsizing resizing the gates. So, as to reduce the inertia like or like you know improving this interconnect or inserting buffers at appropriate locations many of this problems have been studied algorithmic for the algorithmic solutions. So, core notion in timing analysis and also one of the simplest to understand and get develop some good intuition about for more difficult concepts and problems. So, that is so called static timing analysis. So, this static refers to static means not dynamic means is something that does not really put any give any specific emphasis to the runtime behavior dynamic behavior more about most. So, this static means static analysis means mostly based on static information not runtime information. So, that is the delay estimate worst case delay estimates actually at the runtime the delays may not be as bad as the worst case delay estimates and also the topology that is graph representation or graph abstractions. By looking at topology and the worst case delay estimate one can fathom lot one can get a lot of I mean lot of useful information about timing requirements and timing optimizations and which will help in the automation I mean I mean hoping to arrive at good high performance layouts placement routing. So, when you hear about static timing analysis you will automatically I mean hear about the terms like a t which stands for actual arrival time r a t or some other notation for like mnemonics for this required arrival time. So, these are the times arrival times of signal transitions. So, I will will obviously elaborate with the help of examples. So, things will be very clear and based on these two concept there is a notion of slack which is quite important slack. Slack will be r roughly speaking it is a difference between r a t and a a t of individual nodes. So, in the timing analysis we will interestingly we will be kind of dealing with will only some kind of combinational. So, if you start looking at timing analysis algorithm many of them seem to be just talking about combinational circuit. So, I mean what does it mean? So, does it mean that there these things apply only to very restricted situation of purely combinational designs? No, in fact this combinational portion of any design is the really the core of it in terms of the logic part of it. The other than in any typically any synchronous sequential circuit there are going to be flip flops and there is going to be combinational logic portion. The flip flops are for the purpose of storing the flip flops are being used for storing the data or the state of controller or the state of the computation data path state and combinational logic that is the one I mean is the portion of the circuit which is actually like you know continuously working continuously kind of updating its outputs in the response to the changes at the inputs. So, that is the combinational part of the sequential circuit is the one which is which is kind of trying to compute the next state of computation next state of controller and the next the next values of the variables the data items and the flip flops are only like you know holding on to the state or the state of computation or the data current values of the variables the data items and so on so forth. So, for the timing analysis the flip flops really want I mean and we would not have to worry about the flip flop so much. In fact, at an abstract level we will kind of be cutting the circuit at a flip flops and once you cut this big sequential circuit at a flip flops if it is a well designed sequential circuit then what will be left with is obviously purely combinational, but more interestingly there would not be any feedbacks within the combinational portions. If at all the circuit obviously will have feedback there will be some like you know next state depends on the current state. So, that means and the next state is going to become the current state in the next clock cycle. So, there is a role of feedback in sequential algorithm sequential circuits, but every any time there is a feedback then that feedback path will include necessarily include a flip flop one or more flip flops. So, if you cut at the flip flops you are going to have all the feedbacks removed and whatever the purely combinational circuit that is left is feedback free. Of course, there is nothing wrong really in having feedbacks in the in a circuit with which has just combinational gates, but those kind of feedbacks can give you latches, can give you rise to memory elements or can give rise to oscillators configurations. So, there is no need like for designing latches and oscillators in a like you know in that using just they would be one would in large designs one would typically make use of them as black boxes or as well designed components and the combinational gates would be purely used for the in the feedback free manner for generating the next state logic or the output logic milli or more output logic. So, one of the things about static time and analysis you will notice is that this example the circuits that we will be dealing with are will be shown to be purely combinational and without feedback also. So, again I am emphasizing cautioning that like feedback free is not the absolute necessity in designs especially feedback free I mean, but like you know well designed circuit the combinational part did not have feedbacks. If at all feedback is meant for holding like you know like designing a memory element like a latch then you could as well use a well designed latch in that particular implementation technology. And it helps a lot to like you know assume that there are no feedbacks that makes the algorithm design process analysis process very smooth and efficient interesting and efficient. So, I will take an example right away which will be kind of exploring to show some concepts. So, here is one circuit I have some labels or notations over here about a moment I will explain what this mean all right yeah. So, this is again an example courtesy here is 0.15 the book VLSI physical design from graph partitioning to timing closure by Cahang, Linig, Markov and who Springer I think it came out last year ago or couple of years ago may be good book like fairly elementary introductory and well written of course, there are other books, but I chosen to use examples because this is not a core course like a full flash course on VLSI design automation just for the overview of some concepts I have try to keep the matter simple examples and notions simple simplistic overview essentially. In this particular example here we have a net list again what you notice is that there are no flip-flops here it is purely combinational gates and also what you notice is that there is no looping there is no feedback here there seem to be this ABC we can regard them as they are there to be regarded as inputs and F is the only output of course, you could have multiple outputs and many more inputs much more complex such combinational circuit the annotations the labels here 0 0.6 they kind of they represent the arrival time of signal transitions at this inputs. So, you know like from somewhere like with respect to certain synchronizing time let us say positive age of a synchronizing clock in the system this signal becomes stable at 0.6 nanosecond after the rising age of the clock this signal is let us say immediately stable and so on take it with the pinch of salt this things need not be 0 then the labels on this wire segments are like they indicate the delays of this interconnects the labels on the gates like this is the this is then and gate and this label name is wire and this quantity in 2 indicate the delay the worst case delay of this particular gate and this is the inverter with delay 1 this is or gate with delay 2 and gate with delay 2 and these are the wire delays 0.2 0.25 nanosecond 0.3 nanosecond 0.1 nanosecond 0.1. So, you do not worry too much about you know this net is being driven by this it is going here it is going here. So, like you know what is the delay of this common portion what is the delay of this portion one can study at that level also anyone studies the l more delay R C trees, but right now just assume that this 0.1 means that it is a delay the worst case delay for the effect of signal transition at this point to reach or this particular pin of this gate and so on. So, 0.3 is a delay between signal transition here and a corresponding signal transition over here. So, and let us assume that for the purpose of so called pessimistic static timing analysis the whole circuit all the elements of circuit the wires and gates are behaving in the worst case fashion that is all these numbers that we are showing which are worst case estimates they actually like you know the signals are stabilizing or like you know making transitions at the like with the worst case delays. So, things might turn out to be better than that in the at the run time and those things are also studying this subject, but that will complicate our discussion a bit. So, based on this feedback free combinational circuit which is which would have been obtained like you know out of a general kind of sequential circuit which has this kind of structure there is a controller a controller is basically a set set of trip flops which maintain the state and combinational logic which will generate the next state based on the current state this trip flops maintain the current state and these are clocked and this combinational logic is computing the next state which is to be loaded into the flip flops at the beginning of the next clock cycle or the end of the current clock cycle also this combinational logic is also influenced by a primary inputs or inputs from some other source not inputs from this flip flop. These are considered to be primary inputs of this particular controller this is the controller and then there is a data path. So, the data path might have some flip flops all by some combinational logic some another set of registers followed by and so on. It could be this is kind of linear picture I drawn just for I mean the in general data path can be far more complex there will be registers combinational logic all there will be multiplexers and so on. But again with the data path you see that there is there are flip flops and there are combinational logic clouds controller also has area of trip flops for maintaining the state and combinational logic for generating the next state and the outputs this outputs of this controller go to the data path and so on so forth. We are aware of that we are not going back I mean they can you know leading the discussion back to FSM plus data path. But the important like here we want to I want you to identify that this combinational logic is the one that we have to focus on for static timing analysis. Just cut this flip flops or like you know remove them from the picture what you are left with is possibly disconnected set of combinational logic clusters or clouds we can think of them as which are feedback free like in this example this circuit is feedback free of course this is must be a very small part of a very small sequential circuit if at all but in general it could be hundreds of thousands or million or tens of millions whatever very big like not everything would be one like you know monolithic combinational circuit there could be lots of separate parts of it and they can be after partitioning they can be separately identified separately So, partitioning has one big role in this timing analysis also. So, this was just a picture of a general sequential circuit which will have controller data path. So, highlighting which portion is the one that we are going to look at in the static timing analysis this combinational logic. So, the notion of timing critical this is like vaguely remarked that the timing analysis static timing analysis is going to compute this so called actual arrival times and required arrival times which will be illustrated on this example. But after doing that and after computing the slacks this tools the analysis will identify the timing critical portion and in particular this critical path is an important like concept which most of you all of you will be very well aware of critical path is the one which is going to like which is important because that is the one which is going to like which has the maximum delay from any input to any output and which will like influence the maximum frequency at which the sequential circuit can be driven. So, that will be influence the speed of your implementation. So, critical path is the path which has max delay from any input any output. So, how is critical path identified? So, this the state of our timing analysis has much more ability than just identify critical paths, but it will help to begin with like you know understanding how critical paths are found and like that is a core notion. What kind of algorithmic ideas model the graph models graph algorithms get used that gives you some kind of insight motivation to study the next level more advanced concepts. So, I will just focus on the basics. So, this concept of actual arrival time. So, actual arrival time at U say where U is a pin of a gate say it could be output or input pin. So, this actual arrival time at a U at a pin U say U is this is a gate and this is say U. So, how is it going to be defined and what will be what will determine this particular actual arrival time which is the arrival time of the signal transition. The signal transitions are happening at the primary at the inputs and like you know because of the delays of the wires and delays of the gates the corresponding signal transition will happen at certain time and the time at which that signal transition occurs assuming that all the gates and all the wires are working are acting in the worst case fashion with worst case delays. The time at which this corresponding signal transition occurs and after which the signal this signal at U achieves its correct value is the actual arrival time. So, this will clearly be like you know based on say this is v 1, this is v 2, this is v 3. So, if these are the signals which are at the input of this then this will be max of a a t in this example a a t of v 1 plus what the delay of this gate say the gate g comma a a t of v 2 plus delay of g comma a a t of course, I can say it will much more elegant fashion, but anyway let us see how our thought ideas develop. So, clearly this right. So, it will be influenced by the one by the pin which is kind of which has the latest or actual arrival time you know. So, if this particular input might like becomes stable very early, but it will not like you know it would be of no use if some other input is going to arrive much later. So, the one which is going to arrive input that is going to arrive at the latest time instant is going to define it is going to determine the actual arrival time at the output of this gate. The delay of this gate is also included that is common for all these cases. So, it looks like you know it hints at the fact that this actual arrival times are recursively defined and that is the main key of things. Similarly, the notion of r a t required arrival time is also going to be recursively defined and I will just come to that in a moment. So, like to do this recursive computation recursive computation of a a t's and similarly of r a t's. This recursive that this recurrence relation is with the help of dynamic programming of I did not mention this, but this if one is interested one can like look at this as note that these are very interesting important examples of dynamic programming like otherwise one can think like you know one can also invent this ideas or discover this ideas without like you know up into this sophisticated notions of dynamic programming very intuitive concepts. So, this recursive computation with the help of dynamic programming or otherwise is can be efficiently done done in iterative fashion. By that I mean like we are going to compute the a a t's at all pins of combinational circuit which is which does not have feedback. We are going to start at the inputs and then like iteratively start computing the like iteratively compute the a a t's actual arrival time is at different pins you know in certain order the pins or gates will be processed in a clever order clever, but natural and simple clever that I do not mean it is going to take you effort to it is a clever idea like so called topological sort clever simple natural. So, I do not want to clever to necessarily mean that it is something very hard to further or understand very simple idea. So, in some kind of topological sort again the word I mean it is one of the very simple notions in algorithms and quite likely you are already familiar with it is going to be used to like you know visit this nodes the gates or pins in certain order and compute the a a t's and similarly for r a t's may be the order is order would be different over there, but the idea is the same instantly like I think I have missed mentioning once small point the one of the reason I was like you know bringing your attention to the the flip flops and like you know while talking about while in that you will see the we will see the focus on combinational circuit although there is no most I mean genuine like digital designs will have flip flops the flip flops are for the purpose of storage combinational logic is for the purpose of computing the next state computing doing the data processing and computing the outputs. So, what are the the so called inputs to this combinational logic and outputs from the combinational logic of course, some of the inputs to the combinational logic are coming from the external world and some of the outputs are going to the external world. So, they are primary inputs and primary outputs, but other than that we should regard the outputs of flip flop also as kind of secondary input to combinational logic like this output of this flip flop would can be regarded as a as an input to this combinational logic and to differentiate it from the input coming from external sources I will call it secondary input. Similarly, output of this combinational logic is going to is not going to the external world, but is going to like over here it is going to flip flops again. So, this is to be regarded as a secondary output of this combinational logic. So, should be in some sense regarded as an output. So, and that is of course, crucial because this notion of critical path that I mentioned which you are already familiar with which says it is a max delay path from any input to any output, but that any input any output include not just primary input primary output. So, this secondary input secondary output which are respectively the flip flop outputs and the flip flop inputs. So, one says loosely like critical path is the max delay flip flop to flip flop path, but I mean also it should include primary inputs and primary outputs. So, basically any input output path where the input outputs could be either of the primary kind or the secondary kind. So, I am sorry for the digression, but we will come back to. So, we are just like you know going to get some more idea about this actual how to compute actual arrival times and required arrival times and I said there like at a sophisticated level one can think of all this as very good example of so called dynamic programming very important idea in the algorithms as well as in particular VLSI CAD has many applications of this. And this notion of topological sort some kind of ordering anyway this is what you will get to study when you do that course on design automation or course on algorithms data structures. So, a graph modeling is preferred one can do this on the net list itself, but like to make good use of standard packages standard libraries for implementation one should like and do a clean analysis clean algorithm development and use of libraries like the abstractions are very useful. So, a graph modeling and again there is no just a single way of single particular way of modeling things by a graph. So, that circuit that I had drawn this one I am going to model it as a graph. So, I will just draw the graph first this there are remember like we call that there are a b and c there are this primary inputs or it could be secondary input inputs and there were labels here 0 0 and 0.6. So, there were those this labels were denoting the arrival times of signal transitions at this input. So, I am going to have some kind of dummy source and arcs of this kind edges directed edges of this kind and this I am going to label with this. So, this is going to mean that a signal transition arrives at this input c at 0.6, but at a and b it is there from time 0 itself. Then a is connected to input of the gate y. So, I am going to represent y by one node and I am going to label this by 2 remember that y is a and gate with a delay worst case delay 2 and this connection this wire from a to y has delay of 0.15. So, that I am going to represent it as by this directed edge because this is the direction in which the signal travels is 0.15. Similarly, I am going to draw the rest. So, b b drives this inverter x which has delay 1 and I think I forgot this this was 0.1. So, 0.1 this is x with delay 1 output of x drives y as well as this gate z. So, z is like z is a or gate with delay 2 z is driven by c as well as by x the length of this delay along this wire from c to z is 0.1 this delay is 0.3 like you know do not go by the lengths they could be because of the width of the interconnects or the cap and so on and some other factors. This also drives y with delay 0.1. So, this 0.1 and 0.3 correspond to this x driving this pin of y with after 0.1 delay and this with 0.3 delay c driving z with 0.1 delay. So, let us complete the rest of it like there is another gate called w which is an and gate with delay 2 which is driven by y delay of the wire is 0.2 and also driven by z this delay is 0.25 and this is generating as shown in that picture like it is going to output and the wire connecting the output of w to this output f is of delay 0.2. This is your f. So, I have introduced this dummy source for the purpose of kind of capturing this arrival time information at the inputs a, b, c. So, a, b, c are not really gates there is think of them as some kind of input pads or some input terminals at which signal transitions are arriving at certain specific time time 0 time 0 and time 0.6. So, this all the information has been captured here and it should you should convince yourself that the like this will suffice to like you know know the essence of the timing information the input information that is delays of wires and delays of gates. Now, we can start building up this propagating actual arrival time information and similarly the required time arrival information. So, arrival actual arrival time at a, b, c are the points 0, 0 and 0.6. So, it is going to be bit of a clutter here. So, I say a, a stands for actual arrival time a at this is going to be 0, a at this node is 0, a at this node is 0.6. Sorry, actually yeah that is enough because signal comes here this nodes are not really gates or they can think of them as simple red thumb dummy gates with 0 delays. So, at the output of this like over here we can we know that the arrival time is 0, 0, arrival time is 0.6. Now, based on this which are which of this for which of the other nodes their outputs we can find arrival times the signal is arriving here at time 0. So, based on this can we find can we decide what would be the arrival time of signal at this output of y not exactly I mean we need we know this information this 0.15 plus 2, but it could this arrive signal transition here to a final value would depend possibly it could depend on some other input path you know. For example, it could depend on signal going along this wire getting delayed here getting close like converted and another delay. So, this would have lead to 0.1 plus 1 that is 1.1 plus 0.1 1.2 plus 2 3.2. So, just knowing this this alone would not give this knowledge 0.1 1.2 will not give us the actual arrival time here to know the actual arrival time at this point you will need to know the actual arrival time over here and over here to know this we will need to know the actual arrival time of this and so on. So, we have to kind of process this visit this in certain order. So, before visiting y we should visit x simply because y depends on x. So, this so called topological order is ordering of this gates and so on like nodes gates or nodes as in graph in such a way that we do not we visit a node only after we have visited all the nodes on which it depends. So, we will visit y we will process y only after we process a and we process x because y depends on a and x. X will process we can process as soon as we know information about b. Similarly, z will process only after we have process x and we have process c. C would have process quite quickly x we would have once we have process x and a b c then we are eligible to process y and compute do a computation at z. And once we have computed at z and we have got a a a t also at y then we can go on to computing this at f or the output of this w and so on. So, we have to go in this particular order and that is that topological that is an example of so called topological order that is simply visit the nodes in a manner such that you do not visit something before having visited all the nodes that it depends on. So, topological order here will be first we will do x because x does not depend on once we have done a b c x can be done like immediately, but y neither y nor z or not w can be done because they will depend on x. So, what will be the arrival time of the signals transition at the output of x a at this point will be see that because of this path 0 plus 0.1 plus 1 1.1 there is no other way x will be signal transition at x will be output of x will be influence. So, it is 0 plus 0.1 plus 1 1.1 so a is decided over here now a is decided at this point and at this at the output of x now because of the signal has made a transition here to its correct value after another 0.1 there will be a stable value available at this input pin of y and at this input pin of y the value stable value is available at 0 plus 0.15 that time. So, then there is a further delay of 2 nanosecond let us say at this gate y. So, at the output of y now we are ready to compute a or a actual arrival time and that will be max of how much 0 plus 0.15 plus 2 that is 2.15 comma 1.1 plus 0.1 plus 2 that is 3.2 right 1.1 at the output of this plus 0.1 plus the inertia of this gate that is 2 that is 3.2. So, this will be 3.2 similarly a over here can be computed because it is going to be max of 1.1 plus 0.3 plus 2 comma 0.6 plus 0.1 0.6 plus 0.1 plus 2 which is equal to how much 1.4 3.4 right and similarly what will be the actual arrival time at the output of w I will just confirm I will work it out yeah what will be the actual arrival time over here yes a will be this is 3.4 plus 0.25 plus 2 that is 3.65 plus 2 that is 5.65 and from this side it is 3.2 plus 0.2 that is 3.4 plus 2 that is 5.4. So, maximum is 5.65 and at f will be a will be 5.85 5.65 plus 0.2. So, it is a very simple calculation very easy to implement as an algorithm in any language like it is just looking at topology we define figure out an order in which this node should be processed all the labels are indicating all the information that you need the delays of the wires delays of the gates and based on that in a systematic in a very linear efficient time you can get all these values actual arrival times at outputs of all the nodes all the gates in this particular design. So, now that means we know that sorry we know that the signal will as a result of signal transitions arriving at a b c at this given times at time 5.85 we will get a correct value of signal f as a result of I mean correct combinational value of at signal f. So, now the related question is like if this is the actual arrival time what like you know what would have been the required arrival times of the signals at different nodes like you know should is it was it really necessary that at a the signal must should have arrived at time 0 was it really necessary that at this c the signal should have arrived at 0.6 could it have been that signal would have been allowed to arrive a bit later. So, what are the required arrival times at the nodes if now we know that we are being able to receive a receive a value correct value at time 5.85 and that is because of this assumptions that we have made about arrival times here these are these are the actual arrival times, but what would be the required arrival time. So, that we meet a certain target required arrival time at the destination at the sink at a target. So, that is a dual kind of opposite kind of question and as your intuition would be telling you that it would really amount to making a backward pass here we are going in some kind of forward direction of the signal flow. We process a node only after we process all the nodes which drive that particular node. So, that is we are going in the direction of the signal flow if you go from the target in the direction backwards reverse direction of the signal flow we will be able to similarly compute this logic like intuitive notion of required arrival times and why is that required arrival time useful or interesting it is because we get to know like whether we have been a bit too like you know too pessimistic and like you know trying to generate the signal very early. We could have afforded a bit of delay the signal might have at certain time it pins the signal might arrive later and still we will have our computation or like you know our result available at the required time say at 5.85 definitely 5.85 is like you know is the best that you can get because these are the actual arrival times of signals. But could the signals have arrived late supposing we get an information that signal can arrive at node y sorry node a at time 0.2 and still we will be able to get at point at time 5.85 correct value. If the required arrival time at a small a is to be is found as 0.2 then we know that there is some kind of slack over here 0.2 that means we could have the some circuit that is driving generating this signal transition here could be made could we can afford it to be less efficient in terms of delay and generate this signal transition a bit later ok. So, having computed the arrival times we know that a here has been found out to be 5.85 ok. Now, say we say that this is also the required arrival time r at is also 5.85 ok. We require this as like you know as has been given by this actual arrival time we also. So, we let us say we require it exactly at this time only like you know by this time we require it then if you do a backward analysis to see what are the required arrival times of signals at the other nodes. So, here we want it to be at 5.85 then over here over here the required arrival time will be clearly 5.85 minus 0.2 that is 5.65 ok. Then can we immediately go on go back to finding the like you know guessing the required arrival time over here no right because it would the required arrival time here would like you know intuitively depend on naturally depend on the required arrival times here and so on. So, we have to go patiently in certain kind of opposite order in a direction opposite to the signal flow that is in this direction and process nodes. So, w is known. So, we hope to find the required arrival time here and required arrival time here. So, how much say at z this is over at the output of the gate w it is 5.65. So, over here at the output of z will be this is a required at 5.65 there be a 2 because of the 2 nanosecond delay of this and 0.25 nanosecond delay of this wire over here at the output of z we must have we must require the signal transition to take place at 5.65 minus 2 minus 0.25 that is is 3.4 again ok. It just happens to be same as a like you know we will like understand the reason of this for this phenomenon that wise turned out to be the same that bit later over here now over here. So, this is 5.65 we require the signal there is a 2 nanosecond delay and the 0.2 nanosecond signal. So, we require this at 5.25 sorry 3.45 yeah 3.45 like 5.65 minus 2 minus this is 5.65 minus 2 minus 0.2 right 3.45. Can you compare it with the actual time here at this output of the actual arrival time was 0.3.2 over here it was 3.4. Somehow may be a coincidence we could, but like actually it is not over here we have found this required arrival time at the output of z to be 3.4 which is same as the actual arrival time at the output of z which is 3.4, but the 80 at y output of y is 3.2, but the required arrival time at the output of y is 3.45. So, there is a discrepancy here and there is a like you know thing matching over here anyway. So, we will just you would have probably guess the reason for that also. So, this is going to tell us something about critical path ok. Now, having known the required arrival time at y and z we will can compute a required arrival time at x and that will be how much will that be that is interesting. So, r a t at x at the output of x by x I mean that output of x is going to be you can like you know check for yourself. I mean I encourage it to I would really encourage you to kind of think about it on your own because all these are very intuitively natural concepts even though you may not have done a formal course on this subject or algorithms. You will your natural thinking will lead you to such recurrence relationships r a t at x is going to be minimum of r a t at y minus whatever 2 minus 0.1 minus 2 minus 0.1 comma r a t at z minus 2 minus 0.3 and this will turn out to be 3.145 minus 2 that is 1.45 minus 0.1 that is 1.35 that is this term and from here 3.4 minus 2 that is 1.4 minus 0.3 that is 1.1. So, 1.1 is going to be 1.1 once again you notice that this is matching this particular arrival time of 1.1 over here is again it is not a coincidence. So, let us in fact wherever we find things matching like you know 5.85 and by design I have chosen this r a t also to be 5.85 and then r a t here was 5.65 which is matching this actual arrival time of 5.65. So, let me like you know color it differently. Similarly, here r and a are matching 3.4 see that 3.4 here and 3.4 and here also they are matching. So, from this let us quickly compute the remaining once we know the r a t here r a t at a is known and that will be r here will be 3.45 minus 2 that is 1.45 minus 0.15 that is 1.45 minus 0.15 is 1.3 sorry am I making a mistake 5.5 yeah ok here here r a t will be a please compare it with and it is obvious to note that it is like that here a t was 0, but r a t is 1.3 that means you know we got the signal here a bit too early we did not even have got a signal transition here it is time 0 could have got it as late as point 1 time 1.3 and still we would have been able to make it that is a meaning of it right yeah. So, now over here this is 1.1 this is 1 and this is 0.1. So, it is actually 0 that is interesting it is exactly matching the actual arrival time over here and that is why I will like you know kind of mark this. So, I will mark this mark all the things along which I am seeing things r and a matching. So, and over here it is going to be 3.4 minus 2 minus 0.1 that is 1.4 minus 0.1 that is r is going to be 1.3. So, here a was 0.6, but here it is now it is 1.3. So, they are not matching. So, now based on that r at this will be 1.3 minus 0 or minimum of that minimum of 1.3 minus 0 or 0 minus 0 or 1.3 minus 0.6 then that is clearly going to be 0 a was also 0 because this is kind of dummy source at arrival at some signal is at time 0 here and after 0.6 it arrived here and so on. So, this also I will mark it. So, what I have marked over here are this like you know is a path along which I have seen this r and a matching provided this r at t assume that I required the signal transition at f to be same as the time at which it actually arrives. So, r at and a at were matched over here and based on that I retraced and computed r at and along this path may be along some other path also it could have been matching, but definitely along this path things matched. What does it tell you like you yes. So, in fact, this is the this is an example of a critical path which is timing critical in the sense that if something if this components here the gates here are like you know if they are designed to happen to be poorer then the timing will become worse or if on the other hand if they become better marginally then actually timing can improve it is not necessary that they become much better the timing improves that much better like you know, but there is sensitivity to that. So, the timing of performance of this is going to be sensitive to the timing performance of the individual the wires along this path the gates along this path. So, this is what is considered to be critical path and a lot of attention is given attention can be given to this critical path things can be resized restructured the interconnects can be made more like efficient in terms of delay buffers can be inserted along longer wires of this kind 0.3 and things can be improved and design will improve. So, this is what roughly what roughly what happens in like timing analysis after doing this AIT RIT calculation the difference is calculated wherever there is a discrepancy that means there is a slack things could have been worse, but there is no slack that is along this RIT and AIT are matching the slack is 0 that is a critical path and that is helping that helps us to identify the critical portions which can be improved for better timing or and effectively better layout. So, this is how the timing analysis can give feedback to the layout automation algorithms let me just see yeah. So, I did not show the slack, slack were just the differences between the R and A. I am not describing this formally I am just wanted to bring out the intuition and the insights it is something quite simple. So, you will most encouraged to read of the book the book by Cahang Linig, Marko and who that title various physical design from graph algorithms graph partitioning to timing closure. The in fact the last chapter of this book is on timing closure bulk of the book is about physical design and last chapter tells you how timing analysis interacts or what kind of role it has in the context of physical design automation and so on. So, this is there are some more interesting ideas there is the timing analysis again is a big subject by itself with lot of interesting research contributions it should appeal to you are most encouraged to take a look at it and with help of a specific course on various I can.