 So, up to now the logic that we have been using has a continuous drive to the load all the time. That means if the output is a 1 or it is a 0, then it is continuously driven to 1 or 0 by some drive, okay. Now, there is a particular style of logic which is possible only with CMOS. So, the original logic styles which developed in MOS followed the bipolar style and those styles were continuously driven styles. Those CMOS added this extra thing of low power by making sure that if pull up and pull down are there, then only one and exactly one of them will be on at a time. The natural question then arises that you have a pull up and you have a pull down. So, there are four combinations of these two, on and off, right? So, we have allowed only two combinations. That is to say the pull up is on and the pull down is off or pull up is off and pull down is on, right? And that makes sense that if you say to drive to 0 or 1, this is what you should do. But what happens in the other two cases? Now, obviously both of them being on is destructive, right? If pull up and pull down both are on, then power will just go from VDD to gram. So, that is not useful. But the other combination is what dynamic logic uses. That is to say what happens if neither is on. So, if both of them are off, what happens is that in case of MOS devices, no current is drawn from these nodes. And therefore, these nodes can retain for a pretty long time the status of 1 or 0 on that node, okay? There are only capacitive loads. The outputs go only to gates of transistors. So, there is no DC drawn. And once you charge up a particular node to a 1 or a 0, then if both the drivers are off, then that node will retain its value of 1 or 0. This is called dynamic logic. This is how DRAM works, for example. But essentially rather than using a latch for storage, you can just use a capacitor for storage, okay? Now, this is extremely advantageous if it can be used because a latch takes a lot of space and consumes power. Whereas a capacitor takes very little space. In fact, you do not add a capacitor. Just the parasitic capacitances provide the storage. You do not actually lay out a capacitor. So, therefore, simple circuits, similar to very similar to CMOS logic, not needing a new technology, can now be built which will consume very little power. And the only requirement is that they should not be left undriven for long periods of time. Because if you do not drive it for a long period of time due to parasitic leakage and so on, a node which has been charged to 1 might eventually leak down to 0 and may cause errors. So, as long as you can make sure that these things are driven pretty frequently, then there is no problem. And now you can reduce the area required for implementing a function and you can also reduce the power that this circuit will use. That is the basic idea behind all the dynamic circuits, okay? So, essentially some nodes are required to hold their logic value as a charge stored on a capacitor. Now, here is an example. Essentially what we have done is that we have taken a CMOS inverter, okay? So, you see the PMOS there and you see the NMOS here, okay? So, this is just like an inverter and this by itself will ensure that only at a given time both pull up and pull down cannot be on. Right? Remember there were 4 combinations. So, this one will rule out both being on at the same time. Because if the clock is high, then this guy is off. If the clock is low, then this guy is off. So, there is never a direct path from VDD to ground which is nice, okay? Now, in addition to that we have borrowed from CDO NMOS and we have that same logic style. So, from the output node towards ground we have inserted a switch combination which follows the rules that we had earlier described, okay? So, as you can see this will be A plus B because they are in parallel dot C because C is in series whole bar, okay? So, this will then implement this A plus B dot C whole bar, okay? Now, the way it works is the following. When the clock is low, then this guy is off and this is on. Because this is off, there is no current in this direction, there is current cannot flow in this direction. Whereas, this is on. So, as a result this capacitor gets charged up to VDD, okay? So, this capacitor is unconditionally charged to 1. Then when the clock goes high, this charging stops. This transistor turns off. This transistor now turns on and depending on the values of A, B and C, the output if as a whole this switch is off then the output will remain charged to 1. If as a whole this switch is on, in this particular case either of A and B must be on and C must be on, right? So, if that condition is true then the output will be discharged to 0 through this path, okay? So, this works nicely now. No current just like CMOS. This is a low power technology. But the point is that if the output is supposed to be 1 then there is no discharge. If the output is supposed to be 0, it is conditionally discharged to the output, okay? This kind of logic is called dynamic logic. Very often we include a clock which makes sure that this charge is refreshed, okay? Suppose the output is supposed to stay 1 for a long time then what happens is that this pre-charge will not take any power actually. You might think that this is wasting power by charging and discharging a capacitor unnecessarily. But if the output is supposed to be a 1 then it is already charged up to 1 last time and it was not discharged. So, if this transistor comes on during the low phase of the clock, so what? This capacitor is already at VDD. This is also at VDD. Therefore, even though this gate is turned on when the clock goes low, no current flows. No current is drawn from VDD. So, as a result no power is actually wasted. This is discharged only when it must be discharged to make it equal to 0, okay? So, this is a useful style of logic implementation. Notice that now we have that advantage that each output now goes only to an n-channel transistor, okay? So, therefore the capacitance is lower than in CMOS and therefore the dynamic power is lower, okay? In CMOS this output would have gone to a PMOS as well as NMOS. Whereas now inputs are only NMOS. NMOS transistors are smaller than PMOS transistors because of higher mobility. So, capacitor is inherently smaller and on top of that only one transistor needs to be driven, not both. So, as a result the dynamic power is also reduced, okay? So, I will just introduce an very interesting tussle which has occurred in design styles and that is this. See the static power is whatever it is. It is some constant as a function of frequency, right? If your signal frequency changes, the static power will not change. Static power remains. It is just a leakage power. On top of that the dynamic power that is given by C V squared F, okay? Now for a given implementation V is constant and for a given gate C is constant whatever its load with respect to frequency. So, as a result the power has this kind of behaviour with frequency whereas this is the static power and the dynamic power increases linearly with frequency, okay? Now the idea is that I want to reduce this power and there are various approaches to reducing this power. So, one thing is that I can bring the whole thing by reducing static power, okay? And that is what CMOS does. So, it reduces static power to zero, right? The other thing is that you reduce the slope of this curve, okay? Now what determines the slope of this curve? C V squared, right? That is the slope. Therefore, you reduce voltages which is why you have scaled down technologies or you reduce C. Now reducing C means good layout, etc., etc., but you can go only that far. Reducing V, there is a particular voltage that you have chosen for operation, etc., etc. So, you would use as low a voltage as possible but remember that reducing V reduces the speed. Remember this was the trade-off that we did when we did the logic. So, as a result, you can reduce V but only up to a limit, okay? Now interestingly, many modern integrated circuits actually operate different parts of the IC at different voltages. So, what they do is that if some portion need not work at the highest possible frequency, then they give it a clock which is divided by a lower clock and at the same time reduce its voltage. That way, at least that part of the circuit consumes less power, okay? And very advanced power management techniques need to be employed, otherwise none of the modern ICs will actually work. So, that is called dynamic voltage switching and you then have to have circuits which will translate the output of a low power supply module to a high power supply module, okay? But coming back to the dynamic this thing, the other thing is that this frequency is actually the average rate of switching. One other technique is to reduce the rate of switching called the activity factor, okay? Now, the disadvantage that the dynamic circuits have is that the activity factor is very high. That means switching takes place at every clock, right? And the clock is the highest frequency signal. So, therefore it has a slight disadvantage. But on the other hand, it has the great advantage that this value of C is very low. The load capacitance is very low. Why is it low? Because it is going to only one transistor. Now, typically P MOS to N MOS ratio is 2 is to 1, right? So, the total loading is like 3 in case of C MOS. In this case, the total loading is like 1 because there is only an N MOS. So, you have a 3 is to 1 advantage in the capacitance. Now, you might say that look great capacitance is a very small part of the load. The actual load is from the interconnect capacitance. But even there, this has a great advantage because the N well is far away. Therefore, if you have to take a line to N MOS as well as to P MOS which has to be far away because the two wells have to be isolated. The interconnect capacitance is also very high in case of C MOS. So, you have a minimum gain of a factor of 2 in interconnect and a factor of 3 in gate capacitance, okay? So, you gain by a factor of somewhere between 2 and 3. If you use dynamic circuits, okay? So, essentially what we are trying to do is that C MOS static reduces this but cannot do anything about this slope. Whereas, C MOS dynamic can reduce this and can reduce this slope substantially. Unfortunately, it has to operate at a high point here, okay? So, if your signal itself requires switching very often, then there is nothing lost in having a high activity factor and those are the conditions in which dynamic logic is most important, okay? So, you got the motivation of going to dynamic logic otherwise why should we bother? The C MOS is supposed to be low power and so on. But what really happens is that C MOS looks like this. Its static power is nearly 0 but the slope of this line is very high, okay? Because the capacitance is very high. So, everything to the right of this intersection point favors dynamic logic and everything to the left of this intersection point favors static logic, okay? Now, it is the effort of the static logic designers to push this point as far to the right as possible. So, that static logic is optimum. And it is the effort of dynamic logic designers to reduce this slope and thus push this point to the left as possible. So, that dynamic logic is the optimum choice, okay? So, both camps then try to optimize their design styles and of course we are impartial, we will learn both. So, we have spent some time learning static and now we should see how the dynamic logic operates, okay? This provides the motivation for learning dynamic logic. However, for this to be successful, the circuit has to work. If it does not work, then all bets are off, right? Then who will use this? So, there unfortunately happens to be a flaw with this circuit. It looked very impressive when we analyzed it but there is a particular flaw with this circuit where in certain circumstances it will cause problems. So, let us see what are those circumstances. When you cascade this logic, single stage works perfectly as we had discussed. But if you cascade this logic, then we have a problem, okay? So, let us consider this case in which we have that same old logic stage which we had which was A plus B dot C whole bar, okay? And we are giving it to an inverter. Inverter is the next stage, alright? Now, this is the waveform for the clock, alright? And now, let us consider the waveform at X. Now, if A plus B dot C is false, then there is no problem, okay? Why there is no problem, alright? When the clock is low, this node X charges up, okay? Now, because A plus B dot C is false, that means either both A and B are 0 or C is 0, then there is no discharge path. So, this output remains put at 1. Okay? Because this remains put at 1, at the same time that this guy got charged up, this guy will also get charged up here when the clock is low, right? So, when the clock is low, this output charged up and because this is 1, right? This one, this will, when the clock goes high, this will discharge, right? So, as a result, the output will be 0, which is what you want. This is after an inverter. So, therefore, this should give you A plus B dot C. Since A plus B dot C is false, the output should be 0, okay? So, when A plus B dot C is false, there is no problem, okay? Just to go over this very quickly. During pre-charge, both these capacitors charge up, okay? Because A plus B dot C is false, this capacitor remains charged high, okay? As a result, when the clock goes high and this lower transistor turns on, because the input is high, this capacitor is charged through this path and as a result, the output goes to 0, which is what we expect. No problem here. The problem comes in the other case. When A plus B dot C is in fact true. In that case, what happens? As before, when the clock is low, both of these charge up, okay? When the clock goes high, that is when problem occurs. When the clock goes high, now this transistor is on and this transistor is on. Now for quite some time, this output will remain high, right? So, it will start discharging. But at the same time, this guy is sampling X and it will start discharging this output to ground. Now depending on the time that this stage takes to discharge this capacitor, this capacitor will be wrongly discharged. It was never meant to be discharged because this output was supposed to be 0 and therefore this guy was supposed to be off. But because the sampling takes place at the same time and for some time, this guy is not valid. So, that invalid value leaks away this charge and depending on how much leakage is there, this might remain at 1 and be restored the next time or may become 0. So, therefore this circuit will actually fail. So, what do we take out from here? That the circuit is quite promising, but on the other hand there are problems with it and that problem is non-symmetric. If the input is inactive, that means for an N switch, if the input was not changed, that means if the output of the previous stage was 1, then there is no problem. But if the output of the previous stage was supposed to be 0, then because for some time it is invalid, that causes problem to the output. So, this is the problem with cascading of a simple-minded dynamic logic that we had constructed at that point. So, obviously we need some correction to this and there are two separate ways of correcting this. We will look at both of these ways. Now, one way is after we analyze why is this problem occurring? This problem is occurring because in this stage the power supply has already been turned off, the p-channel has been turned off when the clock goes high. Now, if the input is active, that means if the input is 1 wrongly, then that will cause problems. If the input is 0 wrongly, then there is no problem, right? Because if the input is 0 wrongly for some time, that means this guy does not discharge this, but when the input becomes 1, then it will discharge it, right? So, that is not a correctness problem, that is a timing problem, right? So, that is an asymmetric problem. I hope you have followed this, that this problem does not occur for both combinations of logic, okay? It occurs when the input is wrongly 1. If it is wrongly 0, there is no problem because eventually it will become 1, though for some time it is 0 and being at 0 for some time does not cause any problem to the output, okay? So, essentially the tap is off, so you are not wasting anything. When the tap comes on, it is fine, you will do whatever you need to do. But if the tap is wrongly off and your storage of water is limited, then you may empty out your tap. So, the water being left on wrongly is a problem, the tap being left off wrongly is not a problem, okay? So, eventually you will turn the tap on, alright? So, therefore there are two solutions. One is that the problem is that this guy is by default 1. Why not make it by default 0? Then there will be no problem. That is one solution, okay? The other solution is that the problem is that we have been too hasty in connecting these two guys. If this guy had started sampling only after this guy had settled down two values, there would not have been a problem, right? So, these are the two parts to correcting this problem. One is to insert a time slot in between giving the time for the previous stage to stabilize and only then connect it to the next stage. Then there is no problem, okay? The other thing is that do not have the dangerous logic level as the default level. Do not pre-charge it to 1. Pre-charge it to 0 and conditionally charge it to 1. Then if it is wrongly 0, no problem. Eventually it will come to its right value and then you will evaluate the outcome. So, two different logic families have developed as a result of following these two different ways of correcting the problem, okay? Let us look at those. The first one is a four-phase dynamic logic. Obviously, this two-phase clock will not do. You need an extra phase of the clock at least to insert for completing the evaluation, okay? So, at least a three-phase clock is required. There are three-phase clock solutions. We are looking at a four-phase clock here because it has some advantages, okay? So, what happens? You have actually four clocks which are on only in phase one, phase two, phase three or phase four, okay? These are non-overlapping clocks, okay? So, clock one is on during phase one, the first quarter. Clock two is on only during the second quarter. The clock three is on only during the third quarter and clock four is on only during the fourth quarter, okay? And then after in the next, the clock one comes again, okay? So, essentially you have these phase clocks like this, one-two-three-four, one-two-three-four, right? So, you have four clocks. And now you can construct complex clocks. For example, clock one-three is a clock which is the ore of clock one and clock three, okay? Which will be on during one and three. Clock one-two, clock two-three, such clocks can be constructed, okay? This is the complication of multi-phase logic. But once you assume that the appropriate clocks will be taken to different logics, then the problem gets solved, okay? Now, notice what we do. You have a pass gate here, okay? So, this is our old friend, a plus b dot c. Same circuit we have analyzed it. There is not much problem, okay? Now, we are using this complicated clock, okay? So, rather than giving clock here, we give it clock one-two-bar. Now, this is only a complication in name. It is a same old clock actually. What do you mean by clock one-two-bar? This is a clock which is zero in one and two. And it is one in three and four. So, it is the same old clock actually. It is just two periods wide, right? So, nothing has really changed. We are just calling it by a new name, okay? Because half the clock period it is off, half the clock period it is on. So, really not much has changed here, alright? So, clock one-two-bar gets applied here. Now, let us go phase by phase. In phase one, what will happen? The clock is higher low, one-two-bar. Therefore, it is low in phase one. So, in phase one, now this switch is clock two-three, right? This is on only during two and three. So, in phase one, this is actually off. This switch is off, okay? And this transistor is on because the clock is low and this switch is off, okay? This everybody agrees? In phase one, this clock is low. As a result, this guy is on and it charges up this capacitor, okay? This is the pre-charge phase. That is all that happens in phase one, okay? Now, we go to phase two. In phase two, this guy is still on, clock one-two-bar and this guy is still off. But now, this guy is closed. As a result, this capacitor also charges up, okay? So, as a result, both these capacitors are now charged high at the end of phase two. What happens in phase three? In phase three, this clock goes up now, okay? So, this transistor shuts off. This transistor comes on, okay? And these two capacitors are in parallel because this phase three, this is on. So, this combined capacitor is now evaluated by A plus B dot C like before, okay? So, now at the end of phase three, phase three is that safety phase in which nobody is looking at you, okay? So, at the end of phase three, the evaluation is complete. Then, in phase four, what happens? This switch goes off. Whereas, this is still on, right? So, phase four, this output retains its value, which is valid, okay? And it will also retain it during phase one. Remember, this one will be pre-charged in phase one. So, essentially, this circuit evaluates in phase three and its output is valid in phase four and phase one, okay? This is somewhat like noise margin. That means the input needs to be valid only in one phase of the clock. But the output is valid in two phases of the clock. So, the output is more generous than the input in timing sense, okay? Input needs to be valid only for one phase of the clock. The output is valid in two phases of the clock and this type of gate is called type three, okay? Type three gate is one which evaluates in clock phase three. The output is valid in four and one, okay? So, this is the four phase logic. And now, all gates have a restriction. So, you have type one gate, you know, just by cyclically permuting these clocks, you can make type one, type two, type three and type four gates. Now, notice, type one gate evaluates in clock one. And when is it valid in two and three? The two subsequent phases, it is valid, right? When it evaluates, then in two subsequent phases, it remains valid. So, therefore, type one can drive a type two gate and a type three gate, correct? Similarly, a type two gate can drive type three and type four. Three can drive four and one and four can type one and two, right? So, as a result, when you distribute logic, you make sure where the input is coming from, okay? And you have to make sure that the input is coming from the correct type of logic. Only then will it work properly. The other input, other technique, makes use of the other factor. That is to say, to en masse, a wrong one is dangerous, but a wrong zero is not dangerous, okay? So, then what we say is that, alright, I will put a static inverter here, okay? Now, when this is pre-charged to one, the output will rest at zero, right? That is not dangerous to the next stage. And then, when it conditionally discharges, should it go to zero, output will become one, okay? So, that seems to solve the problem. Then why do we bother about that four phase clock at all? It introduces a very bad problem. What is that problem? Our original logic was inverting. Now, this has become non-inverting logic, okay? You cannot produce functions which are non-inverting because of this extra inverter. Now, any function can be constructed out of inverting logic. But you cannot construct any old function with non-inverting logic, right? So, now the problem is that if my logic needs an inverting logic, where am I going to get it, okay? So, this is very often true in this business. You solve one problem and it unleashes another problem on you. This is the second problem that we now need to solve, okay? However, it is not too bad to solve because after all, who says that these switches must be N-MOS? You can use P-MOS switches, okay? And while a one is dangerous to N-MOS, a zero is dangerous to P-MOS. So, if you do not want to put an inverter here, make sure that this output goes to P-switches. And the output of that goes to N-switches, okay? So, you have, ultimately, like in the previous case, P-switch cases, N-switch cases, P-switch cases, N-switch cases alternately, okay? That logic is called NORA or zipper logic, okay? It works like a zipper. If you have ever examined how a zipper actually works. So, there are these hooks from both sides and a hook engages from this side, then a hook engages from this side, then a hook from this side. So, that is like a zipper. So, you essentially have, notice that here, these are P-MOS switches. The output is pre-discharged by the clock in the same phase while this is charging. And this output is presented to P-MOS switches, which conditionally charge, okay? You just inverted ground and VDD and change N-MOS to P-MOS. So, if this output is wrongly one, that is what it can be. It can never be wrongly zero. If this output is wrongly one, it will just hold the switch off for some time. Then when it becomes zero, this will turn on, okay? So, this will evaluate correctly. So, this kind of logic is called zipper logic and sometimes it is called NORA for no-race conditions, okay? There is lots of tasty stuff to be done for dynamic logic. But this introduction to dynamic logic now will suffice. Now, we will stop here. And then we will go over to the little discussion on HDL, largely for motivation of HDL, meaning a generic discussion of HDL rather than specifically VHDL or very long.