 Hello and welcome to this presentation of the STM32 Flexibles Memory Controller. It covers all the features of this interface which is used to connect external memories such as NOR Flash, SRAM, PSRAM and NAND Flash memories. The FMC controller integrated in STM32 MP1 microprocessors provides the external memory support through two memory controllers. The NOR Flash PSRAM memory controller and the NAND Flash memory controller. This enables the CPU to communicate with the external memories including NOR and NAND Flash memories, PSRAM and SRAM. This interface is fully configurable, allowing easy connection with external memories or other parallel interfaces. The benefits of the FMC controller include not only RAM and flash memory space extension, but also the ability to interface seamlessly with most LCD controllers which support Intel 8080 and Motorola 6800 modes. This LCD parallel interface capability makes it easy to build cost-effective graphic applications using LCD modules containing embedded controllers or high performance solutions using external controllers with dedicated acceleration. The mapping of the FMC bank addresses is fixed. Bank 1 is used by the NOR PSRAM memory controller. Bank 3 is used by the NAND memory controller. All other banks are not used by the flexible memory controller and are available to the SOC memory map. The FMC controller offers four independent banks to support separate external memories. Each bank has an independent chip select and an independent configuration. Each bank features programmable timings, a configurable 8, 16 or 32-bit data bus, and can access memory in asynchronous or burst mode for synchronous memory such as NOR Flash and PSRAM. Synchronous memory can be accessed at a maximum frequency of HCLK divided by 2. The FMC controller supports a wide variety of devices and memories. It interfaces with static memory mapped including static random access memory or SRAM, read-only memory or ROM, NOR or one NAND flash memory and PSRAM. Furthermore, the FMC interfaces with parallel LCD modules supporting the Intel 8080 and Motorola 6800 modes and is flexible enough to adapt to various LCD interfaces. The FMC outputs a unique chip select signal to each bank and performs only one access at a time to an external device. The external memories are connected either to the NOR PSRAM controller or the NAND controller and share address, data and control signals. The NOR PSRAM controller allows the configuration of various timing parameters for the supported memories. Address setup phase, duration of the first access phase. Address hold phase, duration of the middle phase of the access cycle. Data setup phase, duration of the second access phase. Bus turnaround phase, duration of the bus turnaround phase. Clock divide ratio, number of AHB clock cycles or HCLK within one memory clock cycle or CLK. And data latency, number of clock cycles to be issued to the memory before the first data transfer access mode. The FMC controller features a NAND memory controller supporting up to two NAND devices of the same type and a common ready busy signal, programmable page size up to 8 kilobytes, programmable timing parameters and 8-bit or 16-bit interface. The NAND memory controller has a hardware error detection and corrections supporting hamming code, one-bit correction per page and BCH code with either 4-bit correction or 8-bit correction per 512 bytes sector. The FMC also interfaces with NAND flash memories and supports error code correction or ECC for up to 8 bytes of data read or written. Three interrupt sources can be configured to generate an interrupt when a rising edge, falling edge or high level is detected on the NAND flash ready busy signal. Bank 3 is used to interface with the NAND flash memory. It is divided into two memory spaces, common memory space and attribute memory space. Both spaces are similar. The common memory space is for all NAND flash read and write accesses, except when writing the last address byte to the NAND flash device where the CPU must write to the attribute memory space. This allows you to implement the pre-weight functionality needed by certain NAND flash memories by writing the last address byte with different timings. Each memory space is subdivided into three sections. Data section, 64 kilobytes, used to read or write data from NAND flash memory. Command section, 64 kilobytes, used to send a command to NAND flash memory. And address section, 128 kilobytes, used to specify the NAND flash memory address. The NAND device, NCE1 and NCE2 is decoded according to the address bit 24, 16 megabyte range. Each common and attribute memory space can be configured with different timings for the NAND flashes command, address write and data read write accesses. The attribute memory space is used for the last address write access if the timing must differ from that of previous accesses in case of ready busy management. Otherwise, only common space is needed. Four parameters are used to define the number of HCLK cycles for the different phases of any NAND flash access. Setup time, hold time, wait time and data bus high Z time. Three additional parameters are used to control the timings for the address to read delay, the command to read delay and the minimum chip select high duration. The FMC generates the appropriate signals to drive NAND flash memory. The address, data and control signals are shared with the NOR-PSRAM controller. The command latch enable or CLE and address latch enable or ALE signals of the NAND flash memory device are driven by address signals from the FNC controller connected to address line 16 and address line 17 respectively. The ALE is active when writing to the address section and the CLE is active when writing to the command section. The FMC NAND memory controller includes support for the following features. Error correction code. The ECC algorithm can perform one-bit error correction and two-bit error detection per 256 to 8192 bytes read or written from or to the NAND flash memory. It is based on the Hamming coding algorithm. Three interrupt sources can be enabled to detect a rising edge, falling edge or level on ready or busy signal output from NAND flash memory. Weight feature management. The controller waits for the NAND flash memory to be ready before starting a new access. The MPU memory attribute of the FMC NAND bank must be configured as a device. The NAND controller offers three interrupt sources. Rising edge, falling edge and high level detection on the FSMC INT pin when it is connected to the ready busy signal from the NAND flash memory. The available Hamming code can perform one-bit error correction and two-bit error detection per 256, 512, 1024, 2048, 4096 or 8192 byte access from or to the NAND flash memory. It consists in calculating the row and column parity. This algorithm is supported by 8-bit and 16-bit NAND flash memories. To increase the error correction capacity, the FMC embeds a BCH or Bose Chowdery and Hock-Quingaman coder and decoder. It supports either 4-bit error correction with 8-bit error detection per sector or 8-bit error correction with 16-bit error detection per sector. The BCH encoder decoder module handles sectors of fixed size equal to 512 bytes. The error correction code or ECC controller can use one of two algorithms, Hamming or BCH, depending on the ECC requirements of the NAND flash device. The controller works at page level for reading and or programming the NAND flash memory data located in the main array and parity bits in the spare array, also known as OOB. The controller can use one of two modes, Direct Mode with CPU polling, applicable with any ECC or Automatic Mode with a sequencer and DMA transfers, applicable only with the BCH algorithm. To program a page in Direct Mode, enable the write access and the ECC computation. Write the 512 byte sector to the NAND flash page. While the sector is written, the BCH encoder computes the ECC value. Wait until the BCH code is ready. Copy the ECC value to the NAND flash out of band or OOB area. Repeat the previous steps for all sectors of the page and launch the page programming. To read a page in Direct Mode, enable the read access and the ECC control. Read the 512 byte sector to the NAND flash page. Read the ECC parity bits, 7 or 13 bytes from the NAND flash out of band or OOB area. During the reading phase, the BCH syndrome is calculated. Then the error location information is processed to detect potential errors. Wait until the error detection is completed. From the error decoding results, the software can correct the sector when it is possible. Repeat the previous steps for all sectors of the page. Data and ECC byte accesses can be managed automatically by the FMC command sequencer using DMA channels for the data transfer. One DMA channel is required for write operations and two DMA channels for read operations. The sequence is performed at page level, each page being one or several 512 byte sectors. The error correction is applied to each sector with the redundant bits located in the spare array. The NAND flash controller sequencer can perform one operation after another to program a complete page without any software intervention. For each 512 byte sector in the page, the sequencer sends the command and the address to the NAND flash main array. This requires only one DMA channel. Triggers a DMA request to write data to the NAND flash main array. While data are written to the main array, the parity bits are computed by the BCH engine. Sends the command and the address to the NAND flash spare array. And writes the parity bits to the NAND flash spare array. Once all sectors are written to the main and spare arrays, the sequencer generates the completion interrupt to the host CPU to issue a page program command to the NAND flash memory device. The software overhead is only one interrupt per page. During the interrupt, the next page can be programmed in the sequencer. The NAND flash controller sequencer can be pre-programmed to perform all operations to read a complete page without any software intervention. For each 512 byte sector in the page, the sequencer sends commands and addresses to read the NAND flash main array and the associated parity bits located in the spare array. This requires two DMA channels. Triggers a DMA request to copy data from the main array to a memory buffer. The sequencer keeps the data read access and the DMA transfer in sync. While data and parity bits are read, the BCH engine computes the error location polynomial to determine the potential presence and position of bit errors. This information is then recorded in an error log. When the error log is ready, the sequencer generates a DMA request to save the error log for this sector. Once all sectors are read, the sequencer generates a completion interrupt to the host CPU to process the error log and correct the erroneous bits in the memory buffer. The software overhead is only one interrupt per page. During the interrupt, the next page can be programmed in the sequencer. The FMC is active in run and sleep modes. An FMC interrupt can cause the device to exit sleep mode. The device is not able to perform any communication in stop and standby modes. It is important to ensure that all transmissions are completed before the FMC controller is disabled or the domain or system is switched down to stop or standby modes. To retain external SD RAM memory data while in stop or standby modes, it can be put in the self-refresh mode prior to entering stop or standby modes. Here is a list of peripherals related to the FMC interface. Users should be familiar with all the relationships between these peripherals to correctly configure and use the FMC controller.