 Hello and welcome to this presentation of the STM32 Nested Vector Interrupt Controller. We will be presenting the features of this controller. The interrupt controller belongs to the Cortex-M4 CPU, enabling a close coupling with the processor core. The main features are 63 interrupt sources, 16 programmable priority levels, low latency exception and interrupt handling, automatic nesting and power management control. Applications can benefit from dynamic prioritization of the interrupt levels, fast response to the requests thanks to low latency responses and tail chaining as well as from vector table relocation. The nested vector interrupt controller provides a fast response to interrupt requests, allowing an application to quickly serve incoming events. The STM32WB implements more than 63 interrupts. Some interrupts are combined on the same nested vector interrupt controller vector. By reading the peripheral interrupt register, the software can determine the peripheral that requested the interrupt. The priority assigned to each interrupt request is programmable and can be dynamically changed. The interrupt vector table can also be relocated, which allows the system designer to adapt the placement of interrupt service routines to the application's memory layout. For instance, the vector table can be relocated in RAM. Software is in charge of assigning a priority level to each interrupt, as well as to all exception sources excluding a reset, as well as to all exception sources excluding a reset, non-maskable interrupt and hard fault. Whenever a peripheral interrupt is requested at the same time, a supervisor call instruction is executed. The relative priority of these hardware and software exceptions dictates which one is handled first. Regarding the STM32WB microcontroller, a non-maskable interrupt or NMI is caused, either by an SRAM2 parity error, a flash double ECC error or a clock failure. The priority of any of the 63 peripheral interrupt requests is programmable in a dedicated priority field located in the Cortex-M4 nested vector interrupt controller registers. The nested vector interrupt controller provides several features for efficient handling of exceptions. When an interrupt is served and a new request with higher priority arrives, the new exception can preempt the current one. This is called nested exception handling. The previous exception handler resumes execution after the higher priority exception is handled. A microcode present in the Cortex-M4 automatically pushes the content to the current stack and restores it upon interrupt return. When an interrupt request with lower or equal priority is raised during execution of an interrupt handler, it becomes pending. Once the current interrupt handler is finished, the context saving and restoring process is skipped and control is transferred directly to the new exception handler to decrease interrupt latency. So back-to-back interrupts with decreasing priorities or higher priority values are chained with a very short latency of only a few clock cycles. When an interrupt arrives, the processor first saves the program context before executing the interrupt handler. If the processor is performing this context saving operation when an interrupt of higher priority arrives, the processor switches directly to handling the higher priority interrupt when it is finished saving the program context. Then tail chaining is used prior to executing the IRQB interrupt service routine. When all of the exception handlers have been run and no other exception is pending, the processor restores the previous context from the stack and returns to normal application execution. When accessing the nested vector interrupt controller registers, ensure that your code uses a correctly aligned register access. Unaligned access is not supported for nested vector interrupt controller registers as well as all memory mapped registers located in the Cortex-M4. An interrupt becomes pending when the source asks for service. Disabling the interrupt only prevents the processor from taking that interrupt. Make sure the related interrupt flag is cleared before enabling the interrupt vector. Before relocating the vector table using the VTOR register, ensure that fault handlers, NMI and all enabled interrupts are correctly set up on the new location. In the dual core STM32WBMCU which embeds a Cortex-M4 application core and a Cortex-M0 plus radio core, the peripheral interrupts are connected to both cores. To prevent unwanted interruptions, the interrupts mapped on the Cortex-M4 nested vector interrupt controller and having multiple peripheral interrupt sources can be preliminarily masked in the system configuration controller or SYSCFG. The SYSCFG interrupt mask registers ensure that only the wanted interrupt sources are forwarded to the Cortex-M4 nested vector interrupt controller. The peripherals impacted are listed. The nested vector interrupt controller is linked with the SYSCFG module and the Cortex-M4 CPU. Please refer to the related presentations. For detailed information, please also refer to the programming manual for the STM32F3, F4, L4 and L4 plus series and the reference manual of the STM32WB.