 Today we are going through 18th lecture which is continuation of application of signal processing activities of the op amp in terms of negative feedback. We had in the last class let us see discussed the basic signal processing activities like buffer stage, unity gain amplifier, non inverting amplifier design, trans resistance amplifier design, trans conductance amplifier and current control current source design, summing amplifiers and difference amplifiers as an application of the difference amplifier we went for instrumentation amplifier which is the most common amplifier used in instrumentation setups for measuring force, velocity, pressure variation using these bridges, sensor bridges, strain gauge bridges. We have 2 and 3 op amp versions of these instrumentation amplifiers and we had discussed how common mode gain of that topology can be determined based on the tolerance of resistances used in the instrumentation amplifier setup. Under that assumption it is assumed that common mode gain contribution comes mainly from the resistive mismatch in the difference amplifier. It is assumed that the op amp contribution for the common mode gain error is negligible compared to that caused by the resistance mismatch. Differential mode gain evaluation of this and common mode rejection ratio which is nothing but the ratio of the differential mode to common mode gain which is represented as rho. So these are the ones that were discussed and I had given you a problem on 2 op amp instrumentation amplifier evaluation of the differential mode gain and common mode gain. We can apply VB equal to for example minus VD by 2 and VA equal to plus VD by 2 and then what happens is this becomes minus VD by 2 and this becomes plus VD by 2 and this will now have a current which is made up of VD across it okay divided by R dash. So VD by R dash is the current okay and to that this current gets added okay this current is going to be VD by 2R okay. So these two currents will sum up and go through this and establish a potential here which is minus VD by 2 and the drop across this that drop. So that is the voltage at this point okay and the current in this can be then evaluated current this is already known. So this current is then established and this voltage is then obtained as the AD into VD right. So AD into VD this is the differential mode voltage so AD is going to be then obtained as 2 into 1 plus R by R dash that is the differential mode gain okay. Then we can actually apply the common mode voltage to this and then establish what the common mode gain is so if this then becomes VC this also is VC this is VC and this is VC. So now there is no current in this due to the common mode voltage because there is zero potential across this so no current in this. So only these resistances come into picture and it can be established that it depends upon the ratio of these resistances that exactly equal to 1 okay the nominal value as shown here then the common mode gain is zero because of the tolerance of these four resistors it is going to depend upon the tolerance delta and AC can be shown to be equal to 4 delta instead of the 2 delta that we obtained for the 3 instrumentation type we have here this as 4 delta it is therefore slightly disadvantageous to use this for the same common mode differential mode gain this as a poor or CMRR than the 3 op amp version. Obviously this is not a symmetric structure a symmetric structure is always preferred structure of the present day ICs okay and matching is better in these cases and common mode detection is better in a symmetric structure and therefore it is better to use a symmetric structure than an asymmetric structure like this for instrumentation setups okay next effect of finite gain mended product of these op amps are the same as what happens in the earlier feedback amplifier design. So in for example let us take a general sort of summing amplifier topology where we had put these feedback resistors for different voltages to be summed up so we had chosen this as alpha 1 R by alpha n so this is V1 to Vn so if you have such number of resistors put for a variety of number of voltages at the input for summing action then the feedback factor keeps on changing because of this so we have this effect of the gain due to this feedback composite feedback caused by all these resistances so is going to be equal to if this is let us say GB by S open loop gain then the loop gain is GB by S into the attenuation factor of due to all these feedback resistances that is that can be shown to be equal to actually ideal gain which is actually speaking for different voltages we have it as V1 into let us say alpha 1 Vn into alpha n sigma of all these voltages that is the summing action that has taken place with the negative sign that we had already shown. Now what happens due to the finite gain mended product okay of the op amp is that it is S by GB into 1 over the loop gain so GB by S into the attenuation factor is the loop gain so 1 over the loop gain becomes 1 plus alpha 1 plus alpha 2. So the actually the bandwidth decreases by a factor GB divided by 1 plus alpha 1 up to alpha n so this is a reduction of the bandwidth due to all the summing action right. So if you do not want to why did it take place mainly because we have a voltage to current conversion which is not really ideal conversion so the best thing for coupling with a trans resistor amplifier like this is a trans conductor getting different voltages as input and converting directly to current then the gain bandwidth product would have been just the GB. So for a trans conductor the trans resistor amplifier the gain mended product is just 1 by 1 plus S by GB or it is R divided by 1 plus S by GB that is the transfer function. So this method of conversion of voltage to current is not appropriate if you do not want the gain bandwidth the bandwidth of the whole amplifier stage to be reduced because of this. Now let us also consider how an instrumentation amplifier has to be designed based on the transducer that is going to be connected to it. So this is the familiar bridge arrangement for measuring the variation due to resistance occurring because of pressure pressure gauges right strain gauges. So we have balanced condition with this R, R, R and R the common mode voltage will be nothing but VC by 2 these 2 voltages will be the same that will be pretty large in order to have the sensitivity of the bridge large because that directly determines the sensitivity of the bridge. So when delta R change occurs okay in the bridge then we see that the differential mode voltage that is occurring across this is going to be VS into delta R divided by 2 RS plus R. The common mode voltage at this point when it is balanced is going to be VS into R okay divided by 2 RS plus R okay effective change in resistance here is 0 because this changes by delta R negative and this is positive. So effectively change in resistance is 0 and therefore current remains the same okay at all times. So we have this as common mode voltage this as differential mode voltage and an instrumentation amplifier which is not having a perfectly matched structure will have a finite AC non-zero. So that we had seen because of tolerance of resistors used in the instrumentation amplifier. So the output of the instrumentation amplifier is going to be AD into VD which is wanted plus AC into VC which is the error right. So this error has to be minimized so actual value expected is AD into VD that into 1 plus VC divided by rho is nothing but AD by AC which is known as common mode rejection ratio. So it is VC by VD divided by rho that is the error. So that means in normal setups like this VC is very large compared to VD and therefore you must still have rho which is much larger than this VC by VD in order to make this error go to 0 compared to 1. So this is the method of designing okay the instrumentation amplifier for a given bridge arrangement with certain sensitivity factor. Data R by R is what is called as the sensitivity it is dependent upon the sensitivity of the sensor in this case may be a strain gauge okay. So this is what decides the instrumentation amplifier CMRR expected let us say. Now V naught of the instrumentation amplifier is ADVD plus AC VC and this is what is wanted and this is the error component 1 plus VC by VD divided by rho. So now this has to be kept very small let us say if it is expected to be 0.1% okay which is tolerated for the best sensitivity possible for us okay using the bridge then accordingly rho gets fixed. So let us try to solve instrumentation amplifier design problem instrumentation amplifier has to be designed to measure with the specified accuracy and specified change in resistance of the strain gauge. Let the change in resistance be 0.1 ohm that is the level up to which we want measure 0.1 ohm change in 100 ohm okay and the accuracy of measurement should be 1% for the instrumentation we assume that the entire error is due to the common mode rejection ratio. So the 3 op amp configuration is chosen for the instrumentation amplifier as it has superior CMRR okay 3DVMO in comparison with 2 op amp version and it is a symmetrical structure. So let us consider the 3 op amp design now AD is 1 plus 2 R1 okay divided by R dash this R1 okay AC is equal to 2 delta is the tolerance of R1 error is 1 by rho into R by 2 delta R that is what we have established that should be maintained okay better than 1% 1 by 100 delta by R by R is 0.1 ohm in 100 ohm that is the change we would like to measure. So that means 10 to power minus 3. So rho becomes it should be greater than 1 by 2 into 10 to power 5 is 1 by 100 into 1 by 1000 half of that so 97 decibels. So it should be greater than 97 decibels such an instrumentation amplifier you have to design or purchase okay chosen with CMRR better than 97 INA 103 for example costs $5 per unit for 1000 up quantities which has a minimum of 100 decibels which will suit fine as fine right. So R dash to be chosen for that design okay this has all the other resistances already fixed okay R1 for example is 3K that is already there internally we have to connect R dash externally. So R dash is to R1 by AD minus 1 R1 associated with INA 103 is 3K for AD of 1000 therefore R dash is 6 ohm so we have to accurately obtain the 6 ohm and connected at the point which is already pointed out in the IC. The bandwidth of for gain of 1000 is about 80 kilohertz as mentioned in the data sheet. So consider the design of INA given delta and CMRR okay we have to find the AD that is suitable for this for delta we want to build this instrumentation amplifier now okay using let us say op amps instead of going for INA 103 can we therefore build this for our specification with available resistor components that is 0.1% component as far as resistance is concerned tolerance okay of resistor. The op amp is chosen that is TL084 which as a CMRR of 80 dB that means much greater than what is required so we can use that because it is contribution for the error will not be coming into picture minimum AD is equal to 2 delta okay which is 2 into CMRR therefore is equal to 2 into okay delta 1000 into 1000 that is the so this is equal to 2 CMRR is 1000 from 60 dB so 2 delta into CMRR that is the AD required that is 2 so R dash is equal to 2 R1 R1 can be just 1K and then R dash is 2K so this is a instrumentation amplifier that we can design using TL084 okay so what is the consequence of this for a given AD and CMRR what is the delta right. The example 2 is can we therefore design every time such a design is left to us by selecting the proper op amp and the resistors. If AD is given and CMRR is given okay AD equal to let us say 100 okay CMRR is 120 decibels that is 10 power 6 then delta required becomes almost virtually difficult to get not commonly available 0.005% precision component has to be got which is difficult or it be very expensive. So we can as well use the IC which is available as instrumentation amplifier like NEM or 3 hours so let us now consider the trans impedance amplifier design integrator as the basic building block. Now instrumentation is one of the most important front end requirement in current day signal processing activities okay which improves the signal to noise ratio enormously because of here it is differential topology right all common mode signals get rejected because it has it is designed for a very high value of common mode rejection ratio. So the common mode signals like in the case of ECG waveforms etc the most common mode signal most important common mode signal that interferes within the band of the biomedical signal is the 50 hertz component. So common mode rejection ratio ability is an important criteria of the front end of biomedical setups and therefore instrumentation amplifier is a basic unit which improves the signal to noise ratio enormously typical value of common mode voltages which we had already seen in the introduction okay will be of the order of millivolts and the differential mode signal to be amplified is of the order of micro volts and therefore minimum of 1000 common mode rejection ratio okay is commonly expected with most of these instrumentation amplifiers better than 1000 okay. So integrator where is it coming into picture in building block approach integrator is the building block of most of the VLSI analog filters of today. So the building block approach is the most suited approach for VLSI design today and therefore a study of integrator and integration operation is the most of use linear operation okay in signal processing activity. So integrator is nothing but a trans impedance amplifier the capacitor is the integrator the current voltage relationship is voltage okay current through the capacitor is CDB by DT. So if you put a differentiator in the feedback loop of an op amp it should behave as an integrator inverse operation let us look at it. So current through the capacitor is CDV naught by DT voltage across the capacitor CDVC where DT okay and I am putting it in a feedback where this voltage is converted to current okay. So this is a current feedback this current follows this current input current output current follows the input current okay. So this is the current feedback that is occurring at this single node here. So CDV naught by DT is equal to I naught is equal to minus I this is the current fall over here. So V naught is equal to minus 1 over C integral I DT that is all. So V naught by I is equal to minus 1 over CS this is what happens with the integrator this voltage is a virtual ground this is grounded so this virtual ground this current flows through this totally because this is null later no current can be coming through. So this current is equal to minus I naught and that is CDV naught by DT and V naught by I is minus 1 by CS. So please remember that this is a integrator by virtue of the capacitor being put in the feedback path. Now however I can convert voltage to current roughly by because this input impedance is looking like a short circuit voltage is zero current is anything that passes through this okay. So it is acting like a short circuit so this VI if it is applied here always gets converted as VI by R current. So the current in this is VI by R that flows through this and develops a potential okay which is going to be V naught equal to minus okay this is zero so this is the drop 1 by C integral I DT. So this is turning back okay minus 1 by RC integral I DT. So let us look at this gain actually is going to be GB by SA is roughly equal to GB by S. So this itself acts as an integrator so in order to make an integrator okay out of it we are actually utilizing this. So let us see the effect of this finite gain bandwidth product of the op amp on the performance of this integrator of ours. So before that let us simulate this integrator with R equal to 1K and C is equal to 0.1 micro farad the op amp used is 741. Now you will see this is the input waveform that I have applied to this a square waveform okay. So an integration operation should convert it ideally speaking into a triangle. But what has happened is it has done it has done integration but with a lot of error and what is this error due to this is because of the finite DC gain of my which may be very high of the order of 10 to power 5 or 10 to power 6 but because of that okay and it has finite offset voltage offset typically for 741 may be of the order of few millivolts at the input and that offset simply gets amplified by the open loop gain it is DC unstable okay. Now what is integration operation it is 1 by SCR okay ideally. So that means it is DC gain is as much as the open loop gain itself right. So it simply amplifies offset voltages okay by that DC gain N naught and this is the effect of the offset there is no feedback because it is the capacity feedback that is coming into picture there is no DC feedback and therefore the gain is nothing but the open loop gain. So this is the effect of it has almost gone to the saturation you can look at it and it is still working right as an ideal integrator there okay. So next what I have done now is to shunt this capacitor by a large resistance 100 key we have used for R for converting voltage to current 1K and I have now shunted made the capacitor non-ideal by connecting a resistance of 100K across it. Now there is DC negative feedback okay of 1 over 101 okay 1K and 100K form a DC negative feedback of 1 by 101 that means gain for DC is now 101. So the offset effect is only to the extent of gain of 101 or few millivolts 101 into let us say 2 millivolts so 202 millivolts is the offset final offset. So that means it is reduced considerably and you will see that the in the steady state okay is now reproducing only a triangle the effect of offset is considerably reduced okay it is almost not there here visible okay and it is now doing the integration okay. So this slope is determined by 1 by RC right of the integrator that I have used okay R equal to 1K and C equal to 0.1 microfarad is what has been used. So let us see the effect of finite gain might be product of this. So the loop gain of this system if the op amp gain is GB by S this is the op amp gain you are now putting for example in this integrator right you can form the loop this way this is C and this is R. So it is R okay in series with C forming the loop here. So minus GB by S into SCR by SCR plus 1 is the loop gain. So that is what is shown here. So that V naught by VI is nothing but the ideal value 1 by SCR this is the ideal value for the integrator always divided by 1 plus 1 over loop gain this is what we should remember. And loop gain is this if you substitute that we get minus 1 by SCR okay which is the ideal transfer function of the integrator divided by the effect of non-ideality 1 plus 1 plus 1 over SCR into S by GB okay this 1 over loop gain DC loop gain okay 1 over loop gain becomes this. So minus omega naught by S 1 plus omega naught okay if you put omega naught as 1 by CR right then it is 1 plus omega naught by GB plus S by GB okay minus omega naught by S is the ideal value which can be approximated as minus omega naught by S into 1 plus omega naught by GB that is this factor. So that is what is called as the magnitude error this is the magnitude error of the integrator and this is the phase error of the integrator. So that is approximately what changes omega naught of the integrator E as minus omega naught dash and that is modified by the GB it is fixed error and we have a frequency dependent error here which is 1 plus S by GB and it is primarily the what phase error. So it is causing a phase error of S by GB please compare this with what we get in the case of resistive feedback okay here that is capacitor coming into picture in the feedback okay. So in the resistive feedback like summing amplifier or instrumentation amplifier we had already seen that there is only the phase error dominant okay due to the feedback factor okay. So if beta is the feedback factor it is going to become 1 plus beta S by GB right. So and it is going to give only the phase error and the magnitude error is second order and it can be ignored that we had pointed out pretty early okay. Here there is both magnitude error and phase error in the case of integrator. So every integrator contributes to magnitude error because of this omega naught by GB which is fixed and the frequency dependent omega by GB phase error tiny nurse omega by GB which is approximately equal to omega by GB within the bandwidth. So this error becomes important only within the bandwidth for the signal and therefore we have to consider this error every time we encounter an integrator a phase error that means the ideal phase is phase lag of 90 degrees okay which is increased by a factor of omega by GB further lag of omega by GB occurs. Please remember this when we discussed this effect in most of the amplifiers and let us say in filter design later. So now we have an integrator which can be built using a grounded capacitor. So this is what is called as Debo's integrator let us see how this integrators integration this is another alternative integrator. So you can see that VI is the input voltage and this V naught is the output voltage here and we have a feedback okay R and R that means this feedback is V naught by 2. So again the nullator concept this is V naught by 2 this voltage is same as this voltage and there is a positive feedback in order to this is nothing but a low pass filter R and C and that is going to be a non-ideal integrator low pass filter is nothing but a non-ideal integrator okay it can be made ideal by simulating this is V naught by 2 and this is V naught that means the current here flows this way okay and it is going to be a negative resistance that is going to be seen by the capacitor across it. So we can now do the analysis this equation at this point is V naught by 2 into okay the capacitive current SC plus 1 over R plus 1 over R that is the summation of current at this point due to only V naught by 2 this is equal to the current coming in VI by R plus V naught by R. So in this equation if you write now V naught by VI comes out as 2 by SCR okay this gets cancelled with this this gets cancelled with this right and therefore we just get V naught by VI equal to 2 by SCR. So now effect of offset voltage in ahhh an integrator you can see here that the offset voltage in the simulation we have seen already if you do not put a resistance across this so as to cause discharge of this capacitor R okay ahh provide finite DC gain for this DC negative feedback here then most of the input offset gets amplified by the open loop gain of this stage that is A naught typically of the order of 10 to power 5 to 10 to power 6 and the input offset is of the order of few millivolts apart from that if you have this as input stage as bipolar then the base current of that will flow through this okay and ahh so and it causes okay finite offset voltage to appear here because of the finite base current through the source resistance ahh this resistance now this voltage to current converter resistance which may be pretty large okay and then this offset voltage will further cause problems at the output so it will add to this 2 millivolts so in order to compensate for that always ahh resistance is put this we had already talked about earlier also how to reduce the effect of offset current okay this reduces enormously because the same current roughly flows through this also and it causes an opposite voltage to get generated automatically so this is an offset compensation key okay particularly at low frequency ahh omega naught when it is low R will be pretty high and then this offset effect is going to be predominant in such situation this is the way to compensate for the offset in integrators. Now let us discuss differentiator ahh filter design is normally equivalent to solving differential equations or integral equations so you can either use differentiators as basic building blocks or integrators what is wrong with using differentiators. Let us look at the other application of differentiator differentiators if you give ahh sudden change here that sudden change simply gets carried over to this as an impulse okay so these are normally used as time markers for triggering some action okay so these are important components but this active integrator differentiator let us see what it does it is using the concept of converting voltage to current at the input of an op amp with one ahh non inverting terminal grounded so it converts this voltage to current as CDVI by DT I is equal to CDVI by DT so that is the current flowing through the CDVI by DT because it is voltage is zero. So what happens this current is converted to voltage so this op amp is only acting as current to voltage converter or it is a trans resistance amplifier so this CDVI by DT goes through this resistance develops a voltage V naught which is minus IR and that is minus RC into DV naught by DT so V naught over VI becomes minus SCR or it is minus S by omega naught where omega naught is equal to 1 by RC. Amplifies noise because the gain is directly proportional to frequency if the op amp is ideal it is pretty useless as a ahh amplifier amplifies noise okay that ahh white noise which is contained at all high frequencies okay so this is simply dominating and submerging the actual signal in noise. So this is pretty useless okay the more the ideal it is the worse it is for use in any practical circuit that is demonstrated clearly by taking the effect of finite gain bandwidth product. Look gain is again GB by S that of the op amp that of the op amp okay into 1 by 1 plus SCR let us look at it as a loop so RC this is GB by S minus GB by S because this is minus plus okay and this is 1 by 1 plus SCR that is the loop gain. So again V naught over VI is minus SCR which is the ideal value divided by 1 plus 1 over loop gain okay and 1 over loop gain now is this S into 1 plus SCR divided by GB so minus S by omega naught divided by 1 plus S by GB plus S squared by omega naught GB. So now look at the difference the integrator remained a first order in spite of the effect of GB by S so it only cost ahh the lag error of omega by GB to occur here this becomes a second order system this is first order integration and this is low pass filter action so making it basically a loop with second order and we had understood in system design how a second order system behaves. So it can be equated to minus S by omega naught divided by 1 plus S by okay omega naught okay ahh omega n Q plus S squared by omega n squared omega n is the natural frequency of this system which is square root of omega naught into GB and Q by comparison is GB by omega n okay square root of ahh GB by omega naught okay omega n if you substitute this it becomes square root of GB by omega naught. So as normally GB is much greater than omega naught okay the Q of such a system is very very high this causes ringing ringing means we have studied ringing means number of peaks which are countable okay from initial amplitude of unity to one tenth you go. So Q of such a system becomes very high this causes ringing to be sustained before it comes to steady state so it is pretty useless in most of the application. So whenever input changes suddenly okay let us look at the simulation of this we had seen the effect of offset becoming predominant here the ahh triangle is applied what is the expected output is differentiated okay so you should see a square view ideally okay. So differentiation of a triangular view is an ideal square view this way. Now see what happens for R equal to 1 K C equal to 0.1 micro farad okay same value that we had used for ahh an integrator LM 741 okay is the op amp doing it and its gain meant product is let us say roughly 1 mega hertz. So we have ahh huge ringing taking place whenever sudden change okay is expected this is the sudden change that has happened okay and that has got converted into a square wave a sudden change occurring at this point of transition the slope is changing suddenly from this to this okay. So this is the place where the ringing starts again the slope is changing from this to this gain ringing starts right. So now how to design a good analog differentiated in spite of this it is very simple make the queue become equal to 1 that means there will be just one ringing and it will come to study state very quickly. So that is what is done in the next design so R is equal to 1 K C equal to 159 pick of errors and the op amp is still the 741 okay and ahh C has been changed by more than ahh 1000 okay factor from point 1 it has been changed to so that the queue omega naught is 1 over 2 pi R C is made equal to 1 mega hertz Q we have seen is nothing but square root of GB by omega naught GB is 1 mega hertz. So I design my omega naught okay such that the queue of the system is 1. So GB is made same as omega naught and therefore Q is 1 that means it comes quickly to study state and we get back the ideal waveform that we are expecting as an output after differentiating. So this is the way to design systems that take the finite GB gain bandwidth product of the op amp into a con in your design to design better feedback systems okay this way now as an exercise I am making you okay connect an integrator to a differentiator okay having the same value of RC select the value of RC so that the distortion in the waveform at the output is minimal distortion means deviation from what is expected ideally okay by this operation. So square wave is getting converted to triangle and the triangle is further converted to square wave using the same value of RC what is the best value of RC that is to be chosen so that the distortion is minimum that is the problem. So this is having a finite gain bandwidth product effect this also has finite gain bandwidth product effect okay how best to if the op amp is given let us say 741 is what you are used earlier let us say we want to use TL081 instead of 741 okay what is the consequence of this in selection of the components for this you know is what I want you to study and get a relatively distortion free square wave because a square wave okay integrated and differentiated should give back the square wave that I have started with okay if everything is right that means if these parameters are not affecting it should be got perfectly. So how to select okay the gain bandwidth product if RC is given or the other way if RC is okay to be decided how to do that for a given gain bandwidth product for the op amp is what the problem is all about. So I want you to attempt this and show that it is possible to design such a circuit okay with least amount of distortion next we are already seen how a grounded capacitor integrator can be designed okay why can't we do the same thing for differentiated so this is a differentiated design so this is VI and this attenuator gives VI by 2 here so this is VI by 2. So once again let us write the equation at this point VI by 2 into SC plus 1 over R plus 1 over R summation of all admittances here gives the total effect of the current due to this voltage at this node and that should be equal to the current coming gain due to VI at the input and that due to the output okay. So again we have here VI by R and that VI by R gets compensated here by VI by R. So VI by 2 SC equals V naught by R okay so V naught is equal to SCR divided by 2. So I would like you to simulate this okay exercise using similar inputs there and determine the effect of GB by S again it will start ringing how to select the RC so select the same similar RC there also okay so that the Q of this entire design becomes equal to 1 design it for Q equal to 1 for this second order system okay. So this is the exercise that is given to you please try this out and see for yourself how systems can be designed where in the effect of gain bandwidth product can be minimized distortion can be minimized to the extent possible. Now in the next lecture we will be discussing in some summary what we have done in this is to deal with design of instrumentation amplifier specifically 3 op amp version of the instrumentation amplifier which is the most popular one. Some minor modifications to these topologies can be given by actually using transistorized transconductor to feed on to these different amplifiers okay make it work for all gains with the same bandwidth okay as the gain changes the bandwidth is likely to change in the 3 op amp also okay because the feedback keeps changing. So how to counter this by using transconductors as the front end okay. So this is a problem that can be solved in IC design okay and those topologies are already in the market okay with better performance than the 3 op amp version that we had proposed there earlier but that is the basic stage. So in conclusion what we can say is we have just design of other building blocks like integrators and differentiators and the effect of finite gain bandwidth product has been thoroughly understood on how to optimize these designs okay of these integrators and differentiators for a finite gain bandwidth product has been brought out. So in the next class we will be considering how to design a combination of op amp with transistors as transconductors okay in a variety of non-linear applications last signal applications as data compression circuits and data expansion circuits log antilog amplifiers square law and square routing operations using transistors bipolar or MOS.