 And thank you, Elke, for the introduction. Can you hear me? OK, OK. So in this work, we investigated the possibility of adding security to chips that are fabricated on plastic substrates. And it's a collaboration between KU Leuven and IMEK. So first, I will say something about the technology, then about our implementation and our key hiding solution. And finally, I will draw some conclusions. So flexible electronics on plastic substrates are commercially used for flexible displays. And in these displays, thin film transistors are used to control the current that is drawn from the pixels or sub-pixels in these displays. But a bit over five years ago, researchers started to notice that this technology could also be used to develop digital circuits on flexible foil. And that's why they started making these circuits, first very small, then larger, and larger. And these circuits are mainly used in passive, near-field communication chips. And they can be integrated because they are flexible, bendable, stretchable. They can be integrated in paper, cardboard, and plastics. So examples of circuits that have already been produced and tested are transponder chips and also an 8-bit microcontroller with a very reduced or very limited instruction set. But technology is not standing still. So there are a lot of evolutions. And researchers are working actively to improve the technology. So in the near future, we can expect applications such as smart packages, intelligent labels, electronic paper, et cetera, using this technology. So what does a transistor or a thin film transistor look like in this technology? So actually, there are several options. But the option that at the moment shows the best performance and also the lowest production cost is amorphous metal oxide, thin film transistors. And you can see a cross-section of a transistor here. So the semiconductor, yeah, so the substrate is plastic. The semiconductor is A-exo. And A-exo is the metal oxide semiconductor. And it stands for amorphous indium gallium zinc oxide. Then the metal that is used to connect the source and the drain and the gate, and also the metal layers and the via is molybdenum. And then we use silicon dioxide as a gate dielectric and silicon nitride as intermetal dielectric. So this is the technology, the specific technology that we use in this work. So how does it perform and why do we want to use it? This is a table that compares this technology to silicon chips that we are used to. So these are some ballpark numbers, actually. It can deviate a bit, but just to show you the order of magnitude, the differences. So first, coarse-applied voltages can go below 1 volt in silicon chips. In the technology that we use, we are still at 5 to 10 volts, which leads together with other factors to a higher power consumption in general. Then the charge carrier mobility. This is the speed at which electrons and holes can move through the channel of the transistor under the influence of an electric field. This charge carrier mobility is a lot lower in the technology that we use, which leads to a much lower performance. Then the transistor density is much lower, which means that we need a much larger area for the same functionality. The semiconductor type is only n-type, which leads to unipolar logic, which is usually less reliable, or needs more transistors to reach the same reliability. So I only said negative things up to now. So what's the positive thing about this technology? The most positive thing is the cost. So as you can see here, the cost of one transistor is much lower in this technology than in a silicon chip. And another advantage, of course, is the flexibility. So the chips are bendable and stretchable, which means they can be integrated in, like I said, plastic, paper, cardboard, et cetera. So what is the challenge that we tackled here? So we noticed that nobody looked at secure communication between these flexible tags and a reader yet. So we had a look at it. And we thought that there are many challenges that we need to tackle. But we started with a few of these challenges. And what we did in this work is to integrate a crypto core in the flexible chip. And the reason why this is challenging is because up to now, only like this amount, ooh, sorry, only this amount of transistors, like 3,504 transistors was the maximum that was integrated into one chip. Because otherwise, if you go higher, the reliability becomes questionable. So that was a challenge. And we wanted to show that we can have more transistors for our work to serve as a driver for technology researchers to show like there are other applications that need more transistors. So that was one thing. And then the other thing we wanted to make sure that the key bits could not be read out. And there's two reasons for this. So these chips are not packaged. So it's just the bear die that is used. That's one thing. And also the features are very large. So like I said before, the density of the number of transistors per square millimeter or centimeter is much lower. So you can really see the transistors very easily under a microscope. So that makes it very easy to look at the circuit, actually. The other thing is that there is no or currently no electrically readable, writable, erasable memory. So we cannot have ROM memory, for example. So we need to find other solutions to program the key. And these other solutions are much more visible than programming a bit into ROM, as I will show later. So I will go over our implementation now. So which choices that we made in this design? First of all, the algorithm. So the most important factor there was that we needed the least number of transistors possible. And then we checked and Katanten 32 is the algorithm that as far as our knowledge reaches has the least number of transistors reported up to now. It has a block size of 32 bits, key size of 80 bits. And it has a fixed key, which means that the key, it doesn't have a key register, but the key is supposed to be burned into the device and thus cannot be changed. So it consists of two shift registers and some logic. And this is what we implemented. So the way we implemented it is in a serial architecture. So we have three input bits, a start bit, a clock bit, and one bit for the plain text to be shifted in a serial manner. Now we have two output bits, a ready bits, and then one cipher text bit that shifts out also in a serial manner while the ready signal is high. So then you get this architecture. Now when we go one level down, what do the standard cells look like? So like I said, we can only have n-type transistors so we cannot have CMOS logic. No pull-up, pull-down network. So we have to use other types of cells like people used 30, 40 years ago when there were only animals transistors in silicon chips. And that leads us to this gate construction. Sorry, so this is called pseudo CMOS logic. And it consists of two stages. So in the first stage there is an animals pull-up transistor connected to a bias voltage in combination with a pull-down network consisting of n-type transistors as well. The output of this stage goes to a second stage and drives a pull-up n-type transistor supplied by the power supply voltage and it repeats the pull-down network. If you make sure that the bias voltage is at least equal to the supply voltage plus two times the threshold voltage of a transistor, then you can make sure that the output range of this gate is between ground and VDD. And this is important to get real-to-real behavior and higher reliability. So this also means that we need, because for an AND gate we need two n-type transistors in the pull-down network, so that means that we need six of these thin-film transistors for one NAND gate while this number is four in silicon standard cell technologies. Then one level down is the transistor, but I already showed you the transistor, so this is again this cross-section. Then when we look at the layout, this is just a picture that we drew from the layout. So you can see that we used 4044 thin-film transistors for an area of 331.5 square millimeters, so this is very large. It's almost two centimeters by two centimeters. And on top we have the place where the 80 key bits are being programmed. I will zoom into that later because it's the second part of the talk, actually. And at the bottom we have 48 pads to connect i-opens, supply voltage, bias voltage, and ground voltage. And some of these pads are actually unused, but the reason why we use this structure is because we can then easily connect to a probe card for testing afterwards. So this is our measurement setup. This is the chip again. The 48 pads to connect to the chip. These connect to the, if you can see it, there are 48 needles here. So these are probes that are connected to a probe card. The probe card is here. It connects to a PCB that contains level shifters to make sure that we can communicate with an FPGA. And the FPGA sends the test vectors and takes back the response from the chip to check if the output is correct. So we fixed the 80-bit key. I will tell you later how we fixed it. So this is the value, not important in hex. We applied 1,000 plaintexts automatically and then received the 1,000 ciphertext. Actually, we repeated this many times also, so there's more than 1,000 plaintexts applied. And we got correct outputs for these combinations, like VDD 10 volts and V bias 15 volts and also 11 volts for VDD and 16 and a half volts for V bias. The maximum clock frequency that we could reach was 10 kilohertz. And the number of cycles to complete one caten 10 encryption was 32 for shifting in the plaintext, 254 for doing the encryption, and 32 for shifting out the ciphertext. At the clock frequency of 10 kilohertz, this means 31.8 milliseconds, which is a lot, of course. But like I said before, these types of chips are used for applications that do not need speed, do not need a small area, but mainly need low cost and flexibility. So then when we look at the key programming, so this is actually, so you can see the 80 key bits here, and I just took a part of it. This is an image that was taken under the microscope, so this is not the layout drawing anymore, but this is the real chip. So as you can see, we have a power rail and a ground rail here. Then we have a number of bits, 11 on this picture, 11 of the 80 key bits that are connected both to the 3DD and the ground rail. That's how the chip is fabricated, and then you can see part of the logic here. When we zoom into this part, then you can see how we made sure that before using the chip, one of the connections is broken. So actually what we did is we used the laser to break every time for each key bit one of both connections. So it's a very simple way to either connect the key bit to a logical one or to connect the key bit to a logical zero. But you can see the problem here. So this is an image that could be taken with a very cheap microscope, actually, even. The problem is that you can easily read out the key bits, so you can easily see the 80 bit key. So that's why we propose a solution to hide the key. And first, you should look at the left side of the slide. This is the concept that we propose. So if you look at the graph here on the y-axis, you can see the current that flows through the transistor. And on the x-axis, you can see the voltage that is applied at the input of the transistor. If you look at the full line only first, then you can see that if you apply a fixed negative voltage at the input of the transistor that the transistor is off because it only starts conducting when the input voltage is larger than the threshold voltage of the transistor. But if we then heat up the source and the drain of the transistor, this VT value shifts to the left, which means that this curve also shifts to the left and we get the dotted curve. If you then apply the same fixed input voltage, the transistor suddenly switches from off to on. So this way, by lasering, we can make a transistor change its mode from off to on. And that has the same effect as having a wire that is first open or a connection that is first open and then closed. So there's two options now to use this phenomenon. So on the right side of the slide at the top, you can see the first option. So what we can do is we can use a pull-up N-type transistor to connect the key bit to a logical one and then a pull-down N-type transistor that has this fixed negative voltage at its input. If we don't do anything, the key bit is one. If we then use a laser on this bottom transistor, then this transistor starts drawing a current. And if we make sure that this transistor is larger than the top one, then this one wins from the top one and the key bit becomes zero. A second option for programming the key bits is to just use two transistors that are connected to this negative input voltage and then choose which one to laser in order to choose which one will be connected either to the power supply or to the ground. Of course, the value that comes out here is VDD minus the threshold voltage, but that's still high enough to be used in the rest of the chip. So then we experimentally validated this approach and the first experiments were actually disappointing because we could see the difference between a transistor that had been lasered and a transistor that had not been lasered. So what you can see here is the top view of the chip, also an image made with the microscope, under a microscope. So on the left side, you can see a transistor that has been lasered and you can see these, yeah, maybe the quality of the images is not good enough, but you can see the lines here, it's a bit darker. So maybe I should say that this is the gate, the horizontal line and these are the source and the drain. And you can see the small lines here or the darker orange color for the transistor that has been lasered because this one has not been lasered and you can see that this yellow part is everywhere the same color. I don't know if you can see it, but I hope so. So the problem is that the difference is, at least we could see it when we looked at it under the microscope. So the problem is that the difference is visible between a thin film transistor that has been lasered and one that has not been lasered. So we had to find a solution. And our solution is that we try to apply different laser settings. So actually we explored 20 or 30 laser settings to see if every laser setting had the same effect on the transistor. And what we saw is that for some laser settings, we actually really got this VT shift that I showed on one of the previous slides. And for some other laser settings, the VT shift was very minimal. So the curve almost did not shift to the left. And the good thing is that these two images look similar. So you can see for both transistors that they have been lasered. So it's both a bit darker orange, but the VT shift is different. So we applied two different settings. At the top we used an attenuation of 45 dB in low energy mode and we applied one pulse. And then our experiments showed that applying a laser with an attenuation or a beam with an attenuation of 35 dB in low energy mode and with two pulses gave us this result. So if we now apply a negative voltage of minus five volts, then in the top case, before lasering we get the blue curve and after lasering we get the red curve. So in the top setting, applying this fixed voltage makes the transistor go from off to on. And in the bottom setting, applying this negative voltage and then lasering the transistor does not change the state of the transistor. So it stays off. So we can now easily apply this to one of these two settings to program the key bits in an invisible way. So to conclude, we presented the first cryptographic core on Flexfoil. We presented a solution for the invisible programming of the key bits. And actually there are many more security challenges to be tackled. The technology is rapidly improving and will soon also be ready for mainstream applications. So that shows the importance of really tackling these security challenges and making sure that we can guarantee the security of chips in this technology for future applications. That concludes my talk. Let's thank speaker. We're running a bit late, but maybe somebody has a question. Is, congratulations, great talk, fun research project. One question. One possible remaining attack is probably just a direct probing of the transistor, I assume, right? And you can do an exhaustive search and you can probably almost manually, right? Yeah. That's a transistor. Yeah, so actually, other things that we could do is to cover, which would also be an option to hide the key, actually to cover the foil with ink. But then we would, I mean, such that you cannot see where the transistors are. Yeah. Actually, this ink is hard to remove by mechanical means because you would break the chip. But there might be solvents that can solve the ink and it's, I mean, we should investigate it. We didn't look at it yet, but that could be a solution to prevent that. And then we would have to apply ink on both sides, of course, because you can access the transistors, actually. So you probably could get medium level security at a pretty low cost. Yeah, something like that. That's good. But it's all over. Congratulations. Okay, let's thank Nelun again.