 So, welcome to this lecture on advanced digital design, digital system design in the course digital system design with PLDs and FPGAs. In the last lecture we have seen how to kind of decide the minimum frequency of a state machine and with regard to the data path. And also we have looked at the conditions you know the inputs are not very neat waveforms and when there are the real life inputs are there how to handle it because it may not meet some kind of requirements we put forth. And we also have started looking at the features I mean what is the difference between Millet and Moore kind of outputs and maybe how to at least in some cases how to make what is a Moore output into a Millet output or at least to illustrate that is what we have done. We have converted a Moore output to Millet output and I have seen what are the advantages what are the disadvantages we have not completed it and we will complete it and today. So let us look at the last lecture slides and we have you know looked at the minimum frequency and we said the main game is suppose if you look at 3 inputs and put this clock then we soon find that this clock is not able to detect change in this input 3. So it is like we need at least one clock edge active clock edge during that change in entry and to kind of an ideal example we have taken some square wave and it is soon clear that at least one clock period less should come within this kind of change. And change being symmetric or regular we can say that the clock frequency should be at least twice that of the maximum input frequency that is a kind of thing we have told and that is not surprising because the state machine is basically sampling the input looking at the inputs for any change any event and trying to respond it with output a sequence of output sometime that is why it is called sequential circuit. And input in real life input is not a square wave or periodic waveform but the pulse width should not be the criterion that means that you have an input which has a we changes for a while you know it becomes 1 for a while say a few nanoseconds then say 1 microsecond it is inactive again it comes like for this change to be detected in a kind of very straight forward way then one would expect to have a clock period kind of matching this pulse width. But we know that we have we talked about the frequency and we know that the frequency is quite low. So definitely this pulse width is not the criteria for choosing the minimum clock frequency of the state machine or the controller. Also the kind of waveform suggests that there should be some way to stretch the waveform and then suppose in this case if you stretch it here you could definitely use a lower clock frequency for the state machine. And we have seen some practical example of I mean how to pull how to stretch it. Before that I said something much more important here the requirement is only to detect the event detect that it is input has changed the state okay and respond to it. But maybe in some cases you have an kind of accuracy requirement that means that there is a timing pulse and say we are trying to detect say it has gone high in respond to some event the state machine has made it high or enable something to something which has made the signal to go high and waiting for it to go low which needs some precise timing. And in that case if you use a clock like this it will detect that it has gone high here and it will detect that it has gone low perfectly okay just we are trying to recognize that it has gone high and gone low. But if you need some precise timing to be kind of measured then you know that this clock is much better because this clock detects that it has gone low after such a long time. But this is much faster so that means suppose if somebody say there is a plus or minus error okay within which need to be detected or within which an event has happened within which that has to be responded or whatever. Then like this is the event and it should be detected with an accuracy of some kind of time period. Then you know that the clock period should match that error okay then only we can detect it that is what I mean by this you know and this situation arises you know you have an event and somebody say the controller has to kind of respond to it within a certain time okay. It is nothing do the pulse would maybe the pulse itself remain high for a long time it is a very rare event. But the requirement is that the event has happened but this may next event may happen after one second. But somebody say that the response should be as fast as a kind of one nanosecond. Then definitely you need to detect it with that accuracy you need that clock period to be one nanosecond otherwise there is no way to do that okay. So that is what I mean and now let us come back to this kind of clock stretching and we have seen one kind of circuit which is not very much used I have just shown something to illustrate. So this is the pulse catching circuit where the clock is this is the kind of pulse we are trying to extend it that is a clock and the input is 1. What we do is that we use a two stage shift register so that we are not sure because this clock and this pulse is not synchronized. So we are not sure when this will happen and that is double clock so that at least you get one period width here the synchronized pulse this one. So in the picture it is shown as almost two clock period but you know that this is gone up this edge could have been very near to it and then you get only one clock period and that is shifted and it is reset okay. So basically it is stretched and if you put multiple stages of flip-flops you can stretch it any longer but then if it depends on the clock of the FSM but if you use a lower clock there is no reason to kind of stretch it you know more than two stages because we have one clock edge you know coming in that period that is all what we require kind of to be detected by the state machine. So there is practically there is no reason to put more flip-flops because after all this clock is the clock of the state machine. So two stage should be enough I have shown a practical circuit which is not stretching it what we do is that we as output when a pulse come the output goes high and stay there till the next pulse come when the next pulse come it goes low and it goes to the state machine and what state machine does is that every edge every positive and negative edge you can make kind of a pulse and that is a pulse to level converter this is the circuit you have the pulse clocking the flip-flop and you have a kind of toggle flip-flop the Q is fed back to D through an inverter. So first pulse come it is high next pulse come it is low and our aim is to get a pulse here at the receiving end and one pulse here ok. So we do a synchronization for timing reason to avoid the metastability in flip-flop we have not discussed it but at least for the time being you just try to put a double stage synchronizer which is nothing but same clock and two flip-flops in series and here is what we do you do an I2 the input of the flip-flop and output of the flip-flop you combine and if you do I2 I3 bar you get a pulse here the opposite I3 I2 bar then you get a pulse at the negative edge and we want pulse at both edges because maybe in the last class I did not kind of stress it because here there is one pulse then it goes high next pulse come it goes low. So at the receiving end we need a pulse here and a pulse there depending on the which is of the width of the state machine clock and that is what we have done this is the clock of the state machine and you do say you do I2 I3 bar you get a pulse at the positive edge I2 bar I3 you get the negative edge you over it then that becomes I2 X or I3 so this is an X or gate then you get pulse here and pulse here and you know that it comes with the delay of the clock period. And that perfectly works fine for the state machine because this is high during the active edge of the clock and that is this is correctly detected by the state machine. So this is a very practical circuit very much used though there are some kind of timing constraints probably which at this stage we will ignore it is not that you know it works for all cases you know. There are some restriction on because of this double state synchronizer because you know that for the I2 to come here it takes 2 clock period okay. And so that means between these 2 pulses there should be at least 2 clock period gap of the state machine okay nothing do with the pulse itself okay after the pulse comes here you know that it will pass through 2 stages of flip flop and that introduce a latency maximum of 2 clock period because this is not kind this the input pulse is not synchronized to the clock. So may take maximum 2 clock cycles so it is important that the gap between these 2 pulses is at least 2 clock period of the state machine clock or the receiving domain clock we can say. So that is a circuit and that I have shown it you know in combined together you have a kind of level 2 pulse to level circuit or pulse to toggle circuit and this is a toggle 2 kind of pulse back circuit. And we have discussed when we have a register to register path be it a state machine or a sequential circuit or a data path where a register a combinational circuit register in the case of the state machine or counter this could be next aid logic in the case of data path this is some computation. But the clock period is chosen as TCO, TCOM and T setup all maximum and T clock period should be greater than that and to avoid whole time violation this delay plus this delay which is minimum delay should be kind of greater than the minimum whole time. And many a times the people ask a name question why this cannot be the clock bar as I said there is no great issue with the like the trouble is that you are looking at a part of the whole. And if you have an old picture put in mind then you will soon realize that this is not possible because this is clock bar and again next is clock that is fine. But then there is a feedback from back here then you find this is the last one was clock and the feedback is also back to the clock not to the clock bar. Similarly you have a path here and it terminates at clock bar and you have another path here which terminates at clock then both output go to another register then you are confused whether that should be either clock or clock bar but cannot be both then you are stuck okay. Similarly like you have a data path giving the signal to the state machine and maybe state machine receive output in respond to a positive edge to get clock you know register and negative edge to get register. So, there is a big issue so you have to stick to one priority it can be clock or clock bar and timing wise and we have seen there is no big deal because if you use the old like if it is possible to use half the clock period then this t clock min by 2 as to accommodate the maximum delay. The only thing is that the clock period will be you know twice that of the clocking by single edge so the clock frequency comes down that is only kind of advantage but practically it is not possible to do that that is a simple answer and this is where we have looked at and we were trying to kind of understand the difference between Moore and Millet output because in most textbook would deal with very simple cases of state machine with one input and one output and somehow many times it appears that you know at the beginning you can kind of decide the state machine is Millet or Moore and accordingly you at least that is the kind of it may not be intended by the textbook but that is the kind of picture many a times students get but in practical cases there are as I said there are may be so many states may be more than 20 states more than 15 output and some are Moore some are Millet and one it is not a kind of ideological or some matter of taste to choose Millet and Moore output is not that you like Millet or something like that it is there are some cases where Millet is the most appropriate thing and some cases it cannot be done at all. So you have to kind of choose and that is what we are trying to do this and this is an example which is drawn from our case study that is why I take the case study so that you can illustrate the various kind of concept based on that once you understand that. So this is our ADC kind of data acquisition controller so there when we discussed we said that the power on it comes to the state 0 and when the start it is waiting for the start from the host processor and when start is low remain there and we are only looking at this particular output which is of kind of concern and the start of conversion pulse is 0 and when the start comes it transit to next state and there the start of conversion is made 1 and there is no condition on that state next clock it transit to the next state and SOC is made 0. So this state remains there for 1 clock period so you get a pulse of which 1 clock period and you make it 1 ok. Now let us think whether we can make this as a this is a definitely Moore output because this is a decode of state 0, this is a decode of state 1 and so on. So if the SOC is 1 we know that in the state diagram SOC is 1 only in one state so it is decoded as we know that this is 0 0 this is 0 1 so it is decoded as Q1 bar and Q0 ok that is all that is the equation that is a decode of the present state. So what we are trying to do is that we know that already that this SOC has something to do with the start ok when as long as the start is low SOC is low when the start goes high the SOC becomes 1. So why not kind of envisage a Millet output in that way ok that means that like this you are the machine is in state 0 at the power on it is waiting for the start signal so as long as start is not active remain in this state and we say instead of saying SOC 0 we say SOC is 1 if start is 1 in this state we are not transiting to another state ok. So we are hoping that sometime being in this state the start becomes 1 so that state you know that state that means Q1 bar and Q0 bar that is 0 0 and start is the decoding of SOC it is a Millet output and also upon the start it transit to next clock edge it transit to the next state and we are skipping S1 because that is done here. So we skip to S2 where the SOC is 0 so that is the Millet output that is why it is converted so I think you get the picture and I said already you see an advantage there is one state less and you can imagine in a huge kind of state machine where there is lot of kind of outputs which can be made Millet output then you get the states less so number of flip flops could go less and if the number of flip flops are less maybe the next state logic because it is a function of the present state and input the area of that could become less and the output logic which is a decode of the present state and input that becomes less and so on ok. So the area can become small the state machine can be clocked very high you know high frequency it occupies less area reduces the power dissipation and so on. So many advantages one can think of and as I said that for a clever student like as an advantage there already should some indication of a disadvantage you know there is an timing issue because you are remaining in this state and when the input goes high the output is high ok that already should give you kind of a hint as to what can go wrong. So let us kind of illustrate it much more than that this is not a quiz so I want that concept to be ingrained in your mind so that you design something I do not know what you are going to design maybe you design something trivial then it does not matter like if you design a computer game where there is a chip and if something misfires it is not a great deal but if you are sending a rocket to the space and if a slight mistake could put things in a jeep party. So maybe you are part of an aircraft which is being designed and there is a controller which you are designing as part of something guidance then it has to be precise. So let us kind of imagine the worst scenario the critical application and handle this. So let us look at the timing diagram of this kind of two outputs. So this is a scenario so we have a very simple three state and two states so we have the clock and we have a start signal which is going high like that you know it goes high after the positive clock head and for the two clock period say it is there. So now you look at the Moore machine okay so or Moore output so there you see that at the beginning start is low so differently you know that this is S0 here also you know that when the clock edge comes is still low so this is S0 and the next is S0 because there is no transition when the clock edge comes it is low so it is S0 but in here you see when this clock edge come the start is 1 so the next one is S1 and you know that S1 in the next clock edge without any condition transit to S2. So if you look at the Moore output the states are S0 then S0, S1 and S2 okay. Now how does the SOC output looks like we know that SOC is 1 when the state is in S1 okay so the output will come like this you know you have SOC is decoded from the present state and it will be like that it will not match the period because there is a output logic delay because output is decoded from the present state. So there is a Tcq delay of the flip flop plus the T output logic that is this one so this is Tcq maximum Tcq plus maximum output logic that is the worst case gap you can have and it appears like this okay. Now let us look at the Millet kind of output we know that there the same thing the state is S0 the clock edge comes it is still 0 it is S0 and it start has gone 1 and you know the clock edge and it goes to S2 there is no S1 in the Millet output so you remember that you know there it was start is high it comes to S1 then S2 but here start is high it just goes to S2 but it generates in S0 and output SOC is generated as a function of start so that is what we are going to see. So here in the Millet case the first one is S0 second one is S0 the third one is S2 but our output now you look output is in state S0 and the start is 1 so basically it is a decode of that and so you kind of and both together this is 1 and this is 1 and since start is going high here it will come with the delay because of the decoding delay. So you have something like that you know you can imagine little more delay because start is going so I have not shown that but this is delayed a bit so this comes like that you know it is very nice. So if you look at the advantage yes 1 state less okay good and output appears kind of much before at least a clock period before. The more output looks good it responds faster okay now the gain comes the question comes what is wrong with this you know here probably nothing can go wrong but here you see the output is a function of the state and the input and this input mind you has got nothing to do with the clock and this input is not synchronous with the clock because this input is our state machine clock and this comes from a host processor and that processor has another clock so this may be generated in relation to that clock which could be much higher than this. So this pause can appear anywhere and the question is what happens if the start come late like that you know I have shown with a fainted kind of mark so if it is suppose the start is coming very close to this positive edge then what happens is that the SOC become kind of glitch you know we said that there is no great timing restriction on SOC in the sense that can be a narrow pass but if it is very narrow it may not be detected or this could be thought of as some other output not SOC. So since the input if the case of if there is a case where the input is not synchronized and the output you will get a glitch which may not happen in the case of more kind of output. So it is a bad news okay it means that if it is a bad news as well as a good news it depends on the way you look at it okay. So there is a famous story of a famous shoe company sending the salesman to a country where people you know long back people were not wearing the shoes or any footwear. So this marketing person was sent to that country so naturally he went around and his eyes were on the feet of the people and he wired back you know at that time there is no internet and the mobile phone. So he wired back he sent a telegram saying that I am coming back the people here does not wear any footwear okay so he went back after few kind of month another marketing bright young men came as a marketing person he was sent to the same country okay. So he went around looking at the feet of the people he wired back you send two ship load of footwear because the people here do not wear footwear okay. So people not having the footwear could be bad news for somebody and good news for someone so it is a way you look at it. So the same situation here in our Millay Moore output the fact that the Millay output when in the presence of asynchronous input can produce glitch is a bad news but it is a good news. It means that when the input is synchronous you can generate the Millay output that is what we should learn positively from this suppose if this start is coming synchronous. Synchronous would mean that in constant phase relation to this clock okay that means somehow this is generated you know indirectly from this clock. So that every time it comes with a specific delay with respect to this clock edge you know it need not be that it comes every time with a very near to the clock edge it can come every time with a fixed phase relation to the clock okay that is the synchronous. So when the input is synchronous there is no timing issue and the output can be the Millay output so that is a game that is a good kind of input so I am putting that in the picture. So you have two synchronous subsystem so you can imagine this is a register which is kind of the condo signal is given by the state machine may be an enable signal or this is a counter which is kind of enabled by the state machine we have seen that or a load signal of the state machine the counter goes from the state machine and the state machine and all these synchronous subsystems are working on the same clock. So and you see that there is some output we do not know what kind of output may be if it is a counter it is a timer it is a decoded output which is going to the state machine input and so on let it be anything but it does not matter. So this output is synchronous to this clock and that goes to the state machine. So state machine in this case has two output I1, I2 it has two control output which is O1, O2 now it is very clear that you know O1 can be generated as a function of I1 and or I2 okay as a Millay output O2 can be Millay output as a function of I1 and or I2 okay it need not be that the O1 is generated only as a function of I1, O1 can be a function of I2, I2 or I1 or you know there is yet another input which is synchronous to this clock does not matter maybe it is coming from the outside world somebody has synchronized to this clock and that can be coming to the input of the state machine then this O1 can be generated as a function of I3 which is synchronous with the clock. So that is a good news that whenever you see a kind of the synchronous inputs you can happily generate the Millay output as a function of that if it makes sense it is not that you struggle hard if it is nice if it works out if it is part of the spec then you can do that and that give you all advantage of you know all these advantages it comes the output comes early to more output number of states are less yeah the glitch does not come since it is synchronous. So that is all about the Millay output when we come to a case study I will show definitely under person how the Millay output can make the life easy only thing is that you should kind of from the day one when you practice you should try and think whether the particular output can be Millay output that is my advice to you. So that is about the Millay output let us move forward ok now let us consider the little issue with the state machine generating the condo signal we have looked at it particularly we have seen an example in this case we have taken a register in our CPU example I hope you remember this was the beginning of the course we have you know we were looking at the advanced digital design and we have taken the CPU as an example we have looked at the top down design I have illustrated all the process all the methodology by taking this example ok. So there we had the CPU registers and it is an 8 bit register and we said that input is connected to the register the Q output is connected to the same data bus because there is only a single internal data bus and that was connected to the bus using a tri-state gate. So the game was that when some data from the input has to be latched to A the state machine will give a signal latch signal or an enable signal in this case we call as ra underscore l and that comes here when this is high and the clock comes the data was whatever was here gets latched ok. And we mention that it is not that this latch signal is going as a clock because it is possible that we want to kind of continuously load the data in some application ok not maybe with the CPU register in that case it is very convenient keep this latch signal or enable signal high for say 10 clock cycles. So continuously each clock the data gets latched maybe this is a few 4 or a counter which is getting incremented whatever but may not make sense for the CPU register ok. And we have seen we were looking at what kind of how the design should be to make that happen that means when the latch signal is high and the clock comes the data gets latched. So every so that is what is shown here we have a state machine and some register or counter or some sequential kind of element which is working with the same clock and the state machine is giving an enable signal here. So that the input gets latched in this register ok. So and we have seen one possible kind of implementation very first thing which comes to mind because we say that when the latch is high and the clock edge comes the data should get latched ok. So this shows 8 flip flops input and output are combined through a tri-state gate because there is only single data bus and this is the enable signal and we have just combined ok. Now at the time of discussing this we did not look at the timing ok because we probably we did not learn enough about the state machine. Now since we have learned we can look at the timing now assume that this is coming from a state machine. So the pulse is like that but then we know that the relation of this pulse to the clock of the state machine. So I am putting the clock frequency in the clock waveform. So we know that the state machine something happened to the state machine changes a state and output is decoded. So there is the output kind of come delayed with respect to the positive clock edge. So there is a tcq the state flip flop delay and tol output logic delay and it comes here ok. Now you can already see the trouble that we are ending here so you and this you see there is an overlap 1 1 here and there is an overlap 1 1 here. Because of this AND gate delay it gets comes delayed and so you something like that you know you get 2 positive clock edge and you see the trouble ok. We are expecting it to be clocked by 1 and it gets clocked by 2 ok. Clocked twice and in the case of register you may ask what is wrong with it because say some data is here you get you clock it it latch here you clock it again it may latch here ok. But look at the timing when this data may be coming from some other register in the as usual in the data path and through some combination circuit. So that is what that means that that is also clocked by the same clock. So data is kind of coming out of that register and normally you know that we should be latching it at this edge. It is too early for like you know we have a clock edge here but the maybe that is too early because we decide the clock period depending on the tcq tcomb and tsetup and we accommodate that in a clock period. So but here if you see the timing available from the clock edge to this clock is only little. So it is too early for registering maybe this is right like we have decided that the data appears here. But then you know that this the data gets latch here but we do not know whether the data will remain there because that register is clocked by this already the output is changing maybe this is coming in the whole time after the whole time window and so on. Then a wrong data can get latched suppose this is a counter which is getting incremented on this kind of latch signal. Then you know that an edge comes it gets incremented probably again it gets incremented and so on. So this is because of this glitch this scheme is not timing wise very kind of neat okay. So that is why we have I have discussed this points that is why we have looked at this scheme okay. When we discuss the CPU I have shown this scheme and this does not have the timing disadvantage okay. So here we are not doing anything with the clock path we are combining the latch signal in the data path. It has advantage in two ways one is you look that when the latch is one the input is going there okay. So input gets latch and you see that we know that because of the state machine decoding it comes delayed and it is made one and the input is coming from some register clock by the same clock. So it appears it starts appearing here and it has all the time till the next clock period and upon the clock this clock edge the data gets latched here. So it is very clean okay. But the only problem as you see is that the clock is coming every clock this is getting kind of clocked okay. So maybe the data we enable sometime and the data goes here. But all other time this same output is recirculated back to input and so on. So assume that say in a case where the latch signal comes only once in an hour but unnecessarily this whole thing gets you know keep on switched so many times. Suppose it is 1 gigahertz for 1 hour nothing happens but the because of the switching lot of power is getting dissipated. So the recirculating buffer is timing wise is very kind of nice very clean but the power dissipation wise it is really hopeless and absolutely hopeless. It has no relation to when the latch signal is high all the time it dissipates power it just a matter of frequency whatever is the frequency it gets switched and the power is dissipated. Now so it means that for the power as far as the power dissipation is concerned the earlier scheme was nice because when the latch signal come you get 2 pulses okay may be clock twice. But if there is a 1 hour delay nothing happens to the clock and there is no power dissipation. So let us probably if you want low power dissipation. So when you design you can adopt the scheme and we have seen that I will show examples but you are into the like low power domain where you are working with hand held devices mobile devices then you need to dissipate less power anything battery operated or even now its voice you know there are even in a desktop PC there are millions and millions of PCs all around the world even slightest you know power saving will kind of help to reduce the overall power consumption of the world. So we should always look to reduce the participation. So here see the game the trouble comes because like we need actually the hour kind of clocking should happen at this edge. Because when a latch signal comes here the right time to clock is this second edge because the data has changed at this clock edge and it has to propagate and come here. So the right thing to do is that we would like a pulse like this okay definitely but the problem is that because it is coming you know half into this clock period it is problem adding. Suppose this kind of this latch signal instead of coming with respect to the positive edge assume that it is coming with respect to the negative edge. So this pulse will come you know start like this and stop like this and if you and it then you get one pulse very cleanly here okay. So that is the trick okay. So if you can re-synchronize this latch signal with a negative clock edge okay then it comes like this and you can and it with a re-synchronized latch signal the clock is re-handed with a re-synchronized latch signal. Then you will get a pulse correctly like this and you can use it to clock this particular thing. So I have explained what is the idea behind. So that is what I am going to show now. So maybe I will show that and come back okay. So this is what we were discussing. So what we will do is that we will re-synchronize this with the negative edge it comes here then and it okay. So let us look at that you know. So that is what is shown here. So you have the latch signal which is coming from the state machine. Now we put a flip-flop and there is a clock which is coming and it is it is a negative edge to get flip-flop okay. You see that there is a bubble and so that means this latch signal is re-synchronized to the negative edge. So that is we are calling clock 1 and that is handed with the original clock and which generates a clock 2 which is used for clocking okay. So let us put the waveform. So you have a clock and normally the latch signal comes like that and then we are looking at the clock 1 here because it is going to a negative edge to get flip-flop. So it is see when the negative edge comes this is 1. So the clock 1 output is 1 and when the negative edge comes this is 0. So it becomes 0. So you get a pulse with a delay with respect to the negative clock edge and you and now this clock 1 with a clock. So this clock 1 and clock is handed and you get a clock 2 with a delay little delay and you know now you are correctly you are something is happening before at this edge and we are supposed to this edge and that is kind of latch with this particular clock edge and everything works smoothly and there is only one pulse this is clock and it does not continuously dissipate power. So when you need to kind of you need a low power the clock gating then one should adopt the scheme and very standard scheme. Now earlier we had this scheme and this is converted to this. So what many times the tools do is that when they see such a clock gating they can easily convert automatically to this by inserting a kind of negative edge to get flip-flop. So many times tools try to automate this kind of thing looking at this scenario it converts into this even it is possible that you implement with a recirculating buffer and the tools detect that it is a clock kind of recirculating buffer and it can do the proper clock gating by you know taking this resynchronized with the no it can just replace that with this because very regular and that is kind of very close to the it has to be very close to the real flip-flop ok. Otherwise there will be timing issues because you are playing introducing this queue in the path of the clock. So this is many a times done automatically by the tool you give either this or this then that can be kind of detected as a case for proper clock gating and that can be introduced and the FPGAs can be built with kind of resynchronizing flip-flop near to a register and so on. It depends on the FPGAs so when we will look at the FPG architecture then we will see is there a scope is there a flip-flop nearby another flip-flop so that this kind of game can be played but mind you there is one thing I should be mentioning here. So it looks that sometime you know it appears that it is enough to avoid this glitch problem if you kind of push this gate signal you know they enable signal here you know by introducing a certain delay you know you introduce suppose you can introduce 7 nanosecond and it appears here so you might think that you know you can add a kind of 2 inverters to get that delay. But then you know that this delay depends on the clock period and if you add arbitrary delays and change the clock frequency it does not work and you know that the delays are function of the temperature and the supply voltage and so on. So if you kind of in the slowest path you introduce a delay and when it becomes fast this may not work and so on. So that is why we resynchronize with the negative clock at that you should keep in mind. So you should not try to kind of delay this and kind of you know gate it you know that does not work because of the reasons mentioned. And now this is what we have seen so this at least we said that this solves the problem of kind of the power dissipation but many a times we use the same technique to achieve not only one in this case it is just a large signal. But there could be any number of kind of condo signal in the data path and that we have seen in the case of a counter it is not that just one condo signal this is just like an enable signal for a register but assume this is a counter this could be an enable signal from the state machine there could be a load signal from the state machine there could be an up down signal from the state machine and so on. So this scheme can be kind of extended we have already seen it but I just maybe it is a right point to stress it again. So you can have any number of condo signal you can have different data paths like parallel data, shifted data and when you have multiple condo signal you need to have some priority like if both come together which takes precedence okay that should be kind of decided and that is very natural we have seen that condo signal which comes close to the D will have the precedence. So let us look at this you know let us look at this example we have already seen it. So this is a counter with an enable okay very useful kind of structure so the clock suppose is a say 4 bit counter then you have 4 flip flops the clock is common reset is common and suppose a state machine has an enable it is at the reset at the beginning. So whenever it is enabled it is incremented that is a basic idea. So some event happens the state machine enables it and it gets incremented you know that is a great game. So how it is implemented you have a 2 to 1 MUX the enable is the select line of the MUX when the enable is 1 Q is nothing but Q plus 1 and incrementer is in the path and otherwise Q is recirculated. So definitely there is participation but the timing wise it is very neat and we know how to write a VHDL code for it. So we write a process because we know that a single process will work for the registers preceded by some combinational circuit and this is what is a combinational circuit. So we say we write a process with clock and reset in the sensitivity list and we say begin if reset is 1 because it has a priority asynchronous if reset is 1 then Q gets others 0 else if clock event clock is equal to 1 and this is synchronous we say if enable is 1 Q gets Q plus 1 end if that means else you recirculated and the end if of the first if and end process. So that is what shown here process clock reset begin if reset is 1 then Q is others 0 else if clock event clock is equal to 1 and under that because there is a condo signal if enable is 1 then Q gets Q plus 1 end if okay that means recirculate if not Q is Q that is the meaning of it. So that is a 2 to 1 MUX which is synchronous which is coming to the input of the input D of the registers. So let us take another example where there are not 1 condo signal 2 condo signal we have already seen it but I am just reinforcing the concept. So here we have a load signal a 2 to 1 MUX and when the load is 1 the input which is 4 bit gets latch here upon the clock and if the load is 0 then if enable is 1 okay. So it has 2 control load signal and enable control enable is 1 the count gets incremented otherwise count gets recirculated and naturally we know that this has a priority because this comes first. So if irrespective of the enable if load is 1 the input gets loaded when the load is 0 then depending on the enable either it is incremented or the output is held okay and we know once again this register with this combinational circuit can be coded as single flip flop this is synchronous so this comes you know within the clock event clock is equal to 1. So same thing process reset and clock begin if reset is 1 Q gets Q you know Q is other 0 else if clock event clock is equal to 1 and the highest priority load is 1 Q gets D in else if enable is 1 Q gets Q plus 1 and if okay and process you know. So that is it process clock reset begin if reset is 1 then Q gets other 0 else if clock event clock is equal to 1 if load is 1 then Q gets D in else if enable is 1 then Q gets Q plus 1 and if that means else the Q gets Q this is the end for this this is the end for the main thing and the end process okay. So that is what we have I think we have come to the last part of the lecture. So before taking up a new portion I would briefly tell what we have done we have looked at the Millet and Moore output and we have seen that the Moore Millet has an advantage number of states are less the output comes early but there is a problem of glitch. So it works neatly with the synchronous kind of input you can straight away go for Millet output if it permits. And we have seen the condo signal and especially in the case of register a clock gating has timing issue because there are two pulses and the solution is that go for a recirculating buffer it does not have any problem with regard to the timing but all the time it is dissipating power and this can be extended to the multiple condo signal we have seen a case of a counter with an enable and where it works kind of without any timing issue and we have seen the VHDL code and when there could we have also seen a counter with load and enable with which load as a priority. And once again it can be coded in a single process and we have seen the example we have seen it earlier and we have also seen a kind of low power solution of clock gating to avoid this kind of glitches. We re-synchronize this is a large signal with this negative edge and adding a constant delay won't work because the clock period can change and the delay of the combinational circuit itself can change. So we re-synchronize with the negative clock edge and the re-synchronized version of the condo signal is gated with the clock and that works as clock. So this works very neatly there is no issue with the timing only thing is that it uses an additional flip-flop for a set of register not that there could be 16 kind of flip-flops and one additional flip-flop is required depending on per condo signal. We can say we require an additional flip-flop for each condo signal to re-synchronize that is a basic idea of clock gating for low power. So today what we have seen is that we have completed the Millet and Moore output and we have seen the advantage where the Millet can be safely used and we have looked at the clock gating solution re-circulating buffer what is the issue timing issue with the clock gating and how it is avoided in re-circulating buffer. But the issue is that the power dissipation and we have seen a clock gating scheme for the low power and we have seen the extension of kind of re-circulating buffer for multiple condo signal where there is priority how to design it how to code it and all that. So in next lecture we will try to take some more issues at timing issues and other issues of the state machine then I am hoping either take the VHDL coding of the state machine or we probably start looking at the PLDs so that is the plan. So today I am winding up I advise you to go back because we have covered quite a lot go back and review learn well I wish you all the best and thank you.