 Last class, we looked at how to get a bare silicon wafer starting from the ore which is quartzite. We first saw that we reduced the quartzite to get something called metallurgical grade silicon which is around 98% pure. We further purify the metallurgical grade silicon to get electronic grade silicon which has the purity of the required silicon wafer but is polycrystalline. We also saw that there are two techniques, one is the Chokralski growth technique and the other is the float zone technique which is used in order to get single crystal silicon wafers. Today, we are going to look at an overview on IC device manufacturing or IC device patterning. So the starting material for the IC device manufacturing is the silicon wafer which is what we ended up in last class. This is just the bare silicon wafer in the final configuration that we want. The end product is a silicon wafer containing the functioning chips which are then separated out and packaged into the final product. So this series of steps which start from your bare wafer and give you your functioning chip is the wafer fabrication process. So we can define wafer fabrication as a manufacturing process to create semiconductor devices in a wafer surface or in a wafer. So today, we are going to look at an overview of the wafer fabrication process and then in the next few classes, we will look in detail at some of the individual steps. But before we go to the overview, like to look at some definitions. The first definition is that of a chip or a die. Other common words that I used is a device, a circuit or a microchip. So all of these refers to patterns on the wafer surface that form one functioning unit. Out of these chip and die are the words which are most commonly used. A die is especially used in the context of a fab. Scribe lines is another term. So this refers to the areas between the different chips or dies on a given wafer. So a wafer is made up of a large number of dies. So the area or the space between them is called the scribe line. Now a scribe line can be blank or may also have some additional circuits that are especially used for testing. So it can be blank but more often or not will have some additional circuits for testing. Apart from the die, you also have things that are called the test die. So the die originally refers to the product which is finished and which has to be marketed. But along with those dies which are your product dies, you may also have things that are called test dies or engineering dies. These are again incorporated in the wafer and these are dies used for electrical testing. So this is especially useful when you are looking at product control or process control. You also have something called edge chips. The idea being that any wafer is approximately circular except for the flats. The dies are usually square or rectangle so that you will always have some amount of partial dies or partial chips at the edges. These partial dies are essentially called your edge chips. So with increase in die size, there will be a greater number of these edge chips and one way to minimize that is to increase the size of the wafer. To give you an example, consider the 22 nanometer technology from Intel. So this is called IV bridge which is the code name which forms your I7 processes, so I7 core. There are a bunch of dies here with different sizes but a typical die size is approximately 160 millimeter square. So if you are manufacturing these chips on a wafer then each die has an area of around 160 millimeters. So if you are going to use 300 millimeter wafer, 300 refers to the diameter of the wafer. You can calculate the area and dividing by the die size, you find that you can approximately make 440 dies. So this just assumes that you have dies that are spread throughout the wafer and you are dividing the area of the wafer by the area of the die. On the other hand, if you make the same dies on a 450 millimeter wafer. So this one is the 12 inch, 300 is the 12 inch, 450 is the 18 inch, then you have possibility of making 994 dies. Of course some of these dies will be edge dies or edge chips and may not be fully formed or only partial but you can increase the number of dies of a given size by increasing the overall size of the wafer. So let us look at some of the basic fab operations that are in use. These can be separated into different categories. So I will just look at one particular classification where we divide the fab operations into 4 major categories. So the basic wafer fab operations, they can be divided into 4 categories. The first one is called layering and we will look at each of them today. Then we have patterning, doping and heat treatment. So these are 4 broad categories into which you can divide your fab operations. If you think of your fab as an assembly line, then your wafer go through each and every step in sort of an assembly line process and you can have different combinations of this. So you have a layering step followed by a patterning step followed by say heat treatment and then doping and then layering and so on. So today we look briefly at each of these techniques and in the subsequent classes we will also look at them in detail. The first one we are going to look at is the layering step. So just from the term layering means you are trying to add a layer or a thin film to the wafer surface. So you are adding a thin film to the wafer surface. There are essentially 2 ways of doing this. So if you look at layering, you can have films that are grown onto your wafer surface or you can have films that are deposited. So in the case of grown films, you are consuming the silicon that is already present in the wafer in order to grow your new layer. So here in the grown films, the underlying silicon is consumed. So example of a grown film can include oxidation in which case you are forming an oxide layer by consuming the silicon. You also have nitridation where instead of forming an oxide layer, you are forming a nitride layer. In either case, the silicon in your wafer is consumed in order to form the oxide or the nitride layer. To give an example of oxidation, in oxidation your silicon forms SiO2. The simplest way to form this is by reacting silicon with oxygen. So oxygen is a gas. Typically, this is done at high temperature to form SiO2. This is called dry ox. Instead of oxygen, you can also use water or steam. So silicon plus H2O gas and just for balance, put 2. Again at high temperature gives you SiO2 gas plus 2H2. So here where you are using water is called wet ox. So in both cases, the gas you are supplying is oxygen or steam and the silicon comes from the wafer. Compared to grown layers, deposited layers are those where you deposit the layer onto your wafer surface and do not consume the underlying silicon. There are a variety of deposited layers. So they can be grown by chemical vapor deposition, thermal evaporation, sputtering. Both thermal evaporation and sputtering are actually called physical vapor deposition processes. Well, this one is chemical vapor deposition. It can also have electroplating. So these are some examples or some techniques of growing deposited layers onto the wafer. So let us look at some of them briefly. So in the case of a deposited film, the underlying silicon is not consumed, deposited layer. So we saw some examples of processes. One common example is an epitaxial growth process using chemical vapor deposition. So CVD, let me write the full form here. CVD stands for chemical vapor deposition. In the case of an epitaxial process, you are growing a new layer having the same orientation as that of the substrate. Epitaxial growth can be homoepitaxial, in which case the material is the same. You can also have heteroepitaxial growth, which case you are growing a different material. For example, in the case of a silicon wafer, it is possible to grow an epitaxial layer of silicon on top of the wafer. So this can be done by reducing dichlorosilane glass or tetrachlorosilane gas along with hydrogen. So SiCl4 with hydrogen gives you silicon solid plus 4HCl gas. So this reaction can take place in the gas phase and the silicon solid that is formed gets deposited onto the substrate and has the same orientation as that of the substrate. So this could be an example of homoepitaxy using chemical vapor deposition. Another way of growing epitaxial layers is called molecular beam epitaxy or MBE. So in this particular case, molecular beams of the constituents of your layer are directed onto the surface. So for example, if you are trying to grow gallium arsenide, you have a gallium source and an arsenic source. So both of these sources are used to produce molecular beams of gallium and arsenic, which are deposited onto the surface and form gallium arsenide. The advantage of MBE is that a very precise composition can be obtained. It is also possible to dope. For example, if you want to dope gallium arsenide with something like say sulfur or phosphorus or any other group 2 element, that can also be added as a source and by controlling the amount of material can get a precise amount of doping. So this is an example of a deposited layer both CVD or MBE. You can also get deposited layer by physical vapor processes. So in that case, you have thermal evaporation or sputtering rather I should say thermal evaporation and sputtering because both are physical vapor deposition processes. So they can be used for growing metals, oxides, nitrides and a variety of other materials. So first we have looked at layering, which is a way of adding a layer of thin film onto your substrate, the substrate here being the wafer. The next most important part, the case of the wafer fab operation is the lithography step. So the next step is called patterning, another name for it is lithography. So this is one of the most important steps in wafer fabrication because this is used in order to define the size or the dimensions of the various components of the device. So patterning is defined as a series of steps that is used to selectively mask or selectively expose parts of the wafer. So it is not one step, but it is a series of steps to selectively mask, which means to selectively cover or selectively expose, which is sort of the complement to mask portions of the wafer surface. So this we do because on these exposed regions you can do other things. You can do doping, you can do layering, you could do etching or you could do other processes on these portions that are exposed, so that you can build a pattern onto your wafer. So lithography is important because it sets the critical dimensions of the device. So remember with the increase in technology we have a situation where we are trying to pack more and more transistors in a smaller area, so that the individual device dimensions are all going smaller. So the latest technology right now is called the 28 nanometer technology. The next one is 22 and then it is 14 nanometers and 11 nanometers and so on. So this size here refers to a critical dimension of the device and this is governed by the ability to pattern the smaller and smaller areas onto the wafer. So the patterning process is also a highly defective process, highly defect sensitive. So if you want to grow things on a smaller and smaller area, then defect control is something that is very important. For lithography or patterning a reticle is usually needed, a reticle is nothing but the hard copy of the design that we want to pattern onto the wafer. So a reticle is usually generated by using a laser beam or an electron beam, so it is by a process called laser writing or for smaller dimensions you go for electron beam writing and usually this is done on a layer of chromium in the case of laser writing, a layer of chromium on a quartz glass or a borosilicate glass. So this forms the hard copy of the design which is then copied onto each and every wafer. So this is done by coating a layer of photoresist, so to make the pattern a layer of photoresist is added to the substrate or to the wafer which is then exposed to UV light through the pattern so that some portions of the photoresist is exposed while other portions are blocked. This is then developed, so this is the language very similar to a film camera and after developing and removing the photoresist the pattern is formed onto the wafer. Sometimes an oxide mask can also be used for patterning instead of a photoresist, those types of masks are called hard masks. So you could use an oxide layer for patterning, those are called hard masks because they can typically withstand high temperature, a pattern that is formed using a photoresist is called a soft mask, it can typically withstand a few hundred degrees but definitely not much more than 200 or say 250 degrees. So we have looked at layering, we have looked at lithography, the next thing we are going to look at is doping. So doping is something which we have seen before right at the beginning of the course, it is a process of adding electrically active impurities, so you want to add specific amounts of electrically active impurities to your wafer in order to get desired electrical properties. For example, if you want to form a P N junction and your starting wafer is N type and you typically add P type impurities or P type dopants to form the junction. So your dopants can either be P or N type dopants and we have already seen examples of them in the case of silicon. There are two main techniques for doping, you can either dope by thermal diffusion or you can dope by ion implantation. So thermal diffusion as the name implies is a diffusion process, the dopants are delivered to the surface of the wafer which is at high temperature. So the wafer surface is maintained at high temperature and then the dopants just diffuse into your material, so this is at high temperature and you have your classic diffusion. So the dopants can be delivered either in a solid form or in the form of a vapor or in the form of a liquid, so you have different sources depending upon what type in which you are delivering the dopants. This will also affect the concentration profiles of the dopant within the material, so whether it is a solid or a wafer will affect how the dopants are then distributed into your material. So because thermal diffusion is a high temperature process, you cannot use lithography in order to pattern it, usually an oxide layer is used for patterning. So the other way of doping is called ion implantation, in the case of ion implantation the sample is maintained close to room temperature, wafer is at room temperature, the dopant atoms are ionized and these ions are accelerated and impinge on the wafer surface and then get embedded. So you are doping not by diffusion but by implantation of high energy ions. So here because the wafer is at room temperature, you can also do conventional lithography, so you can dope really small regions. The case of ion implantation though, the fact that you are hitting your wafer surface with high energy ions can lead to a wafer surface damage. So usually some sort of annealing is used post ion implantation, so you do annealing post implantation to repair the surface. So we have looked at layering, patterning and doping, the last classification is heat treatment. So heat treatment operations are usually a part of the other three, so sometimes it is not always essential to treat it as a separate step, it is closely incorporated with the other three other three categories. For example, in the case of layering where we deposit a layer of metal, a heat treatment operation or an annealing operation can follow it, in order to react the metal with the silicon to form silicites. So this is especially useful for forming good electrical contacts. In the case of doping with ion implantation, once again you can have a heat treatment post implantation to repair the damage in the wafer. Similarly in the case of lithography, when you first put the photoresist layer on to the wafer, you do a soft bake which is a soft annealing step in order to remove the solvent and then after exposure and development, you do a hard bake in order to harden the photoresist layer. So in these of these cases, these are all heat treatment operations which are fully incorporated with the other three. So we have looked at an overview of the various fab operations. So you can always think of the operations in a fab as sort of an assembly line where your wafer goes from one step to the next and undergoes some process. So let us look at an example of fabrication of a device starting from a blank silicon wafer in order to understand how these various steps play a role. So we are going to look at an example fabrication process and the process we are going to look at is the formation of a MOSFET device on silicon. Your MOSFET is nothing but your metal oxide semiconductor field effect transistor. So we have seen a MOSFET device before. We have also seen how the device actually looks. We have seen the schematic of the device. So now we are going to look at the various steps to actually form or fabricate this device. So the first thing is of course your starting wafer. This is the bar silicon that enters the fab. So this is just the wafer. So on this bar wafer you are going to grow an oxide layer which we will use for patterning. This oxide layer is called a field oxide. So the first step is your layering step or your layering operation. So this is to grow the field oxide. So this is an oxide layer that is grown on to the silicon layer. So this could be by dry ox or wet ox but either way underlying wafer that is once we are done growing the field oxide we are going to go to a patterning step. The case of a patterning step we want to open a window in the field oxide so that we can deposit the gate oxide and also the gate. So if you remember a MOSFET device a MOSFET has a gate and a source and a drain region. So the first thing you are going to do is to make the gate. So for making the gate we use patterning and we use the appropriate mask. So mask we will look at later but we use the appropriate mask to create a window. So you create a hole in the field oxide and now you are going to grow an oxide layer. So this oxide layer is the gate oxide so this is again a layering step. In earlier technologies usually SiO2 will act as the gate. Later silicon oxenitrides and now even some high k dielectric materials are used as gate oxide but whatever be the oxide it is basically a layering step. So now you have created your wafer or you started with your wafer. You created a hole in the field oxide and then you have grown the gate oxide. So this is my wafer, so this is the gate ox and this is still the field oxide. So this diagram actually combines both these steps both the patterning and the layering step. So after growing the gate oxide you grow a layer of polysilicon on top of that this is to form the gate. So the gate is usually a highly conductive material it can either be a metal or in this particular case we can use heavily doped polysilicon. So in this step you are another have a layering step where you grow a layer of polysilicon this is typically grown by chemical vapor deposition. So if you look at the diagram once again I have my wafer, I have my field oxide layer, I have my gate oxide and then I am growing a layer of polysilicon on top. So it is my wafer, this is polysilicon, this is gate ox. So we then need to define both the source and the drain. So if you remember in the case of a MOSFET let us say you have a P type silicon your source and drain are N type silicon so you need to do some sort of doping. So the next step is to do the patterning in order to create two openings for source and drain. When you do the patterning you will also remove the excess polysilicon so that you only have polysilicon in the gate region. Now if you look at it wafer field ox I only have my gate oxide in the center and then I have the polysilicon gate on top. This is the gate and you have two windows that are open for forming the source and the drain. So after patterning the next operation is doping. So the underlying wafer is P type, your doping will be N type and the underlying wafer is N, the doping will be P. You can either use a solid doping or a liquid or a gas either way you can diffuse some material in order to create the source and the drain. So after doping you again have to pattern in order to make the electrical contacts. So the first step to do the patterning is layering so you grow an oxide layer on top. So this is for patterning electrical contacts. So let me draw that my wafer, I have my field oxide from the start, I have my gate oxide and gate, I have two regions which I have doped to form my channels, I am going to assume my wafer is P type so that the two source and drain are N type and then I have an oxide layer on top. So this is patterning. So after layering we again do the patterning step, sorry this is doping and layering combined. This refers to these two. So after layering we do patterning in order to create holes in the oxide so we can deposit the metal and form interconnects. So we do patterning in order to create holes for depositing the metal. So the metal layer could be something like say aluminum, so the metal layer is deposited so this could be done by a physical wafer deposition process like say sputtering. After we deposit the metal we go for another layer of patterning in order to remove any excess metal because this is a uniform deposition so it will go all over the place. So we want to remove the excess metal and then finally some sort of a heat treatment is done so that the metal layer will react with silicon to form a silicide which gives a good electrical contact. So if you look at the final structure of the device, so you have your wafer which is a P type wafer, you still have the oxide layer at the both edges. So this oxide layer basically acts to separate one MOSFET from the next. You have two regions which are doped so they form your source and the drain and then you have a gate oxide and then a gate retain. You also have electrical contacts that are made. So these refers, so in this case I am first drawing the oxide isolation but you also have electrical contacts to the source, to the gate and the drain. So this is your source, that is the drain, that is the gate. These are the contacts, so typically aluminum. This is the polysilicon gate that is the gate oxide. So in order to form this MOSFET starting from bar silicon we go through a series of steps. In this particular example we have approximately 12 steps in order to get the final device. This series we have not looked at inspection or looked at various steps. So usually you also have inspection steps that are also included along with this. So this is just an overview of the various processes that take place during IC device manufacture. In the next few classes we will look at each of these in detail. So we understand how the processes actually work.