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Published on Mar 24, 2014
In this interview NVIDIA's Syed Suhaib recounts their DVCon 2013 paper, "A Formal Verification App Towards Efficient, Chip-Wide Clock Gating Verification". In a nutshell, ensuring correct clock gating has been a major verification challenge. In this interview/paper Suhaib describes the automated methodology for exhaustive clock-gating verification using Sequential Equivalence Checking (SEC) analysis with Jasper's SEC formal verification "App". They found multiple bugs across many projects using this approach, where over half of the bugs were found after supposedly high simulation coverage of the design.
Full paper citation: DVCon 2014, Session 2.2 A Formal Verification App Towards Efficient Chip-Wide Clock Gating Verification Syed Suhaib, Scott Fields, Prosenjit Chatterjee - NVIDIA Corp.