 Hello, and welcome to this presentation which describes the DMA-2D addressing mode supported by GPDMA. This is not to be confused with the Chromart accelerator controller, also known as DMA-2D, which also implements 2D addressing mode. This slide summarizes the addressing modes supported by both LPDMA and GPDMA. LPDMA and GPDMA implement the following addressing modes. Fixed addressing, typically used to access a peripheral data register. Contiguously incremented addressing, typically used to access memory in ascending address order. The maximum block size is 64 kilobytes due to the 16-bit field called BNDT, which stands for block number of data bytes to transfer. The GPDMA channels 12 to 15 implement additional addressing modes. Repeated block mode based on a programmable counter, programmable source and destination-signed burst address offset, programmable source and destination-signed block address offset. Thus, two programmable strides can be inserted between consecutive bursts and between consecutive blocks. This figure highlights the repeated block mode and the stride between blocks. This mode is useful for transferring the contents of a peripheral data register, typically an input FIFO to non-contiguous buffers in memory. After filling a block of N-words, the DMA channel automatically adds the BDRA0 signed offset to the current address, jumping to the next buffer in memory. At the end of the transfer, when k-blocks will have been transferred, the CXDAR register, which points to the beginning of the first buffer, can be automatically restored in order to implement circular buffers. This automatic restoration requires a link operation. In this example, bursts are placed contiguously in memory, so the burst destination address offset sets in the BDAO field of the CXTR3 register, must be null. For performances, destination transfers can be programmed as forward bursts. This figure highlights the repeated block mode with the stride between bursts and the stride between blocks. The GPDMA transfers k-blocks of j-bursts, each burst containing i-words. The stride between blocks is useful for transferring the contents of a peripheral data register, typically an input FIFO to non-contiguous buffers in memory. The stride between bursts is useful for interleaving or deinterleaving data, and also for aligning data. Some use cases will be described in the next slide. The first use case of burst stride is 24-bit extension and packing. A source buffer contains data and control pairs. GPDMA channels 12 to 15 are capable of extracting the data field and packing the resulting 24-bit data back-to-back in the destination buffer. A burst address offset of plus one byte and a burst length of three bytes can be programmed for the source. No burst stride is required on the destination. The destination can be programmed as a four-word burst for best-right performance. The second use case consists of deinterleaving stereo audio samples in two separate buffers, one containing the right samples, the other the left samples. There are several possible implementations. One can be based on two GPDMA channels, one for the left samples, one for the right samples. Then, if the source buffer contains two N samples, the even samples may be read by a programmed source one-word burst with a source burst address offset of four and a source block size of four N bytes, and the destination can be programmed as a four-word burst for best-right performance. An alternative implementation can allocate a single GPDMA channel, a source with a burst of one word and a source burst address offset of plus four, a source with two blocks, one source block being two N bytes, a destination with four-word burst optimized writes, optionally with the destination block address offset. In the last use case, data is deinterleaved and packed into three buffers. This could deinterleave the color components of RGB pixels. Similarly, a single channel or three channels can be used. In addition to this presentation, you can refer to the other presentations on the GPDMA and LPDMA. DMA overview, DMA transfers hardware and software views, autonomous DMA and low power mode, DMA circular buffering and double buffering, DMA register file, DMA error reporting, DMA linked list, DMA input output LLI control.