 Hello everyone, welcome to the session 2 of unit 5 static timing analysis. In this session we will talk about the interconnects and delay calculation. Now the agenda is we will see what interconnects are what are the interconnect bias interconnect models. We will see the bio load models there is some overlap with what we studied in unit 3, but there are a couple of more we will go a bit more detail into bio load model. We will look at parasitic formats and then we will look at delay calculation. Now going back to the session 1 of static timing analysis we learned that static timing analysis is of 2 parts. The first is the delay calculation and the second is the checking against the constraints. So,it is the first part we will concentrate on the delay calculation part. Now delay again is comprised of 2 elements. So, 2 elements are responsible for the delay one is the cell other is the next. The cell delay comes from the library we all know that actually not the not the in the NIDM format. Yes, the delay is the delay numbers are represented in pickup table and a tool like prime time just has to do interpolation based on the transitions input transitions and output load. On the other hand, so that the internet delay an STA tool does not have the net delay directly. It will always gather the value of resistance and capacitance of the net and then it has to do the delay calculation using some method some formula. So, that is the concept we will look at in this session. So, a net the properties of net are net is a wire connecting pins of standard cells and blocks. So, any tool tell would be connected by an by an interconnect or a net and a net obviously has only one driver. There are nets that has have multiple drivers, but in that case consider a net that is being driven by let us say two drivers one of them will be in a tri-state at any given point of time. So, in effect effectively there should be only one driver and a net what is a driver will be a cell. The cell will drive the net value to be the 0 or 1 depending on this logic state. So, it is it has only one driver for any effective calculation. Net gain driver number of fan out cells or blocks. So, you can have only on one side you have a driver on other side you have the receivers. Now, there can be there is always one driver, but the number of receivers can be many. In that case net will be segmented obviously. So, let us say a buffer is driving four other buffer. So, there will be there will be one net going from the output of the driver buffer and then the net will be segmented and then it will drive the different announced. Now, this segmentation can happen in number of field physically I am talking about physical logically it is only it will be just one net there is only one logical net from driver to force another receiver, but physically the segmentation can happen at number of all it depends on the routing on the timing constraints and so on. And then the net can travel on multiple metal layers of the chip. Now, a chip is three-dimensional in the sense that you have a chip is comprised of layer. So, at the bottom you have the diffusion layer the poly which makes up the standard cells and over and above that there will be metal layer going throughout the chip that will connect the drivers and receivers that will connect the standard cells together. Now, these metal layers are numbered like metal 1, metal 2, metal 3, metal 4 and so on. So, a typical 65 nanometer process or a 45 nanometer process might have 6 metal layers or 8 metal layers and so on. Usually they are about 6 to 8 metal layers in a particular process. So, if metal 1 is horizontal metal 2 will be vertical and so on. So, 2 consecutive layers will be vertical and horizontal to reduce signal integrity. So, a net can travel on multiple metal layers of the chip and it can be broken up into segments for equivalent electrical representation. We will see what segments are and how does STA tool uses those segments. This is just to make the clarify the concept of inter-connect. Now, inter-connect will have 3 parasitics parasitic means unwanted parasitic by literally means something with a feeding of some parasite is a something that feeds on a host or it is undesirable not needed. So, the R, L and C for an inter-connect are undesirable. So, we would want to use technique to keep the numbers as low as possible right. Inter-connect resistance is between the output pin of a cell and the input pin of the fan out cell. Inter-connect capacitance the every node every input of a cell or every output of a cell or every net itself will have some capacitance with ground and 2 nets running 2 nets will have some capacitance between them this is called coupling capacitance. There is some inter-connect inductance also which arises due to parent loops, but it the value is so low that it can be moved. So, for ASIC design on chip inter-connects do not show significant inductance. Although on a PCB since there are long wires running they show a significant inductance and has to be taken into account for calculation, but when we talk about something that is fabricated on chip the L value is not of any conservation. So, we will only talk about R and C value and why they are undesirable any resistance will consume power will make the chip heat up. So, obviously our target is to reduce the resistance as low as possible this is why a copper inter-connect is very very popular. Again capacitance the higher the capacitance the more time the more current needed to charge it up to VDD and then to this this charge it to ground. So, the more cell the more net delay that is why again there are techniques to reduce capacitance you would probably study in one of the fabrication courses. There are there are techniques to so again we talked about there are two types of capacitance one is with respect to ground other is with respect to the between two nets. So, since we will this is the reason why a metal one let us say the horizontal metal two become vertical just to reduce this coupling capacitance. The coupling capacitance causes what is a cause and effect which is called noise we will see that STA tool also handle also tweak also sign of the chip for signal integrity through what are those what are those issues and how do we check for them. So, that is why these R and C values are called parenthesis. Now a typical inter-connect will have a length L and it will be represented as a this as a distributed R R C 3. What it means is that the trace of length L will be broken down into number of R values R and C values. So, this is distributed R C 3 and now STA tool will employ some techniques to calculate the delay from this node to this node. Let us say this node is driven by a cell by a buffer and on this node there is a receiving buffer. So, what STA tool will do it will try to so, there will be a waveform here and there will be a waveform here. So, what STA tool will try to do it will try to calculate delay between these two points it will use some algorithm and it will try to calculate the delay for this distributed R C 3. In fact, delay calculation for NETs takes much longer time when compared to delay calculation for cell. The only reason being that the cell delays are represented in the lookup table and the only thing the tool has to do is interpolate. But for in this case it has to employ some sophisticated numerical analysis techniques to calculate it there. Now we will define two terms here RT and CPR the total resistance and capacitance this is interconnect of length L RT is equal to RP into L CT is equal to CP into L where the RP and CPR the per unit length values and L is the trace length. Now so, there are various models to represent interconnect some are more accurate some are less accurate the less accurate ones obviously will take two less amount of time to process through because there is less data the more accurate the model is the more time that you take the tool to calculate the time to calculate the delay. So, one of the models is T model in which total capacitance CT is a model is connected half way in the resistive three and the total resistance RT is broken down into two part RT by 2 RT by 2 this is called the T model other model is the pi model in which the RT is in between two capacitances and CT is the one that is broken down into CT by 2 and CT by 2 and RT is the total there is some typo here total CT is broken down into CT by 2 and RT remains here. And then there is a much more accurate and friction representation it is more accurate so, when you keep increasing the value of N it will it keeps on becoming more and more accurate, but obviously there has to be some limit because the more sections you have again the more compute intensive it becomes. So, again it has two models T model and pi model. So, T model in both the models CT is divided into CT by N and RT is divided into RT by N the only difference is that in T model the first and the last value is RT by 2 N and in pi model the first and the last value is CT by 2 N. So, these are these are just modeling techniques. So, in effect in physical effect there is one single copper wire. Now, there are multiple techniques to model is and these models again the more sections you divide it into the more accurate it becomes and the more compute intensive it becomes. This is this session is more about the available techniques to do this thing, but ultimately when we use prime time when we go to static timing analysis tool we are not worried about what model is used. The model use is dependent on what detailed parasitics have been fed into prime time, but otherwise we should not be concerned about what is the model use whether it is N section model, whether it is a T model or a pi model. Once we are given the parasitic data we just read it into prime time and then using report timing we can report the value of capacitance and resistance, but that value is this is the combined load. For example, the report time report will show the combined value of capacitance at any pin right it will not show the section information, because again it is an it is just the way prime time will reduce things it will calculate delay we do not have to be we can just read about it, but when we do static timing analysis we should not be too concerned about it. Now, let us see now in the case in case of free layout SBA when the parasitic information is not there we use something called wire load model which are used to estimate gap or the area overhead and the length of the net based on the number of its final. Let us take an example how do we do that we have already seen that there are different wire load models in standard cell library for example, here it is given there are three models given light conservator and aggressive. It also tells us for what area it is suitable and so on. Now, this is an example where a wire load model tells us gives us some numbers one is the resistance number I think it should be per unit length capacitance number per unit length area per unit length this is the slope of the curve and now it tells us that for what find out what is the length let us say for find out one length is 2.6 for find out two length is 2.9 for find out three length is 3.2 and so on using this data what the tool will do for each of each of the net it will try to calculate the RNB and the length and the area value based on these numbers. Let us see how does it do that we clear the annotation first here. Now, now let us see let us take a look at an a net which has a fan out of 8. Now from the previous data we see that for find out length of 5 this is for find out of 5 the length is 4.1 this is the maximum that wire load model specifies. So, for a fan out of 8 the tool will try to extrapolate. So, for for the value of for value of 5 it is 4.1. So, it uses simple a straight line formula to calculate the value at fan out of 8. So, what it does is it 4.1 plus 8 minus 5 which is the this offset into the slope this is by slope is 0. So, help us help the tool in doing the interpolation and extrapolation right. So, length is 5.6 now based on this length it can calculate the capacitance because it knows the length and the capacitance coefficient which is which is 1.1 the resistance coefficient is 5.0 again we have got the value of resistance again area overhead is length into area partition and then so on. So, this is how they based on the wire load model data the tool is able to calculate for every net just by knowing the fan out it will calculate the length capacitance resistance and area overhead again these are just estimate the things change a lot when we go to post layout. Now when when it when we talk about wire load model for estimation the tool will consider there are there are three. So, first it will choose a wire load model based on area for example, and then it it needs to know what three type is targeted. So, there are three three types you can use we will see in the lab that we have already noticed this this term this term has come across in when we saw the standards the lab it it mentions the tree type in the in the best case tree or worst case tree and so on. Let us see what this three type is. So, in the best case tree it is assumed that destination pin the load pin is right next to the driver what it means is that there is no resistance from the driver to the destination pin and, but the only thing are being considered here is the cap the pin capacitance right. So, what that is why it is called the best case tree because it assumes the resistance to be 0. So, this R is not accounted for all these these receivers and the drivers it is assumed that they are sitting next to each other and there is virtually no resistance the only thing taken is the pin capacitance of each of the each of the receiver pin. It is obviously an optimistic case second is the balance tree now in balance tree the R and C is equally divided among all the receivers all the signouts. So, the total R resistance being R wire total capacitance being C wire this this section has R by C R by N and C by N this section has R by N C by N this is a balance tree. First case tree what it assumes that the destination pin each of the destination pin sees the complete resistance it is this this will only happen when these the fanouts are the the receiver cells are sitting right at the end of the wire per end of the wire. So, the first case assume the best case assume that this receiver pin is right sitting right next to this one the balance assume that each of the fanout is because the receiver cell is at equidistant from the it is at equidistant point from the driver. The worst case tree assumes that all the receivers are sitting at the power end of the driver and each of them will see the complete R and C. So, obviously, this is a this is a worst case scenario. So, that the typical scenario will lie somewhere between worst and best which is the balance tree. So, again this is a violored model characteristic characteristic and not the real parasitic characteristic which is what kind of layout is assumed right. So, usually you do not need to worry about it and it is some of it is set in library by default. So, when you do a report violored model you can see that what what kind of trees taken or you can open up these standard cell library and see that. So, this is the command to specify a violored model we have already seen that in design compiler the command is exactly same for fine time in that sense. Actually in preview out when you talk about the preview out stage the design compiler and fine time they behave exactly same in the sense that most of the commands are similar and the only thing different is that fine time is a much more advanced SPA tool and when you want to work with real parasitics we cannot work in design compiler. So, there is a the timing engine inside design compiler is faster compared to fine time it has less features and it is more throughput to synthesis whereas, the prime time sign-off engine is built for sign-off at various technologies it has much more it is much more accurate it is the data the calculation math will be successful and it has lot more features to aid us in doing static timing. But at a preview out stage there are very few differences. So, we have also seen violored modes top enclosing segmented I will quickly revise them the top violored model the violored model of the top level is used for all the lower level blocks in case of enclosed the violored model that is used for the design which encloses the complete net. So, for example in this case WLM light encloses this complete net. So, the violored model WLM light would be used the segmented violored model divides the hierarchical net into segments and a unique violored model is used for each segment that depends on the design and the under wish this net is imposed. For example, this part of the net this part of the net is enclosed inside B3 and WL under score AGGR is used for B3. So, WLM this basically I will be used for this segment for the second segment WL light will be used for the third segment WL under score TYP will be used. So, we have already seen this that is why I have been cooking over it this is how violored model is represented in the send apathy we have already seen this in unit 3 I will move forward. Now, let us come to the actual parasitic data when we are working post layout state. So, where two parasitics come from? So, first we give the synthesized net list to the physical design team or the guy or the person who is doing physical design it can be you or it can be some other person. Now, the design along with constraints is taken through the back end the design flow the first part of the flow is placement then it will there will be clock 3 synthesis and then it will go through detailed routing after routing when the physical data is completely generated GDS is generated there are tools extraction tools which from the layout now the layout has all the information about on the net and send placement right. So, these tools one of the tool is called StarrRTXP function options. So, this tool will take read in the layout data it will read in the technology specific files which has the information that what is the thickness and what is the what are the coefficients for different metal layers using those that data it will generate the parasitic file. Now, these parasitic files can be in one of the three formats either they could be in the format DSPF detailed standard parasitic format or RSPF reduced standard parasitic format or SPF which is standard parasitic expected format in one of these. So, the tool will extract the data and it will put data into a file which will conform to one of these three formats. Now, the most detailed format is DSPF the format is same as files what it means is that each node is extracted the RLC value will be present for each and each and every node and obviously, since it is represented in spice format and you can use any spice tool to read in and analyze, but again at a full chip level it will become very very time consuming and plus this file is huge for even a simple design this file might run into be or or hundreds of md right syntax is obviously, too detailed because there is lot of information here and it is used for only very special cases where you want to see when you want to do some spice analysis. Spice analysis will be more accurate than prime time or any other static time analysis tool again it takes so much more time right. On the other end of the spectrum is a reduced standard parasitic format RSPF in case of RSPF the parasitics are represented in reduced form. So, what is reduced not every node is represented for example, take a look at this design where a CK buff is a buffer is driving two flops now in this case it will be straight into two parts one and two. The first part which is the this is called the driver model a driver will be represented by let us say a pi interface and then the receivers will be represented by again RLC value and now at the receiver end the driver will be reduced to a a voltage source voltage and current a voltage source or a current or a current control current source. This RSPF can also be used to as an input to spice simulator there are some limitations here I think one of the limitations one has written here the bidirectional input cannot be represented and I am not sure if coupling capacity if and it if it has coupling capacity and I do not do it without. So, it does not have coupling capacitance capacitance. So, you cannot do signal integrity or noise analysis using this RSPF and there is one format called SPF which is which is the most popular industry format for static time analysis why because it is balanced in the sense that it is not as detailed as the SPF, but it has a enough information what it means that it has detailed parasitics up to the next name it also has coupling capacitance capacitance, but it is of a similar format as a DSPF similar to the spice it does not have every node. So, it does so the the approximation is done at the level of the extraction tool the extraction tool will make some approximations or it will make some do some modeling and it will come SPF which will be slightly less detailed than DSPF, but it will have the coupling capacitance on it. So, with with SPF we can do noise and signal integrity analysis. So, this is the most popular industry standard format and I also use this a lot in on the chips I am working on. So, again we would be talked about that every time our wish will be to reduce the interconnect resistance and capacitance both some ways are listed here one of the way is to make the nets wider a wider net will have lower coefficient of resistance and the obviously the resistance of a net is inversely proportional to its area area of procession of the bit. So, the more wider a wire is the more current it can carry easily and resistance goes down. Routing in upper thicker metal in a fabrication process the metal layer at the top of the stack are more wider and thicker. So, usually have lower resistance and most of the time they are used to route power signals and clocks which are most critical in the design. So, power signals are very critical why because an increased resistance of on power signal will cause more IR drop issues the more are the more IR drop that is why power signals will use the top most routing layers to reduce the resistance to as much extent as possible. The top level layers are also used for clock routing because clock is a signal that goes to goes globally it finds out to so many register and the lower mean clock you do not do not want to have signal integrity issues on clock it will cause a lot of problem that is why you use upper metal layers. So, these are two ways either we use wider metal metals or we use the upper metal layer there by default. Now let us see how do we read parasitics in time time. So, read parasitic command read the parasitic data file either in spare for RSPF or there is one more format called synopsis by any parasitic format it just converts the ASCII format we cannot just read this any ASCII format parasitic file into prime time and into some in design and prime time I think and you can write out the parasitic format. So, this the process of reading parasitics and mapping it on to design is called back annotation and the parasitic command by default it can recognize the file format from the file itself. So, so giving the specifying the format is optional obviously, the net an instance bin name in the design must match the corresponding net an instance bin name in the parasitic file a parasitic file should have one to one correspondence with the design if not then what may happen is that some of the nets will not get the data. So, when reading the parasitic file by default PT assumes that the capacitance inside spare does not include the pin capacitance the pin capacitance value always comes from the standard cell actually. So, again delay has two parts cell delay and net delay a cell what properties does it have a cell has the delay is represented in the lookup table, but it also has capacitance on the node each input and each output of an output of a cell both has some in nm pin capacitor and that capacitance value goes in the standard cell library not in the space will only contain interconnect data not cell data although it would connect. So, it will tell us what the nodes are for example, in this case let us see this design what inter what the special contain it can it will contain this node instance name slash z pin to FB FF 1 slash CT pin and this is one net. So, it will contain the RNC value of this net, but the capacitors inherent capacitance value of the bus at z and of the flip flop at CT will come from the standard cell level. So, just the thing to remember here is that parasitic SPF, SPEF or DSPF or SPF they just contain the interconnect data that is it. So, the reduced and reduced parasitic RC networks specified in that file are used to compute effective capacitance we will talk about what effective capacitance is. So, this is a part of delay calculation. So, the capacitance value this is most important thing this you should this is the thing that you should remember the capacitance value reported by a most report command such as report timing or report net is the lumped capacitance what it means is that. Now a net an internet will have multiple segments, but during the process of delay calculation what time time will do it will calculate a single value which is the effective capacitance this is to speed up the delay calculation and it will show this value this lumped value when you do a report timing or do a report measurement it will not show us that how did it calculate the effective capacitance it will not show us how many segments were there it will not show us what algorithm it used to calculate this value of C. So, we have to make we have to note that value of capacitance we see in any of the commands we do is the lumped capacitance or C total C total is the sum of all capacitance value of a net. So, usually in most of the cases it is the sum in case of NLDM I think it is the sum, but I have never verified whether for a particular net that all the capacitance inside the sphere plus all the pin capacitance are they is C total this simple sum of all amount I am not sure, but again the thing to remember here is that any report you do will report a single value of cap at a particular moment and that will contain the effect of the pin cap plus the net cap. Now, let us come to delay calculation. So, to perform STA prime time must accurately calculate. So, for prime time calculate is perfect calculate the delay through each cell whether it be combination or sequential it needs to calculate the delay for AND gate from the A to pin output from B to the output or sequential cell it will be from top to Q. And second thing at each node it needs to calculate the transition why because again the delay depend on the transition value for example, the delay at the output of an AND gate a 2 input AND gate will depend on the load at the output plus the transition at input again let us. So, there will be let us say there is one buffer there is one buffer let us say driving another buffer. So, to calculate the delay here to calculate the delay is at this point prime time needs to know the transition at this point plus the load at this point again to know the transition here prime time this transition here will be some function of the transition at this point again delay is calculated at this point at this point and transition is calculated at this point. So, at every node prime time needs to calculate delay and function both at every stage a stage any stage it comes comprises of a driving cell the RC network in between and plus the receiver cell the network the load fields right. So, what is the goal the goal is to compute the response at driver output and at the network load points given what is what is given value given the input slew input transition is a in is a requirement of prime time to calculate the output delay plus the output transition. Let us see a figure which will explain it all. So, let us see for example, on the left hand side you have a net lift simple circuit without any RC value when it goes to a little design it will get the RC value and the network will look something like this something like this one on the lower end with a different R values and different C values right. So, the on the upper on the on the top the figure does not have any R values only the C values. So, this this tells us the C these values are the ones that are coming from the label these values these are the pin cap values which are coming from the label itself. Here this R value this R value and this C value this C value they come from the set from the parasitic data. So, when we have the non-linear delay form delay model which comes from the standard cell that means. So, standard cell that we will define some lookup tables or delay and transition both this type of model is called non-linear delay model. The non-linear delay model is slightly going out of you present day in lower technology 65 nanometer is beyond CCS constant current source model is most popular, but that is outside the scope of the course. So, we will only talk about non-linear delay model it does not as a as a synthesis and FMA engineers you do not need to be concerned a lot about which model is the MNDM or CCS or something like that. We are we are more this is these are two related things and these they go in conjunction with what is the last one who is the library vendor what is the parasitic data and so on. So, we should just know about it what is it is being used you can go ahead and read about the CCS, but the more important task as at hand in how to define the constraints how to make sure that a design is fully and properly controlled that is the goal of SDM right and next step we should know how to solve the time inversion that is the next step before signing off. So, we will talk a bit about NLDM. So, in case of NLDM any circuit let us say a circuit like this prime time then divided into three parts one is the driver model. So, let us say we I have again a buffer driver buffer. So, this buffer is a driver it will be represented by a driver model this interconnect here in between will be represented by a reduced order network model and the buffer the the receiver buffer here the load buffer here will be represented as a receiver model these three things here they tell us that the turn out is bigger example. Now, the driver model is intended to reproduce the response of the driving self circuitry when connected to arbitrary RC network what it means is that the driver model of a buffer for example should be independent of the interconnection type where does the driver model comes from the driver model comes from the standard cell level right. So, here at the driver at the driver level prime time will assume will will calculate the waveform and where does this waveform come from it comes from some load here. So, this load here is the pin capacitor and the input transition. Now, this input transition would be a result of a previous stage calculation or it is a primary port and you have set input function here whatever, but this is a driver model for NLDM this driver model should tell us what is the waveform what is the nature of the waveform that is it. Now, the the receiver model is intended to represent the complex input capacitance why complex because the capacitance there is not a fixed value and it just depends on how the this is what is is more accurate in CCS when compared to NLDM this calculation. So, it represents the complex the complex input capacitance of the ster input pin of this input pin of this buffer here including the effects of rise for direction the transition of this pin slew or run through anything the receiver output load the state of the cell and then so many things right. So, the the receiver the receiver buffer here is reduced to a single C effective value. So, this value here C is nothing, but the C effective value the reduced order model the network of this one is a simplified representation of the full a static network here. So, this is where this is where prime time will employ some optimized some algorithms to calculate the the delay through this RC network. So, any network any a parasitic network whatever comes from spare will get reduced to a very simple simple circuit which prime time will calculate the delay. So, please please tension time in reading this and understanding this how does the prime time reduce a network and represented into a driver model a reduced order network model and a receiver model. Now, let us talk about the effective capacitance. So, what is effective capacitance I summarize again effective capacitance is a single capacitance value in case of NLGM you know that the effective capacitance is very very specific to NLGM is a single value of capacitance which is used to represent the load the fan out load of a single set right. So, effective capacitance approach is employed to handle the effect of both R and C it is a single capacitance that can be utilized as an equivalent load. So, in this case we RC interconnect. So, what prime time will do it will reduce this RC interconnect into something like this where C effective where this is the driver model and this is the C effective effective is nothing but a single cap value which will replace the load right. Now, effective capacitance as we discussed before in the function of so many things. So, this is let us say one one one particular graph where the total capacitance is mapped the actual load is mapped and then effective capacitance is calculated. Now, we see that there is obviously some difference. So, this effective capacitance would be different from the total cap. So, total capacitance. So, total capacitance I guess would be the would be the most inaccurate because it will not take into effect it will just be the sum of all the capacitance it will not take into effect the rise and fall transmission and so on. The actual load I guess would be should be most accurate because it will be segmented load. Whereas, effective capacitance is something that STO would calculate to make the job faster calculate that they were faster otherwise it will be after 5. So, that the the idea the aim of behind STO is calculating C effective is first to make the delay calculation faster and second it should not be too inaccurate it should be within some percentage of the 5 calculators right usually they will target about 2 to 3 percent power. Third is the l more delay l more delays are applicable for R2 please. So, this is what l more delay is a very very basic formula used to calculate the delay of an output. In case of when you read steps prime time will not use l more delay it will use some some other calculation which I am not sure about what it is you do not need to worry about that. Only when you when you when you read in a reduced static format an RSVS only then prime time will use l more delay because l more delay is a is a very proved approximation and RSVS only RSVS does not contain a lot of parasitic data it already has a reduced format. So, l more delay is applied only when RSVS is there it has a single input note does not have any resistive loops and all capacitance is at between node and a ground for such networks prime time will employ l more delay. So, let us see what l more delay equation is. So, any network which has to be R and C. So, any network which can be segmented into such a the l more delay is. So, the delay through the first question is C 1 R 1 the delay through second section is. So, if we talk about the delay through at 1 it will be C 1 into R 1 at 2 it will be C 1 into R 1 C 1 into R 1 plus C 2 into R 1 plus R 2. So, at any node it will be. So, this is the generic formula 3dn is equal to summation of C i and then each of the capacitance multiplied by the sum of all the resistances seen by for example, at at C i the delay would be C 1 R 1 plus C 2 R 1 plus R 2 plus C i minus 1 R i minus 1 plus R 1 plus R 1 and so on. At node i it will be C i into. So, assuming the all the R values are same R 1 let us let us assume everything to be R. So, it will be C i into n times R plus C i minus 1 into n minus 1 times R and so on. So, this is the equation for l more delay again this is a very very basic formula might now be very accurate, but it is used by prime time when you route read R SPS. Now, there is a very interesting case of slew merging. Now, now at any node at any node like like let us say a NAND gate here at that prime time can have only one transition value prime time cannot maintain multiple transition value at every node. Otherwise, this will blow up the delay calculation problem. So, prime time maintains only one value that value will have two limits mass and a minimum. So, in fact, two values, but the mass and a minimum. So, now the the transition at z will depend since it has two input pins the transition at z will depend on both the transition at input A and transition at input B. So, for example, so now depending on the type of timing analysis whether it is the mass or the min which of the slew will get propagated that is the problem. So, it will have two delays it will have delays from A to z delay from B to z these delay values are separate, but the transition at z can be calculated using the transition of either A or transition of either B. Now, there is a variable in in prime time called timings to propagation mode it can be set to one of the two values. Now, let us say we are talking about the mass path analysis with this is already what is mass path analysis, mass path analysis is used for set a path set up a constraint checking it is usually done in the world it is most typical in worst case library when we consider worst case scenario or worst case operating condition. So, there can be two the variable can be controlled to select which transition number would be used to calculate the transition at z one is the worst slew other is the worst survival what it means is that now let us say this is ok this is A this is B. Now, let us say A has a B has a better slew that when compared to A. So, when we set this variable to worst slew propagation mode prime time will calculate the value of transition at z using the transition at A because A has a worst transition this is the most pessimistic mode and you should be using this almost all the why because in this case you are not worried about whether. So, now the second mode when I will talk about second mode and then we will know why this is pessimistic the second mode is worst survival what it tells us that what it tells prime time is that whatever arrives later use that transition this is a slightly more accurate analysis why because now let us say B arrives later. So, typically the critical path would be to B right because B is arriving later since the delay at B is more. So, the critical path the set a critical path would be to B and ideally it should use the transition at B, but when you use when you use this the variable and set it to worst slew propagation even if sorry even if B is arriving later it will use the transition at A. So, it will always always get a worst value in this case. So, in most of the cases we use this this will make the analysis a bit more pessimistic, but we are ok for min path for whole time in calculation it will use the best slew or best arrival. So, when we set the variable to slew propagation it will use worst slew for max path it will use best slew for the for the whole for setup it will use worst slew for hold it will use the best slew which is the most as more pessimistic analysis and it is more suitable it is good to have. So, every I think the default value is slew propagation. So, the value can be the slew propagation or arrival propagation when you use slew propagation for setup it will take the worst slew for hold it will take the best slew. So, this is please do not worry if you do not get more time talking about this is a slightly advanced technique this is a slightly advanced topic and once we go to lab I will show you what how does it affect. So, when it when you will see this thing happening in the lab you will understand it. The second problem about transition this we are these are all problems that come in delay calculation that is why we are discussing this these are all issues with delay calculation. So, other problem comes when there are different slew thresholds we have already seen what slew thresholds are slew thresholds are the limit values between which the prime time. So, calculate the prime time values they can be 20, 80, 10, 90, 30, 70 and so on. So, if you have cells so if you are sourcing standard cells from only one single algorithm all will have the same threshold. So, there is no but let us say u 1 is from one library u 2 is from other library u 3 is from some other library and they these might have different slew threshold values. In this case we do not have to worry a lot time time does a good job it will see what is the threshold value at each cell and it will calculate the it properly. For example, let us see let us take this example u 1 is characterized with 20, 80, u 2 has a 10, 90, u 3 has a 30, 70 and a slew the rate of 0.5 the rate simply means that multiplies that factor by the slew value the rate means that whatever slew value is calculated will multiply by 0.5. Now, let us say the slew at z is something this is the slew at z. So, slew at u 3 a and slew to slew at u 2 a are calculated how they are calculated first the wave form is plotted and after plotting the wave form what we prime time will do it for example, for u 2 for u 2 it will now take it 10, 90. For u 3 it will take the 30, 70 numbers, but it will multiply that value by 0.5 because the delay calculation is simple delay calculation is simply 50 percent here and 50 percent here this is the difference this is the delay, but the transition numbers get calculated based on what are the slew control. So, it is ok to have difference to threshold although it is not recommended delay calculation will become much more simpler and much more accurate is we use library. So, a particular library vendor will make sure that all his cells has same threshold number this is to make delay calculation simpler and more accurate right ok. Let us move ahead. So, this is a formula which tells what is the slew what is the relationship between 10, 90 slew and 28 slew. So, you can also do this also simple formula slew 20, 80 divide that 0.8 minus 0.2 is equal to slew 10, 90 divide that 0.9 minus 0.1. So, if you know the slew at 10, 90 you can calculate the slew at 20, 80 obviously the 20, 80 numbers will be less than the number because again the region between 20, 80 it is less than the region between 10, 80. So, how the combination part delay is we we did one example when we are calculating the clock latency in the last section. So, for example the prime time wants to calculate the fault delay. So, every node will have fault delay and write delay because not every node the cells the standard cells and net are not symmetrical in terms of rise and fall. So, each node in fact each node will have full value in fact it will have a rise value and a fall value and for each rise and fall value it will have a max value and a min value. We will see the how max and min comes into play. Let us please note that every node will have rise delay, fall delay for rise delay it will have a max value and a min value for fall delay it will have a max value and a min value. So, for example the fall value at this point at this node the final node will be fall here would mean rise at a fall at n 3 would mean rise at n 2 fall at n 1 rise at n 0. So, it will be t n 0 rise t a fall because z is falling t n 1 fall t b rise because now z will rise t n 2 rise plus t c fall again this is a very simple equation not much to worry about you can read about it. So, every node so to calculate the rise delay at any node time time will go back to the first input port or to the first sequential setting it can counter it. So, again remember it will break all the complete designing to different timing paths and then for each timing path it will calculate that this is how it calculated it. Part to flip flop again it is very similar to how the delay is calculated for combination there is no difference here the mechanism the algorithm they are all same the only thing for a flip flop the only extra thing is the calculation of t setup and t whole constraint t recovery t removal and so on. There are constraints and sequential there are no constraints in the combination cell so again it is same. So, the this slide what it does the two slide what they are stressing the fact that prime time will care about unitness that mean what is unitness an inverter is a negative unit that means a rise at n 0 will cause a fall at n 1 a rise here will call a fall here will cause a fall here a buffer is a positive unit a rise at the input of a buffer will cause a rise at the output of the buffer. So, prime time it will worry about the unitness it will calculate the delay according to the it needs to know the unitness that is why you see that if you go back to the standard cell library you see any timing table you see that it also includes a unitness. So, for example, a NOR gate is a negative unit and it is positive unit and so on right. So, you just have to see what is the relationship between input and output in terms of where input rises does output rise at fall and that defines the unitness of the path. Now, there are multiple paths in a complex design let us say let us consider a flop to flop path like this a flop to flop path like this might have multiple time path the path that takes the longest is called the worst made or a max path because that is critical for setup. For example, here this dotted path is the is a worst path it is a longest path longest path is used for setup calculation for setup check the min path the shortest path is used for whole time. Now in the last session the last slide had one exercise where you have to calculate you have to calculate the setup in a whole flap and in that I have mentioned two values the max value and the min value. So, this is why every node this is one reason why every node will have a max value and min value because there are multiple paths through number of cells right and any complex design will have any design you do you do any design you will find out that between two registers or input to register or register to output there might be multiple paths. So, not two paths they they can be 10 paths they can be 20 paths, but it sometime will calculate path delay to every node and it will note down the so it at as deep in it will note down what is the worst arrival for rise it will note down what is the worst arrival for fall it will note down what is the worst best arrival for rise what is the best arrival for fall this will become very very clear in the next slide. Just please note this is just the fact that there are multiple paths and what prime time value is about is the longest path in the process path although you can actually trace to any path, but the longest and the shortest will mean most for the set of critical path in the whole critical path. We have no we saw what is slack calculation this slide just again repeats that slack is the distance between required time and the time when a signal arise there is one example where so this is the one example where it this slides will calculate the slack here the period is 10 nanosecond here the data arise the data arise at 1 the setup. So, data the setup time here is 3 data required is 7. So, 7 minus 1 the slack is 6 this is how slack is calculated we will see a lot more this in the last right. So, that is all for this session. So, again the focus of this session is was to make you all familiar with the concept of interconnect the fact that interconnect they are different format for interconnect VSTF RSVF and STF is the most popular interconnect format the data contained in interconnect format is the only the RLC values of the internet it does not have any cell capacitance value that is important to know and then we know that when in case of NLDM prime time will model the network as a driver model plus the reduced interconnect network model and plus the receiver model the receiver will do model as a simple single capacitance or not not simple, but a single effective capacitance for C effective or C total which will be showed when you do a report time minus capacitance. And then we saw that for for transition calculation we will be ok. So, firstly saw that at every node prime time needs to calculate the delay plus the transition value we saw that what are the problems that can happen during function calculation one is the few more thing this is one one good thing to know. Second thing is they can be different solutions and then we saw that there are multiple path and for each path prime time will calculate the the worst path the longest path and the best path is the shortest path the worst path is used for setup check the best path is used for hold check right. This shows all about interconnects and delay calculation in next session we will see we will learn a lot more about clocks and etc. Thank you.