 Let us begin with today's talk. And today we want to do somewhat miscellaneous things as can be expected from a last lecture, but we will begin with very long. Very long is another hardware description language, very popular in the industry. It is very easy to use because it is think tax is very much like C. And since many people are familiar with programming in C or C like languages. Therefore, it is quite easy to pick up. Very long is also somewhat informal language. It does not insist on everything being declared, everything being defined and so on. And often if information is not given, it selects what it thinks must be reasonable and therein lies the problem because what may be reasonable to the language may not be what you think is reasonable. And sometimes therefore, it can be ambiguous, but otherwise it is a very easy language to use. And as a result much like by people who want to quickly describe hardware and get it working and get it simulated. At least to the time it works very well. And it has a few major conceptual differences from VHDL, which we discussed yesterday. And what we will do today is to concentrate more on things which are conceptually different rather than different in syntax. Syntax can be easily learned by anybody, but we will put much more attention on things which are conceptually different. So, it is syntax is similar to C. One major difference between the C syntax and very long syntax is that blocks are delimited in C by the curly brackets. And curly brackets have a different use in very long. So, the curly brackets essentially form groups of signals and the corresponding functions of these curly brackets are performed in very long by the keywords begin and end as it is done in VHDL. The other major difference that very long has from VHDL is that now you do not have this entity architecture separation. Both of these are combined into a hardware object called module. The module looks very much like a C function and in a C function inside brackets you have the parameters which are passed to it. In case of a module you have signals which are passed and the module then acts upon these signals in a way which is very similar to VHDL. Essentially, the treatment of signals is very similar in most VHDL languages. Very long actually has many more phases than we had described. The description that I had given was somewhat simplified and very long has many more phases of operation in every round of simulation. By phases I mean update of signal finding out whose sensitivity has been triggered and then resimulating that module. So, it is very similar here, but the ordering is more complex and it has many more stages. It actually has five stages, but for our understanding the picture that I have drawn in my simplified presentation in the first part of yesterday's lecture continues to apply for very long. Now, very long has a very confusing terminology which bothers most people when they come across it for the first time. The terminology applies to signals being of two types. So, signals can be of the type NETs or of the type registers. In short, NETs are things without memory and registers are things to which if you allot or if you apply a particular value to it, then later the register holds that value. That means it is capable of remembering that value. Now, as far as this is concerned the use of register is appropriate because after all we associate a register with a storage element. Unfortunately, in C a wire could actually be a register. It is assumed that as in CMOS technology, the capacitance associated with this register is sufficient to hold a value and therefore, very often simple signals indeed a very large majority of signals used in descriptions have to be declared as registers and not as wires. Now, NETs have various kinds of wires. You have simple wires and wires which are connected as or or wires which are connected as and circuits. If you recall during one of the question and answer sessions, I had talked about the use of open drain outputs. So, whenever you have lots of open drain outputs connecting together, then essentially it becomes an extended gate where the pull down is distributed over different hardware modules. The pull up is common and essentially what it means is that if anybody wants to pull down the wire to 0, the resultant is 0. It does not matter how many other units are trying to drive it to 1. So, therefore, 0 is dominant and that is called wired end because the 0 is dominant in end. So, if 0 is dominant anybody who drives 0 then over powers anybody else who may be trying to drive it to a 1 and since that is the property of an end gate that is very often called a wired end. If instead of a pull up you had a pull down then 1 would be dominant and such wires are called wired off. Registers are essentially signals which are which need not be continuously driven which can be driven which can be given a value once and as a function of their own property once this value is given to them then they keep this value. Since this concept is a bit different and more than a little confusing, I will discuss this concept in a bit of detail immediately. The view that verilog takes the view that verilog takes is the following. Let us say that there is a there is a node. So, this some node in a circuit now it holds the value. So, consider first a case of let us say CMOS gate driving this wire. So, if you have let us say a gate say some inverter driving this wire then in fact this wire is continuously driven. Let us see what the electrical impact of this statement is. This is our inverter and this is my output. Suppose the input is 0 the output will go to 1 that is equivalent to assigning a 1 to a signal to a signal in h d s. So, that is fine what happens afterwards is interesting. Suppose due to noise or whatever reason this output which is resting at 1 was to be pulled down a little bit what will happen well the input here is still 0 and if this voltage comes down a little bit then this transistor is on and this transistor is off and this lack of charge on the output will be made up by this transistor pouring current into it. As a result what we say is that this output is being kept at 1 continuously by its driver. So, therefore should there be some small departure from a voltage this guy is awake all the time and whenever that happens it will drive it up and make it up at the output. So, in this particular case the wire need not have any storage facility. So, to speak it just retains there and is secure in the knowledge that its driver will keep it at the value which has been assigned to it. So, the question that very law tries to answer is that you assign a new value to a signal that is fine, but what keeps it at that value makes the distinction between a net and a register. On the other hand let us take a different kind of a case and we have not done pass gates in this and I will come back to that in a minute because that is one of the miscellaneous things that I want to add to what we have done, but assume that you have a switch like this and you have a capacitance. Suppose this node is at 1 closing of this switch is equivalent to charging of this capacitor to a 1. So, that is equivalent to assigning a suppose this variable is some x then this is equivalent to saying that x equal to 1 closing of this switch is equivalent to a hardware description language is saying make x equal to 1. So, that is fair enough. However, let us say that this switch is closed only momentarily that means it is a delta function in time. So, it is a momentary closure of this switch if you close this switch only momentarily then this node is at 1. However, the drive has been removed the drive was there only when the assignment was made and after that there is no more drive on this node. Now, whose responsibility is it to keep this node at 1 that responsibility in fact, rests with this capacitance it is because of this capacitance that even though this switch is opened the capacitor holds that charge and this node remains at 1. Now, if you want to know what is the strength with which this node drives subsequent nodes then it depends on the value of this capacitor therefore, a large capacitor means that it is a large load on the previous stage, but that means it is a stronger driver for the next stage. The other part is that the holding of a value 1 is not because it is being continuously driven because this switch has in fact gone back to open. What is happening however is that you have placed a certain amount of charge on this capacitor and that charge stays and because that charge stays this node continues to remain at 1 this kind of a node is called a register. So, in short if the responsibility of keeping a node at its assigned value is with the driver then it is a wire if the responsibility of keeping this wire at its assigned value is it rests with the node itself in that case it must be a register. Notice that now if because of noise or something you take away some charge from this capacitor then there is nobody to replenish that charge. So, this is the property of a register a register need not in fact be a flip flop as we normally mean when we talk for example, the a register or b register in 8085. So, a register is not necessarily a storage element in the in the sense of being a d type flip flop or a d type latch. In fact it could be something to which an assigned value can be assigned for a brief a delta function in time this value is assigned or driven and the driving is then not continuous as opposed to the upper case. So, this is a case of a wire being continuously driven this is a case of a register. So, this is a case of a wire which is continuously driven and this is a case where the value is assigned, but not continuously driven it is assigned in one instant here and then this switch open and the responsibility of keeping it at one rest with the node and not with the driver. In such cases very log chooses to make a distinction between these two cases and such nodes are called registers whereas such nodes are called wire. So, this is a big difference from VHDL in VHDL a signal was a signal that is it the properties of the signal were then determined by the model that we associated with that, but here their signals themselves are of two different kinds the one without storage are called wires and then they must be continuously driven and the ones with storage are called registers and it is to assign a value to them at one instead of time and not continuously drive. Consequently there is the assignment of a value is the assignment of a value has two different kinds of syntax when you have a wire then you say assign x equal to 1 and this corresponds to a continuous driving of the node called x that means you have attached a driver to it which is driving it to 1. If you simply say x equal to 1 that means at the instant of time in the simulation time by the way the separation of program time and simulation time I had discussed yesterday. So, at the value which the time variable has at that time a 1 is assigned to this node x and now it is the responsibility of this node x to keep it. Now, this leads to a very important distinction which we must be very careful about. For example, if a node is continuously driven and you write assign x equal to 1 and then write assign x equal to 0 similarly you might have x equal to 1 here and you might have x equal to 0 later. In an ordinary computer program which hardware description languages resemble both of them would be the same this later assignment will override the previous assignment that is all the variable was given a value 1 now it is given the value 0 and from now onwards it holds the value 0, but here the syntax is makes that the physical meaning of these two are quite different. This will lead to disaster this will lead to disaster because I have two separate drivers now continuously driving this wire and trying to drive it to different values. So, therefore, two such statements essentially mean that you have notice this is not an inverter a buffer. So, you put a driver here and you have shorted their outputs. This statement essentially creates a circuit with a driver and this driver has the responsibility of driving it to 1. This circuit creates an independent and different driver which is now trying to drive it to 0 as a result there is a clash at this node. So, therefore, multiple assignments are to be used very carefully indeed only when you think that it is to have multiple drivers on a wire and normally this would be flagged as an error. On the other hand this is fine what you are saying is that at the time instant this occurred you placed a 1 on the capacitor that means you charged it up and at some other time you discharge that capacitor. So, that is fine it is for this reason that whenever you have essentially a process then inside that process where sequential statements are occurring you should use statements of this kind and these statements imply that the node is driven at an instant of time and left to hold the value on its own. Therefore, inside processes and I will describe them in a while what are processes and so on, but inside processes you use registers and outside processes you use wires and because these are wires you must use you must continuously drive them. Therefore, you must use the key word assign whatever value and the way it is interpreted by the hardware description language then is that you take this node x and for every assignment statement on x you actually add a new driver. So, this distinction is very important unfortunately it is not well emphasized in text books and as a result if you are in a hurry without understanding the basics and jump to the syntax of very long immediately then you are sure to be confused sometime when unexpected things happen in this language. So, now let us look at what I was talking about what are processes. We will often refer to what we had done in VHDL simply because it is a more formal language which specifically defines various things and we will see what is the equivalent in very long. Now, in VHDL we had talked of two kinds of statements we had talked of concurrent statements and sequential. Sequential statements essentially were used whenever a hardware block could not be described in a single line. So, for example, the behavior of a D flip flop cannot be described in a single assignment. So, therefore, to describe the behavior of the D flip flop we will use a concurrent block, but inside that concurrent block will be programmed like logic statements and they will be sequential. In very long there are. So, sequential statements are inside a block which is delimited by a begin and end and the block is often called a process. It is delimited by a begin and an end. By the way, notice that in VHDL is case insensitive whereas, very long like C is case sensitive and what it means is that you cannot use these two in the same syntax whereas, here the two are taken to be the same and you can use uppercase or lower case letters whenever you want. Now, the corresponding action in very long is carried out by two separate kinds of constructs. There is a process equivalent process to this called initial. It has this special name called initial and then there is a special process called always. So, all sequential statements which were inside a construct called process in VHDL now must be inside either of these two kinds of constructs. You have an initial kind of construct and an always kind of construct. The initial block is performed only once and obviously, therefore, all initialization statements will go in this. It is performed at the start of your description and this is normally not considered synthesizable. That means, this is not describing your hardware, this is telling you what the hardware starts with. Very often inputs are therefore, put inside an initial block. So, even though the actual inputs will take place in the future, they are not part of the description of the circuit and they are put inside the initial block. The always block is like a concurrent statement. It describes hardware and it has a sensitivity. We had talked about sensitivity in the example which we had discussed in some detail yesterday. We had seen for example, that the signals a and b inverter as well as the NAND were sensitive to a whereas, only the NAND was sensitive to b. So, that constitutes a sensitivity. So, the sensitivity list comes at always. For example, you can say always positive edge, positive edge of a signal called clock and then begin and end. So, everything which is inside here is supposed to happen only when you detect a positive edge in the clock. So, that is the sensitivity of this hardware that whatever statements that you have put here, they will be executed only when this event occurs, when clock has a positive edge. So, notice that the time variable has some value when this sensitivity is struck and this entire thing will be executed at that time in zero time. That is because different instructions are not different assignments. It is actually one single logic. It is the replacement for one single concurrent statement which cannot be described physically in one line of the program or description. Therefore, you are using multiple lines, but it is considered as the description of one hardware block. So, in that case, the basic unit of hardware in very long is a module. The syntax of a module is very similar to a function called in C. Now, this module can be invoked by instantiating it. Notice that in VHDL 87, we could not have instantiated an entity directly. We had to declare a component type and then the component was instantiated in structural description. In very long, you do not have to go through all this process. You just can once you have defined the module, then the module can be instantiated immediately. Let us now start looking at various items that very long operates upon. The basic things, of course, are signals. However, these are the actual signals in your hardware. However, to control these signals, sometimes you will require things which will not occur on the circuit itself, but which are required in order to describe the circuit. I will give you an example. Suppose you have a bus. Let us say that we have an 8 bit bus. Now, this is wire 0, 1, 2, 3, 4, 5, 6, 7. These 8 wires together constitute a bus. Now, we do need to index these by something. So, for example, when I refer to this wire, suppose this bus is called B, then I must refer to B 4. Now, B is a signal, obviously. B 4 refers to the status of logic on this wire. Therefore, it must follow all the rules that we have derived for signals. That means, a direct assignment cannot be made. It must be scheduled. This can be sensitive to the value on this wire. When something changes on this, an event has occurred and we must go around waking up whose ever is sensitive to this change. So, these are the properties of signals and B 4 by itself is a signal and will indeed be, will conform to this kind of behavior. But what about 4 here? 4 is not a signal. If I change 4 to 5, that should not take finite amounts of time. There is, if I am referring to B 4 and then I want to refer to B 5, changing the value of the index from 4 to 5 is just changing the index, not the signal. Therefore, I now need things in my description, which are not signals. However, which are similar to signals in the sense that they can acquire values. Such things are called variables. By the way, this is common to verilog and VHDL. In both languages, obviously, you require signal as well as variables. Remember, variables are helpful quantities, which are used to make the description possible. They are not actual signals, which you can go and measure with an oscilloscope. So, if this was the signal, this was the bus and if I placed the oscilloscope, if I place the oscilloscope at this point, then I will see the waveform, which is supposed to be on B 4. But I cannot see 4 on an oscilloscope. 4 is just the index, it is just the name and suppose I now have a variable called B I and I takes the values 3, 4, 5 or 8. In that case, assigning a value to I should not be subject to the same rules as assigning a value to the signal. I am just choosing a different index, not a different value of the signal. Therefore, these must be handled quite differently from signals and such things are called variables. Another example is for example, the counter in a loop. Suppose I have a loop like a for loop, then the counter of that loop essentially just tells you what is repetitively being done. The counter does not represent a signal on that circuit. So, for example, to set all these wires to 0, I might have a loop, which will say for I equal to 0 to 7, make B I equal to 0. Now, notice that this assignment is a signal assignment. I am placing a signal value in the real circuit, but when I say I equal to 0, that is not a signal assignment. That is only to identify what I mean. It does not have any implication to the circuit performance. So, such things are then called variables and these are signals. Now, in VHDL, certain kinds of signals are predefined. Yesterday in the short lecture, we used the kind of variables called bit and bit could have variables, could have values, which are 0 and 1. VHDL is a very formal language. For example, it makes a distinction between a bit type of variable or signal and a Boolean kind of variable or signal. A Boolean quantity can acquire the values false and true, not 0 and 1. And if you declare something to be a Boolean, if you try to assign a 0 to it, there will be an error. This is the level of strictness in VHDL. Very long is much more forgiving. It assumes that 0 is false, 1 is true. It assumes that a combination of bits when written, the most significant bit will be to the left, the least significant bit will be to the right. Indeed, it allows you to do dangerous things like assigning an array of different size to an array of a different size. And then it goes ahead and makes what it thinks is a reasonable assumption. So, then, if you had better understand what the language thinks is reasonable, otherwise you might be surprised. In case of very long, by the way, very often for digital signals in VHDL, we use a library which defines a type of signal called STD logic. And STD logic is a nine valued system. So, as always, VHDL is large and complex. Very long wants to be small and useful. So, therefore, very long has four valued logic system. And these values are 0, 1, x and z. The value 0 and 1 are quite familiar. We do not need to explain. Value x means unknown or illegal. Either the value has not been initialized, it has not been assigned anything. And therefore, we do not know whether it is a 0 or 1 or it could be that it is a signal in which both a 0 and 1 is continuously being assigned to it. In that case, you do not know what its output should be and it will go to x. This value is a tri-stated value or high impedance value and allows you to model gates which can be tri-stated. These are the only four values which can occur for an ordinary very long signal. In VHDL, bit is predefined for any multi valued logic. You have to define your own type. It gives you the freedom of defining a type. And by defining a type, you can have a four valued logic if you wish. The standard type which is provided in the IEEE library is in fact nine values. It makes a distinction between uninitialized and x and it has strong signals as well as weak signals. So, as a result, it is a very rich value set and you can have nine valued variables. Whereas, the standard variable in very long is four valued and signals acquire the value 0, 1, x or z. Very long also has predefined gates. In the language itself, the language itself understands gates. So, for example, it has n gates or gates, not gates and it has xor. All these gates are known to the language. That means, they are language elements. The model is internal to the language. This is very different from VHDL. In VHDL, as you recall yesterday, when we defined the four NAND xor, we had to first define the NAND only then we could define the xor in terms of that NAND. So, commonly available logic is in fact quite is inside the language itself and you can instantiate these by just invoking their NAND. So, for example, you could place an AND gate by giving an instance name, the gate type and then the signals which are connected to them. Now, for all the standard gates in very long, we have a special convention for the order in which these signals are to be placed. By convention, the output is placed first. This is not very intuitive. For example, when we defined the D flip-flop yesterday, we first declared the inputs and then the output. So, when you describe a D flip-flop, the mention of D and clock comes first and Q and Q bar comes later. However, very long chooses to do it in the opposite order and the reason for that is the following. It takes after C and C allows you functions with a variable number of arguments. Similarly, this AND is not a two input AND all the time. It could be an AND of any number of inputs and because there is one unique output and all the rest, the variable number is in input, not in the output. So, therefore, it allows you to give a comma separated list and the first of these is the output and the rest are input. So, for example, this will describe a four input AND, where X is the output and Y, Z, P and Q are in fact inputs. Because these standard gates have this convention, therefore, when people describe their own hardware, they follow the same convention. This is not required by the language. This is the matter of convention. However, it is a good convention to follow because then the modules that you describe will have the same convention as the built-in modules of the language. So, therefore, in very long, we always put the outputs first. The other thing is the following. Whatever is being assigned to inside a hardware module should be a register. However, what comes from output outside could be a wire. So, therefore, there is an automatic conversion from wire to register when an external signal is connected through a port to inside. So, we should be very careful about the distinction. Remember, inside this module, we do not know whether what the property, you may be assigning under various conditions different values to a variable inside this. However, if an input is given to you externally, then you cannot assume that this guy has enough capacitance to multiply assign variables here and so on. Therefore, the convention that you have wires here and registers here and again output will become wire. So, these outputs will then be converted back to wire and then you drive these continuously. So, a typical module will then look like this. You come with the keyword module, you give it a name, you give it a list of signals which form its ports. So, notice that the work of entity is being done by this. So, then you have the outputs could be one or many followed by inputs. This is by convention not by a requirement of the language, but as I said before, it is a good practice to follow this convention. Then you have declarations which will declare the properties of these, whether they are input, whether they are output, whether they are wires or whatever else, wired or whatever. That comes as a declaration module and just like modern versions of C, you can put that declaration right here. Then you have begin and end and the module description remains inside here. This module can then consist of any number of concurrent statements of blocks. So, assigned statements are concurrent initial and always are also concurrent. Initial is sensitive to t equal to 0 and not to a signal. So, these are all concurrent blocks and they constitute the various things here. However, both initial and always could consist of procedural assignments and other statements. So, these will be procedural statements which are in fact sequential. So, these statements apart from procedural assignment which is just the equal to sign without the keyword assign, you also have very C like statements like if, case for, while, etcetera, etcetera. These work exactly the same way as they do in C. So, you can in fact describe the logic of the functioning of at least the behavior by using this. Apart from assign initial and always, you have module instantiation and an example of that was here. This constitutes a module and now this module could be the entire circuit. It could be the test bench or it could be a component of a circuit. I think we just have time enough now to do one more thing about very long which can be quite confusing if you are not aware. Very long has two kinds of assignments, two kinds of procedural assignments and they are called blocking and non-blocking. Remember we had discussed yesterday that in hardware description languages, when you assign a value, you do not immediately assign the value to the variable, you schedule it. That being the case, then the next instruction occurs before the previous variable has acquired its value. This can sometimes lead to very severe misunderstanding. Let us see what would happen. In this case, I am taking a BHDL example here. Let us see what happens in this case. Suppose you say x equal to 0 and assignment uses this symbol in BHDL and now you say if x equal to 0 do something. It appears that we have assigned 0 to x and therefore, this statement must be followed. The if is true. In fact, it is not true. When we say assign 0 to x, we are saying schedule the value 0 for x from the next round onwards. We have not automatically assigned 0 to x. Therefore, currently the value of x could be 0 or 1 or anything else. This assignment has not actually occurred at this time. It has been scheduled to occur. If there is a delay specified here with the after clause, then in a measurable future time, otherwise in the next delta time, but in any case in the current delta, this value has not been assigned. However, it could be that the initial value of x itself was 0. In that case, this statement will be true. But on the other hand, if it is not, then this if will not be followed. If you are not aware of this, then you may look at your code a hundred time and you will never find where the bug is. So, remember this assignment does not ensure that the next statement will see a value 0 to x. In very long, when you have blocking assignments which uses this symbol, then it is assumed that the time will be given for the left hand side to assign the value of the right hand side. Time will advance and only then the next assignment will be done. So, a blocking assignment essentially blocks the next statement from occurring unless the left hand side has already acquired the value given by the right hand side. Such statements are called blocking assignments. The very long also has non-blocking assignments which use the same symbol as VHDL and has the same impact as VHDL. In this particular case, in case of very long, these things are assigned only in the future. When the statement is executed, you compute the right hand side at the current time, but assign it to the left hand side in the future, in the next delta or if you have specified a delay after that much delay. And you immediately at the same time go to the next statement. What this means is that the next statement is not blocked from occurring by this assignment and therefore, these statements are called non-blocking. So, you may well ask why does VHDL do such a silly thing as this, because this can lead to confusion. I look at my code and I cannot figure out whether this will be executed or not. And the answer is that this is the more accurate representation of what really happens in a hardware. When you create conditions so that the output of an AND gate is 0, the output of the AND gate does not become 0 immediately. There is a certain delay only then will the output of the AND gate go to 0, not immediately when the inputs are 0. The inputs are equivalent to the right hand side in an expression. The output is equivalent to the left hand side. So, you are saying that x equal to AND of A and B. If A becomes 0, x should not become 0 immediately. To reflect a proper picture of hardware, we have non-blocking statements as the default in VHDL. If you want to make it blocking, then you have to give an explicit statement like weight 0. That means do not advance the time, but do not advance the time, but let the signal acquire the value and only then follow the logic afterwards. On the other hand in very long, the default assignment is the blocking time. Now, that means that the default assignment does not reflect what actually happens in hardware. Sometimes this can lead to difficulty and very often when it leads to difficulty, there are some special cases. So, this is done by a word of mouth kind of thing and I will give you some words of mouth for it as to when this should be used and then you use the non-blocking. Most of the time you can get away with this and therefore, very long uses this as the default, the more dangerous thing as the default. This is in fact, the less dangerous thing. Let me just illustrate one example and then after that we will call it a day as far as very long is concerned and we will have a longer question answer session today. However, this is very important and let me therefore, illustrate what happens. Consider a shift register. This is D, this is Q 1, this is Q 2, this is Q 3. Now, when the clock arrives, what happens? Well, Q 1 becomes D, Q 2 becomes Q 1 and Q 3 becomes Q 4 and Q 3 becomes Q 4. So, Q 2. Now, suppose we do it in the natural very long way. Let us say that the initial state is some D is 0, Q 1 is 1, Q 2 is 0, Q 3 is 1. Let us carry it out in the very long way. At this statement what will happen? Q 1 will be assigned the value of 0 and only when the assignment is complete, will you proceed to the next one because it is a blocking assignment. Therefore, when you say Q 2 equal to Q 1, Q 2 will be assigned 0 and only when this assignment is complete, will you proceed to the next statement and the next statement will say Q 3 equal to Q 2, which is 0 and therefore, Q 3 will become 0. Therefore, an unexpected thing has happened. The shift register has become a short. Indeed, these equations say that Q 1 equal to D Q 2, Q 2 equal to Q 1, Q 3 equal to Q 2. This is in fact, the description of a short. Then, how do I describe the shift register? The answer is that I must use non-blocking statement and this is what VHDL would have naturally done. Now, what happens is, remember these are the initial values. First statement says assign. Now, we are using non-blocking statements. So, what it says is schedule the value 0 for Q 1. D is 0. So, you say schedule the value 0 for Q 1 in the future, but Q 1 retains its value. So, you schedule 0 to be assigned to Q 1 in the future, but the current value of Q 1 remains whatever it is namely 1. Therefore, when you come to this statement, you say schedule the value 1 for Q 2. So, you have scheduled, this is the scheduled for Q 1, Q 2 and when you come to this statement, you say schedule the current value of Q 2, which is the old value of Q 2. You say schedule this value for Q 3 and that means Q 3 is scheduled to become 0. Then, only in the next delta, these values are assigned and we have the proper value 0, 1, 0, which is the proper shifted value that we expect. So, therefore, if you are not careful in very long by using blocking assignments by default, you might end up with a problem and end up describing something which looks reasonable here. You may describing something which looks reasonable here, but indeed it will result in disaster here, everything will become 0. So, therefore, there is essentially a tip which is passed on in the language that if you want to properly use it, then if logic is intended, then use blocking. If storage is intended, use non-blocking. So, now the user has to be aware, the language does not do the correct thing. The user has to be aware and use the correct construct, otherwise you may get the wrong kind of behavior. This is the kind of looseness, which is the price that we pay for the convenience of a very simple syntax and simple usage and this is what I meant by the difference between the two languages when a question was raised in comparing VHDL and very long. So, in short we just wind it up here about very long, we have to take questions from various centers, but in summing up I will say very long is very convenient to use, it is very C like. If you know C, you can start describing hardware within a day by learning the very long syntax, but on the other hand it makes all kinds of sweeping assumptions, which makes life simpler for you, but on the other hand sometimes it may land you in mess. So, VHDL on the other hand is a very formal language, lots of statements have to be used, everything has to be declared and you have to be aware of the hardware process all the time while writing the description. It takes, it is painful, but on the other hand it is safe. So, that is the choice between VHDL and very long. Obviously, both these languages require a full course to understand fully and excellent text books are available for that, I cannot do justice to this in just a lecture each. However, I hope that this introduction has been enough for you to understand the underlying concept which go below hardware description languages in general and VHDL and very long in particular. So, we will stop this lecture here.