 In this example, we're going to be looking at how forwarding affects this block of code. We already saw what dependencies exist in this code, so we're just going to be looking at the forwarding here. We're going to be looking for data hazards and seeing how the forwarding will help us overcome those. So our first instruction is still not dependent on any others that we've got here. So I can run my add immediate instruction immediately. Our store word instruction is dependent on the add immediate instruction. Now I can forward the results of the add immediate operation directly to the store word. So the store word instruction isn't going to have to wait to get those results to use them. So I can run my store word instruction immediately. And since those results were available for the first store word, they'll also be available for the second store word instruction. Our add instruction doesn't depend on any others, so we can run that one immediately. Now we've got a subtract instruction. This one does depend on the results of the previous instruction, but I can forward those from the add instruction to the subtract instruction right after the ALU stage. So they're really just going from the ALU stage back to the ALU stage, and they're ready to go. So I can run the subtract instruction immediately as well. I have this load word instruction, which is dependent on this very first add immediate instruction. Now it's been more than two cycles, so this data is already available to me. I can just pull it out of a register and come. So there is no data hazard there. Likewise with the second load word instruction, it's been more than two cycles since the add immediate ran, so those results have been committed back to a register. Next I have the add immediate instruction, which is also dependent on the first add immediate instruction. Again, it's been more than two cycles, so the stack pointer is already available to me. Lastly, we have our jump register instruction. This is dependent on the results of the load word instruction before it, but the load word instruction isn't going to be able to read the return address until the fourth stage. Our jump register instruction would like to use that data in the second stage, so I need to wait at least two cycles in this case for that data to be available for my jump register instruction. I'm filling one of those stages with the add immediate, so I'll have one no op instruction, and then I can run my jump register instruction. So in this case, I only have one no op instruction. That's because my jump register instruction really wants to use the return address very early in the pipeline. But if I had something here like an add immediate, then I wouldn't have to have a no op here. That data would have been available in the third stage for me, so it would already be ready in this cycle. But since I want to be able to access that data earlier in my pipeline, I have to wait an extra cycle to put the jump register instruction into my pipeline.