 Hello, and welcome to this presentation of the Embedded Flash Memory, which is included in all products of the STM32G0 microcontroller family. The STM32G0's flash memory interface supports new features with regard to the STM32F0 as indicated in this table. The cache and prefetch buffer decrease latency and consumption. The one-time programming area, or OTP area, is used to store non-erasable data. Fast programming programs a row of 256 bytes instead of discrete 8-byte double words. PCROP stands for proprietary code readout protection, which protects the code by only allowing the execution from flash memory, but not reading or writing. Securable memory cannot be called from non-secure areas. It's typically used to perform a secure boot with image authentication. Error correction and checking, or ECC, improves the reliability by detecting and eventually correcting bit flips that may have occurred in the flash memory. It is handled transparently by the flash memory controller. The STM32G0 embeds up to 128 kV of single bank flash memory. The flash memory interface manages all memory access IDS, read, programming, and erasing, as well as memory protection, security, and option bytes. Applications using this flash memory interface benefit from its high performance, together with low power access. It has a small erase granularity and short programming time. It provides various security and protection mechanisms for code and data, read and write access. The main flash memory is split into two K-byte pages that can be independently erased. A mass erase feature is also supported. Flash memory access may require wait states according to the actual CPU frequency. To reduce the latency, the flash controller embeds both an 8-byte prefetch buffer and 16-byte instruction cache. It also contributes to decrease the consumption because they belong to the V-core power domain. An 8-bit ECC code is appended to the double word to program. It is checked on read to detect and correct single bit errors and detect double bit errors. In case of an uncorrectable error, the flash memory controller asserts the non-maskable interrupt or NMI to the Cortex M0+. In addition to the 128 K-bytes of the main flash memory, the STM32G0 supports a system memory of 28 K-bytes containing the ST bootloader, an OTP memory that can be used to store user data that cannot be erased. Options bytes containing default settings to configure IPs in the system on-chip. They're automatically loaded after a power-up reset. The first table details the memory organization based on a main flash memory area and an information block. The second table details the granularity of the flash memory operations. Programming is done on 8-byte double words. Fast programming is done on a row of 256 bytes. Erase is done either globally, mass arrays, or on 2 K-byte pages. The secureable memory is aligned on pages. Write protection is done per page. Read protection is global. Proprietary code readout protection is done on 512-byte areas. Eraser in flash memory words are 72-bits wide, 8-bits are added per each double word. A double word is 64-bits. The ECC mechanism supports one error detection and correction, two errors detection. When one error is detected and corrected, the ECC correction flag is set in the Flash ECC register named Flash ECCR. An interrupt can be generated. When two errors are detected, the ECC detection flag is set in the Flash ECC register named Flash ECCR. In this case, an NMI is generated. Fast programming enables the programming of a row of 256 bytes, while normal programming has a granularity of 8 bytes. The main purpose of fast programming is to reduce the page programming time. It's achieved by eliminating the need for verifying the flash memory locations before they're programmed, thus saving the time of high voltage ramping and falling for each double word. Fast programming is 37% faster than standard mode programming. Mass erase time, meaning a 128k byte erase operation, approximately takes the same time as a page erase. Fast programming vs standard programming. 256 consecutive bytes are programmed instead of 8-byte double words, located anywhere in the main flash memory. 8-byte programming is more reliable due to the verification step. Note that the maximum time between two consecutive double words is around 20 microseconds. If a second double word arrives after this delay, fast programming is aborted and a flag is set. Consequently, interrupts should be disabled to make sure that this delay is not exceeded. This table summarizes the differences between standard and fast programming. Each program and erase operation can degrade the flash memory cell. After an accumulation of program and erase cycles, memory cells can become non-functional, causing memory errors. Endurance is the maximum number of erasing and programming sequences that the flash memory can support without affecting its reliability. Data retention is defined as retaining a given data pattern for a given amount of time. The retention depends on the number of program and erase cycles and also on the temperature. The flash memory has a fixed access time while the AHB bus frequency can be dynamically changed. That's why the number of wait states is programmable and has to be set according to the actual AHB frequency, called H-Clock. Running beyond 64 MHz also requires to set the voltage scale to range 1. Please refer to the power controller presentation for more information. Software is in charge of adjusting the number of wait states according to the H-Clock frequency. Increasing the number of wait states must be done prior to increasing the frequency. Decreasing the number of wait states must be done after having decreased the frequency. When the number of wait states is non-null, the flash memory accelerator should be activated to limit the performance impact. CPU generates 32-bit instruction fetch requests. The 8-byte line containing the requested instruction is read from flash memory and stored into the current buffer, while the requested word is directly transferred to the CPU. The next line is automatically read from flash memory and stored into the prefetch buffer. So, in case of sequential code, back-to-back words will be delivered over the SAHB until a branch is encountered. When the code is not sequential due to a branch, the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case, the penalty in terms of number of cycles is at least equal to the number of wait states. Small loops can be entirely stored in the current and prefetch buffer. No flash memory access is needed. The flash memory controller also implements an instruction cache of 16 bytes. Each time the requested instruction is not in the current and prefetched buffers, the line is copied into the instruction cache. If an instruction contained in the instruction cache memory is requested by the CPU, it's provided without inserting any delay. Once all the instruction cache memory lines are filled, the LRU policy is used to determine the line to replace in the instruction memory cache. This feature is particularly useful in case of code containing loops. Instructions at the branch target address will be present in the instruction cache. Both the prefetched buffer and instruction cache are enabled or disabled by software because their impact on performance depends on the number of wait states to access the flash memory. The instruction cache can also be reset by software. The performance continues to increase linearly with the frequency when accelerators are enabled. Here the accelerators are prefetched buffer and instruction cache. The slope of the curve related to prefetch on and cache on is almost not affected by the transitions from zero to one wait states achieved at 24 MHz and from one to two wait states achieved at 48 MHz. From zero to 24 MHz, enabling the prefetched buffer and the instruction cache does not improve the performance. This array also shows that enabling the prefetched buffer and the instruction cache contributes to reducing consumption due to flash memory accesses. The consumption is only four microamps per MHz larger when running in power scale range one at a frequency of 64 MHz. The reason is that prefetched buffer and instruction cache are located in the V-core domain. When they provide the requested instruction, no flash memory access is needed, which saves energy. Readout protection aims to protect the contents of the flash memory, option bytes, internal SRAM and backup registers against reads requested by debuggers or software reads caused by programs executed after a boot from SRAM or bootloader. Only a boot from flash memory is permitted to read the contents of these memories. The proprietary code protection is a way to mark parts of the flash memory as execute only. Note that this kind of access permissions is not supported by the memory protection unit present in the Cortex M0 Plus. The user can declare two PC-ROP areas aligned on 512-byte addresses. PC-ROP areas are useful when only a part of the flash memory has to be protected against third-party reads. Write protection prevents part of the flash memory from being erased and reprogrammed. The main purpose of the secureable memory area is to protect a specific part of flash memory against undesired access. This allows implementing software security services such as secure key storage or secure boot in charge of image authentication. Once the processor has exited the secureable memory, this part of the flash memory is no longer accessible. The secureable area can only be unsecured by a reset of the device. The size of the secureable memory area is aligned on 2K-byte pages. In addition, the code executed from the secureable memory can temporarily disable debug accesses. Option bytes are used to early configure the system on chip before starting the Cortex M0 Plus. They represent 128 bytes. They're automatically loaded after a power reset or on request by setting the OVL launch bit in the flash CR register. This capability is required to apply a new setting without resetting the device. This slide and the two next ones describe the various fields of the option bytes. Bit28 configures the NRST pin, either as a GPIO, as a reset input only, or as a reset input and output. When it's a reset input and output, Bit29 configures the output stage, either a pulse generator or a low level driver which drives the pin low until it's seen as low level. This is useful when the reset line has an important capacitive load. The readout protection level enables the readout protection for the entire flash memory. Level 0, no protection. Level 1, read protection. Level 2, no debug. The following transitions are supported. Level 0 to level 1. Level 1 to level 0, which implies a partial or mass arrays. Level 0 to level 2 and level 1 to level 2. PC Rop A start and PC Rop A end define the proprietary code readout protection address range A aligned on 512 bytes. PC Rop B start and PC Rop B end define the proprietary code readout protection address range B aligned on 512 bytes. PC Rop RDP allows to select if the PC Rop area is erased or not when the RDP protection is changed from level 1 to level 0. SackSize defines the size of the secureable memory. BootLock allows forcing the system to boot from the main flash memory regardless the other boot options. The boot memory is selected from both option bytes and also from the boot zero pin. This table indicates in which memory the processor will boot according to the combination of parameters. Note that when end boot cell bit is set to 1, the boot zero pin is ignored. Only option bytes selects the boot memory. When the boot lock bit is set in option bytes, only boot from flash memory is supported. During the option bytes loading phase, after loading all options, the flash memory interface checks whether the first location of the main memory is programmed. The result of this check in conjunction with the boot zero and boot one information is used to determine where the system has to boot from. It prevents the system to boot from main flash memory area when no user code has been programmed. The flash memory controller supports many interrupt sources listed in this slide and the next one. An interrupt can be asserted upon successful end of operation. An interrupt can also be asserted when an error occurs during a program or erase operation. Protection violations can also cause interrupts. A size error occurs when the data to be programmed is not word aligned. Programming sequential error occurs when a program operation is attempted without having previously erased the location in flash memory. A programming alignment error occurs when a complete double word is not provided before initiating a standard program operation or when a complete row is not written before initiating a fast programming operation. A data miss programming error occurs when data are not written in time during a fast programming sequence. When a single bit ECC error is detected and fixed, an interrupt can be asserted. When a double bit ECC error is detected, the NMI is inserted. The flash memory module can be clock gated when the processor does not need to access the flash memory and also in low power modes. The flash memory module can also be power gated in sleep, run and stop modes. The flash memory module supports the following low power capabilities. Clock gating, flash memory power down mode, power gating of the entire module flash memory and controller. In run and sleep modes, only clock gating is supported. In low power run and low power sleep modes, the flash memory can enter power down mode while the clock of the controller is gated. In stop 0 and stop 1, the clocks are gated and flash memory can enter power down mode. In shutdown mode, the power of the flash memory module is gated for both the flash memory and controller. The flash memory module has relationships with the following other modules, system configuration controller, reset and clock controller, power controller, interrupts and system protections. For more details, please refer to application note AN2606 about the STM32 microcontroller system memory boot mode.