 assistant professor, department of electronic voice institute, Sallapur. In this video, we are going to just look for the characteristics of a JFET. At the end of this video, we are expecting this kind of outcomes that we are able to describe what is the JFET characteristics. In this video, we are going to mainly focus on the drain characteristics of the JFET. Friend, this is a circuit we consider to plot the drain characteristics of the JFET here. So, this is normally called as a common source connection there. And we use this kind of configuration to plot the VIA characteristics between, that is the between drain current and the voltage from drain to source, which is called as a drain characteristics. Friend, if you see correctly here, the source is more common and the gate is now applied with the reverse voltage. Friend, this is the JFET I use is of n-type or n-channel JFET I can say. And so that I am just going to make the gate reverse biased as compared with the source here. So, in this n-channel, the gate is made of p-type material. So, I am supplying batteries negative terminal so that that will confirm that the gate is reverse biased here. Now friend, these are some basic arrangements we are going to follow. So, before I go for this circuit arrangement here, the VIA characteristics is a graph between the drain current and the voltage from drain to source. And we take this current versus voltage variations for different conditions of the voltage between gate to source, different values of gate to source voltage that is called as the voltage VDS there. Friend, this one more set of these characteristics is coming here, which is called as the transfer characteristics here. This is a graph between the output current that is current ID and the voltage from gate to source here. And in this case, I am going to keep the voltage from drain to source constant here. So, friend, today in this video, we are just going to focus more on these drain characteristics. So, friend, here again just shortly I am just showing this small fade symbol here and different voltages we are getting across different terminals there. So, friend, if you see in this graph, this graph shows me the VIA characteristics between the current which is flowing in the drain, which is normally called the output current here and the voltage from drain to source here. Now, it has got different regions are shown here. So, friend, how we are going to plot this curve here is very simple. Actually, we are now going to put this voltage VGS to some voltage level and that is kept constant here. If you suppose see in this given set of graphs, the VGS is now varied from this 0, then that is now made reverse bias here is minus 1, then minus 2 volts, minus 3 and minus 4. So, I will keep this voltage constant here and then we are going to vary the voltage from drain to source. It is drain, this is a source and I am just going to measure the current flowing in the drain here. So, friend, this is a practical arrangement we are going to follow in this kind of measurement here. Now, friend, in this case, the graph is shown has got this kind of changes here. We are going to see some hash portions here. So, the region from this 0 to this voltage called the VP here or shorty called the voltage VP. It is normally called this ovumic region. Then the region from this VP onwards and the region is showing me a flat portion of a graph which is named as a region of saturation there and after some reason you find that the graph is now increasing quite sharply here like this. So, friend, in this graph, the axis shows me the current ID and this x axis shows me the voltage from drain to source. So, friend, we are just going to put some more focus on this statistics which is more interesting. Now, just I will just take a single graph intercont here. So, friend, in this case, I am just having a graph in which I am just keeping this voltage which is at a 0 and which is kept constant here. You see that in the beginning portion as I increase the voltage from 0 up to voltage VP you see that the graph is increasing linearly. As we increase the voltage, the current also gets increased here. But above this voltage VP, you see that the current will not change at all here. That remains constant here. And again, above some voltage VDS, you see that the graph is increasing quite sharply here. So, friend, these are different regions we are having in this graph. So, the region from this origin to this A point is normally called this ohmic region. Friend, in this region we find that the output current ID is increasing linearly as we increase the voltage from drain to source. So, the structure is simply acting like resistance here which follows Ohm's Law here. That is why it is normally called as ohmic region there. Friend, just go for one more region from this A to B. Okay, it is A to B we can say. This is a curved portion I can say. In this region friend, it is seen that suppose if I increase the voltage from drain to source, it is seen that there will not be much change here in the current ID. The change in the current ID is rather sluggish in this region here. And after this end of this region here, from this point B onwards here, the current is remaining constant here. Okay, so this is a behavior we are seeing from the device when I change the voltage from drain to source here. And friend, when I get this current at a constant level here, it is normally called as a constant current which is flowing in a drain which is also called as a steady state drain current here. We should denote this simply by this IDSS. Then friend, we wait one more thing which is called a pinch-off region here. So friend, pinch-off region is also called the region of saturation here in which the graph is remaining quite constant here. The current ID is not changing at all here. It is a flat portion. Okay, so friend, this is a portion in which the device is acting in a saturation and this region has got some sort of significance in the applications. So the region in which the drain current remain constant is normally called the pinch-off region there. This friend, in this case, in the pinch-off region, the channel width which is coming for the flow of conduction of drain current here is having the minimum width here. And that's why the device is supplying me some constant current here. And friend, we get one more region which is unwanted which is not good for the reverse here. That above some voltage here, it is seen that suppose if I increase the voltage above this Vmax value here, it is seen that the drain current increase drastically. Now this is only because of the reverse bias voltage between gate and the source here. It is seen that at that potential we are going to create some breakdown of that given PN junction there. So friend, that's why the name is coming as the breakdown junction there. And we had to avoid this kind of happenings in the device here, which is not good for the device. So friend, these are my references here. I hope that you like this video and hope that it is helping you to understand some of the basic concepts of the fit. So thank you friend for watching this video.