 So, in this hopefully short lecture shorter lecture I want to give an outline or illustration of an interesting like placement algorithm for placement that uses the idea of min cut partitioning. So, through an example I will illustrate some important role of partitioning in design of a placement algorithm. In fact, like as I described in the last lecture in the previous lecture there are different kinds of placement is a very important phase of physical design automation and there are various different kinds of algorithms for placement. In fact, it is a very rich area lot of algorithms have been ideas have been researched upon and broadly one can classify this placement algorithms as iterative as like recursive which are top down which are based on this kind of partitioning idea. Then there are some algorithms which are iterative which are based on very celebrated simulated handling idea or like this physics based idea of mass springs called force directed placement. There are some very interesting mathematical or linear algebraic approaches which make use of the Eigen spectrum and of connectivity information there is a matrix called Laplacian matrix which is defined using the connectivity information. Its Eigen spectrum that is Eigen values and Eigen vectors are used to like you know solve a geometric version of this partitioning problem and from that combinational solution for partitioning is a cooked up. So, very interesting class different types of placement algorithms have been invented are being used in the CAD tools. So, for the limited scope of this lectures as an introduction or overview of some physical design concepts I would just focus on the partitioning based recursive or top down algorithm. Again very natural divide conquer idea and just want to connect it up with the important rule of partitioning. I mean partitioning can be done manually at the level that is the designer has kind of indirectly implicitly specified. If designer has specified there is a data path there is a controller. Obviously, natural partition would respect that controller should be separately layout for a controller should be separately done layout for a data path should be separately done. If data path further is kind of like you know logically built up using some like portions like say fetch unit decode unit execute unit. Then the partitioning can manual partitioning or a designer specific partitioning implied partitioning could like you know induce the placement algorithm to look at the separate logical portions like fetch unit decode unit in case of a CPU data path to be implemented to be process for the layout generation separately and then things can be stitched together. That is a divide conquer approach and many of the times the partitioning is very natural is kind of implicit in the design itself or can be hinted or specified by the designer in a manual way. On the other hand if there is no clue about if we are looking at a subsystem and we want to make a good layout of it. We already have a floor plan we have identified a part of the chip to be used for the layout of a subsystem sub design and that sub design is still complex enough that we cannot get a placement or a routing in a ad hoc fashion very easily. So, we want to further reduce the complexity of this sub design by partitioning and corresponding area of the chip to be partitioned and this parts blocks of the sub design could be separately laid out on the parts of the chip area which is meant for the sub design and so on so forth. So, that is the notions behind that I want to illustrate one example in this in this particular lecture. So, it is going to be based on mincut partitioning approach it is it basically is based this discussion is based on an algorithm of Brower and an extension of that by Dunlop and Kearning Han. Brower this is at like the mincut idea the top down idea was use Brower like you know gave a clear definition of a mincut based algorithm for placement and Dunlop Dunlop Kearning Han extended it to include the so called terminal propagation idea which is a very neat like nice idea and without that one would actually not get a good like you know solution even though the partitioning can be powerful the recursive paradigm is obviously into you know, but the terminal approach is extremely important and helps in the quality of solutions as we will see in this example. Terminal propagation I mean propagation of terminal terminal meaning like input output pads that information is going to be propagated as we go recursively down in this process of mincut based top down partitioning. Let me recall some definitions notions again placement it follows floor plan floor planning stage in the floor planning stage here chip area is divided of sub designs sub circuits. So, floor planning is the is one of the is one of the earlier stages which is where some kind of logical partitioning manual partitioning would be used and corresponding the chip area portions of chip area would be identified and they were there to be earmarked for like you know the layout of sub designs and in specifically in part placement we compute of a figure out exact locations of each cell the sub design. So, we are we are already working on a part of a circuit and part of chip and within that we want to like identify the exact locations where this cells of that particular sub design should be placed. Now for the moment like for this lecture it will help to kind of forget about the floor planning part. So, we just assume that we had the full design and there is no floor planning the whole entire area is chip area is available and we want to divide the chip we want to use this mincut based approach. So, to divide the chip and correspondingly divide the circuit and independently trying like you know not too independently, but as far as possible in a decoupled way layout of sub circuits on to this portions of the chip and density took things together in an effective way. So, we might as well ignore the floor planning issue and we just assume that we have the full design is being placed on a given chip area. One of the main objectives of placement is minimize area and wire length total wire length or maximum wire length and so on so forth total or maximum it I mean you would wonder why total is important of course total is important routing, but in terms of delay maximum wire length is more important, but like both kind of influence each other. So, it is very difficult to get very clean optimization objective formulations in this area. So, lot of intuition domain knowledge has to be used to and lot of benchmarking has to be done to kind of validate the algorithmic ideas proposed the core algorithm development can be on an abstracted problem which may not actually reflect reality fully thoroughly, but because of the sophistication of the ideas one hopes that is appropriate and the offer a lot of scope for appropriate modification of those ideas to like you know help. So, in placement main objective of placement algorithm is to minimize area and a wire length. Wire length one can question whether the max total wire length is to be minimize or maximum wire length is to be minimize. Now, that is not too clear of course total wire length is going to influence the complexity that a router will have to work with and max on the other hand the maximum wire length is the main like it could be more important from the delay perspective, but neither of this is going to be a clean like you know optimization objective formulation. So, in fact it is typically hard to like formulate like very correct accurate objective formulations and for those the formulations can be so complex that they would not one would not be able to like make use of interesting sophisticated mathematical or algorithmic ideas for that. So, lot of emphasis is placed on getting good abstractions and then like modifying doing the post processing or like modifying those ideas in a slightly heuristic way for the to reflect the practical considerations, practical objectives. So, we will not worry too much about that we will roughly say that a wire length is to be optimized. It would could mean that total wire length it could partly mean that maximum wire length is to be minimize it could also partly mean that congestion of wires in like it is to be minimized whatever. So, here is hopefully this is this is an example of a circuit again this is from the book like by Cahang, Lienig, Markov and Hu by Springer. The book title various a physical design from graph partitioning to time inclusion yeah. So, this is the net list logical net list and let us say yeah I mean the objective is of the placement is to could be to to lay it out to create a layout for a one dimensional layout or for a two dimensional layout and then followed by a router which will also complete a routing and connect things up to this IO pads and give you a layout of the chip. Symbolically this is how a one dimensional layout will look like this is how two dimensional placement will look like one dimensional placement, two dimensional placement. This might look a bit funny, but yes I mean a lot of problems can be abstracted to one dimensional placement where you have a row of standard cells you keep large number of gates on to that and then you can go to the some something similar with the other rows. So, it is like practically useful, but more typically we are going to have two dimensional layout issues problems to be solved. So, this circuit like which has this 4 6 8 gates is to be is to be laid out on a two dimensional placement or one dimensional placement and you know depending on which how we chose the locations of this A B C D F G H whatever it would give us different wire length estimates or different kind of wiring complexity. So, this routing can become difficult if this particular placement well far worse it is not clear whether this is the best placement. Anyway this is just an example how things would look like what is the objective of this like placement algorithms. So, here is another example again it is not the details are not too important. So, on the left you see one instance of a placement of the same say not same some set of cells A 2 whatever if there is a and there are some wires which are connecting them if there is a placed in this kind of positions then the wires seem to run in some may be disorganized, but not too congested way. On the other hand for the same set of like cells if you make a different placement then the same set of wires logical connections they they will look far more congested when they are laid out. This is not actual layout or routing of the wires, but even if it abstractly this is going to indicate that it is like there is more scope I mean there is more possibility of a worse bigger congestion and more difficulty in routing and a quality of the layout. So, the placement decisions would matter like a lot in getting a good quality layout. Now, over here I have an example again the details are not too important here unlike it is not an example where we are going to work out a delays and some numbers. So, here is simple net list and again there are whatever 6 gates and we have the we have been given this chip area which seems to have some locations where standard cells can be kept you know you do not think in terms of that, but the intention is to kind of identify 6 positions 6 different zones or cell locations where this 6 gates can be placed. So, in a in a list cluttered way or in a more efficient kind of to give us more efficient layout or as efficient as possible. So, let us say you know this an algorithm that is based on this idea of partitioning which will repeatedly find minimum cut and use it for kind of recursive as a for the recursive approach to divide the circuit and corresponding to divide the chip into parts and do this layout generation in a placement in a divide conquer fashion will be given initial cut. Let us say this is the initial cut cut 1 separates A B C from D E F. So, this is the circuit with some initial vertical cut and correspondingly let us say we have say arbitrarily chosen that one this part is to be put on the left side and this part is to be put on the right side. So, A B C should be somewhere here and D E F should be somewhere here. Now what next? So, separately we will be looking at partitioning some example some one particular example of partitioning algorithm, but we let us say we have some partitioning algorithm available that works with an abstract representation of this circuit. Abstract representation of this circuit could be like A B this could be one of the partitioning algorithm like Kearney and Lien algorithm which does not really bother about the electrical significance of bias source, drivers, directions and so on. Just uses a basic like essence of the topology here it is like A is connected to D B is connected to D as over here A is node A gate A is driving gate D gate B is driving gate D who is driving who is driven is not being represented here just some undirected undirected edges A connected to D B connected to D D is connected to E D is connected to E C and E are connected C is driving E in fact and E and F are connected E is driving both the pins on F, but essentially we just look at this we capture the essential information that is E and C are connected E and F are connected yeah it does not seem to be very satisfactory, but still I mean you know this could be one of the starting points for your investigation. So, and cut one that has been given to us initial cut is reflected as something that separates A B C from D F. So, over here in this abstract graph picture this is the cut one. Now, we first would try to get the best two way cut I mean in general if the circuit is this graph is very big the best bipartisaning to two cut cutting it into two parts with equal sizes and with minimum number of edges crossing is a hard problem. So, but in this small example we will be able to work out the best one. So, for example, some algorithm will help you figure out that A D B can be on one side unlike in the initial partition and C F on the other side. So, initial partition was this, but this turned out to be a poor partition in fact yeah there are three edges cutting across, but if you were to use this partition that separates A B D from C F that would be the best one it would cut only one that is over here. So, clearly this is the candidate to be laid out on this partition is should be used to like you know put this portion over here and layout this portion of the circuit over here should try it. We have correspondingly divided this chip into two parts let us say by vertical cut line in the left part I will attempt to make a layout of this and the right part I will attempt to make a layout of this that seems some very natural way to go further right and again the same these two sub problems can again be done in the same recursive min cut based up way fashion. You finding the minimum cut again dividing this into again using vertical cut, but may be more natural would be to like you know do alternating kind of horizontal vertical cuts. So, in the next stage while laying out this on to the left part or laying out this on to the right part we could use horizontal splitting of this chip area by this horizontal cut line. And obviously, there will be more interesting variations of this like adaptations of this I am not trying to give you the best algorithm, but something that that explains the idea very simply. Now, we have a problem I mean we have two sub problems one of implementing ADB on one and one other one of implementing ECF and this sub problem and this is the best cut that we have. So, here ADB somehow we will we should cook up a good layout for this we should cook up a good layout for this is not a layout, but I am just saying that this is to be placed here this is to be placed here or this is just not full layout algorithm just a placement algorithm. Now, as and of course, this wire will also have to be placed this is not placement yet, but we have identified that this is to be targeted for this is to be targeted for this and this wire will have to be correspondingly laid out during the stitching process during the conquer process. So, recursively we go down further and look at this sub problem on ADB again the best cut will be something like this is the best cut and for ECF the best cut could be this it could be other equally good cuts, but let us see this and based on this we will like put mark A and B A and D to be in the upper half previously we are divided this chip into by a vertical cut line now we are going to divide using horizontal cut line A B and D where A D and B where to be on this and using this because we have separated ADB circuit into this two part using min cut I will correspondingly have the split objective refine objective of making a placement of A D in this part and B on this side, but we should have the wiring to complete the picture and similarly I say C and E are to be put here and F is to be put here and N F now that has been probably decided we could have could have been we could have been apparently justified to put C here in the bottom portion and F in the other portion or this way also, but let us say we had to make some arbitrary decision in the absence of any other hint any further information that is what I am going to lead on did you on to the so called the idea so called a terminal propagation which is due to Dunlop and Cunningham. So, further like you know we have now four sub problems the problem of AD placement of AD the sub problem of placement of B which is really already solved and similarly the other non-trivial sub problem is of a layout for placement for C E for that again we divide this and this. So, this is going to lead you to this color coding is nothing specific, but now for like you know in the absence of any other clue we could have placed D here and A here and similarly C here and E here and we might have placed B over here and F over here yeah I mean like the sub problem about doing a placement of AD in this portion could have been further divided until we do not need to go any further and then we could have maybe decided that D is over here and A is over here. So, that solves the problem for a placement of AD in this portion of this chip the placement of B is arbitrarily decided to be here placement of F there is no contention, but say a bit arbitrarily we decided to put it here C and E in this way way, but then completing the wiring if when the router completes or we try to estimate the wires symbolically the wires are to have to be connected this way C to E and C to F and D to E right yeah, but does not look to be look like it is too bad, but clearly there is a better looking solution I mean and just the example is small enough just to help you see that we have not arrived at I mean by doing something arbitrarily although we have made use of minimum cut the best cuts at different times. There was a plenty of choice in relative locations and that might have you know you would like to get like to do something extra to get a better solution. So, we have this layout, but this is not as good as something that we hope that we could have found A, D, E, C on the same chip this would we would like to arrive at this even for this simple example I mean and so clearly what has led us to this has been bit of arbitrariness in the choice of like A, D is to be laid out here I mean it does not matter whether you as far as this sub problem is concerned does not matter whether you put D here A here or the vice versa. So, we had taken some arbitrary decision and that led us to a poorer quality. So, we would like this we like to be able to make use of some extra information which will help us the to some layout of this kind and that will that is something that will motivate the extension of Minkert algorithm due to Dunlop and Cunningham. So, remark. So, the Nive Minkert algorithm which simply relies on finding the best cuts and not really like think about other information this such Nive algorithm does that algos do not consider the location of pins. So, exactly what that means we will try to illustrate to example. So, for example, no where in this algorithm that simulation that illustration that we did we know where kind of worried about things like if a cell that is connected to pad external or like you know or connection to other partition. If we have some information about that with this some cell is to be connected to the is has to be near a boundary a particular boundary then since that kind of cell will be placed or should be placed close to appropriate boundary. So, the location of the pad is going to be used in this decision about placement. So, this kind of like idea did not apparently was not apparently getting used and Dunlop Cunningham developed this terminal propagation idea to give some do some justice to this as an extent to and to enhance browse. So, let us take the same example and to highlight the main ideas here again you will have to take things with a bit of pinch of salt example is contrived to illustrate some points we should not try and punch unless it holds in that like. So, it is now let me go back to the same example. So, we are already had found a good cut for the overall circuit and that is A D B and D and E were connected. So, in terms of placement problem we kind of committed that this A D B will be put somewhere in this left part and the right part E C F. I am deliberately drawing them in a very like you know congested way just to indicate that I have not yet made I have got the input for this sub problem and a good input for this placement sub problem. So, I have the topological information which. So, I am just going to as in that initially I have no part no placement information. So, I am going to as if like you know as in that everything is at the center of the like near the center of this part and everything is going to be all this are going to be a near the center of this right part of the chip that is why I drawn them in a congested way nearby and they has to be this edge ok. Now, to do the while solving this sub problem of getting the placement for A D B we let us say that is file this is important. So, now we are trying to further solve this left sub problem by splitting it into left top and left bottom. So, here E C F this is E and this is. So, here we recall that A D B was split into for like you know we had for solving the left sub problem we had to make a partition get a good partition of A D B and that turned out to be A D on one side and B on the other side and we decided to kind of put A D on in this left top this is L T this is L B and this is R right part which we are not yet touched. So, now you see that this connection D E is like you know compared to this where we did not have any like you know we had not separated A D B in top and a bottom part now that we have separated the connection from D to E will kind of predominantly be here. So, Dunlop Cunningham's approach is to kind of and like whenever you have situation of this kind where things things get separated I am not describing it very formally intuitively like you know this the fact that A D has been moved here how that fact is to be reflected while solving the right sub problem is done with the help of an artificial connection pin called P dash. This P dash is included here is kind of introduced here to capture the fact that this net D E is connecting D on this side and E on this side, but D is already placed in that top left top part. So, P dash is kind of placed at D on this boundary of right side shared boundary, but in this upper half. So, with the fixed location of P dash we are hopefully be while solving the right sub problem will be able to put decide on the relative placement of E and C more appropriately that is the idea. So, P dash is going to be a fixed location over here for the right sub problem. So, this is the way we are kind of propagating some information about this is not exactly terminal propagation, but in general it is to be used for that we are propagating some information through terminals like artificial terminals or artificial pins. Yes, I am by the way I miss this D to B. So, we have decided that A and D are going to be in the left top this is L T and B is somewhere here and this is P dash this is E C F this is the right sub problem that we have not yet touched, but now we are going to address this. Now, while solving the right sub problem we are going to take pay some attention or give some consideration to this P hat which is P sorry P dash which is fixed over here that is that is going to be an input part of the input to the right sub problem, but the main thing is about partitioning this E C F. So, E C F we are going to spread it into E and C and F on the other side, but it is going to be clear now that this part is same A D P hat B. So, E and C are going to be brought in the upper part because if we were to like you know put E and C over here it would be worse because it will be worse because E has to be connected to P hat P dash which is in the top part. So, E and C both should be here. In fact, we are not making any relative placement of E and C we are just deciding whether E and C should be in the top part or in the bottom part and whether correspondingly F should be here or here, but it is natural that since P dash is connected to E and P dash is fixed to be in the top part E also along with C should be in the top part. So, this is my right top and this is my right bottom. So, I have like you know kind of done one level of this problem. So, I am not fully recursively completed that. So, R has been spread into R T and R B. Next let us say we focus this is the situation we have A D sorry here I am missing I should not miss this. So, let us say we want to like we solve this problem for L T. So, L T is to be split into L T L and L T R. So, I am going to split this L T into two parts left and right part and correspondingly move I mean put A and B place A and B in appropriate portion. So, everything is as it is P dash E C still un placed over here only thing that we have decided is that E and C are going to be here F is going to be here B is going to be here, but now we are deciding on the replacement of A and D we are solving this problem and for that we made a partition A and D are to be in separate parts, but I am not clear because of the connection of D with P P dash D has to be over here and A has to be over here. So, you can regard this as being influenced by P dash in some sense it might be I mean if you do a recursion a bit different way things may or may not or, but this is the main idea one can like in fact you can have your own variation of Dunlop Kearney and algorithm where you make use of this terminal idea propagation idea in a different way. So, like do not assume that I am sticking to exact description of that algorithm in fact the idea is to kind of learn this so that you can invent your own or discover your own modifications or figure out like you know alternate approaches and so on. Now, this left top problem is completely solved right so L T L L T R left top right is solved this is left bottom now we will go on to solving this a problem and then later on we will pay attention to this. Now, to figure out the placement of B whether in this or this again it will help to think of this as P double dash. Now, because D is in the right part of left top it is clear that because of that P double dash is going to be like somewhere fixed along this boundary and because of that B has to be when B has a choice of being here or here left bottom right or left bottom left it would be it would be placed the algorithm would place it more like justifiably over here. So, this is my P double dash and this will force B to B here we had we had to decide where B should be and with the help of this P double dash we had decided that B should be over here this is L B L L B R. So, we are basically solving the L B problem I mean like you know making a fixing the layout for this left bottom by like you know recursively dividing things into L B L and L B R and there is nothing to be done here and B when it has a choice it would based on the location of P double dash it is connected to B will be more logically over here. So, this is solved the left side problem completely now similarly the right side problem now let us focus on this R talk problem and this will take us to this is fully done with the help of P double dash this is with the help of this. Now, E has to E c has to be R look at this R T the E c has to be split in two parts E and C where should whether E should be here or E should be here C should be here or C should be here that is again going to be influenced by P dash. So, E is more logically here and C is over here. Moment E and C get separated this way the connection to F gets like biased towards in the upper portion earlier where I had drawn this connection between E and F to be like this, but now I will show it in slightly more biased fashion and I will call this cut like you know this point on the cut line connection as an artificial cut line point called P triple hat. So, now it is clear what is the purpose of this just the way P double dash induce this B to come on this side rather not on this side P triple hat is going to induce F to be placed here not here. So, from here clearly what we are going to get is A B B this was with the help of P double dash this was with the help of P dash E C F this is the best layout that we are hoping to get. So, there is some role of clearly there is some evidence of role of terminal propagation it could be exactly like same as what done law of governing and suggested or it could be your own variation of that. So, I believe like the main point has been brought out that is with the help of the extra information about the terminals initially they could be the fixed location the this particular input has to come from outside world it could which is some other subsystem which is laid out on the left side. So, that input is coming through one of the pads on the left side of the chip and some similarly something else could be on the right side or top side based on that the placement of at some stage in this top down mincut base placement the locations certain decisions will be helped by like you know this information and will be able to cut down on the ambiguity and because of which one might get mislead in the later stages of the algorithm and this will help as this example obviously has been contrived to show the effect of this modification and we have arrived at this good answer compared to the bad answer that we did not like over here. We had by without use of any terminal propagation idea we would have we could have is just using the mincut we could have arrived at this, but instead we have managed to arrive at this kind of solution just confirm that it is. So, this is what we have arrived at exactly what we wanted with the help of P dash P double dash and P triple dash you see anything more yeah you can this example is illustrated bit differently as well as there is another example that you would find in the book just to confirm your ideas your understanding and learn more about it from the book I have avoided to discuss it in a very formal rigid way just kind of focus on the highlights import essence notions. Thank you.