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Embedded Analysis - Workflow - part 1

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Published on May 14, 2011

[0:00] Introduction
[0:35] Aligning top and bottom layer in gimp for tracing
[5:45] Map traces
[7:36] Using grids to determine via to chip PIN map underneath
[8:21] Tracing Xilinx JTAG pins
[9:10] Showing JTAG pad with soldier, using this to find related pads

Covering the start of opening a device to hack it. Certainly not exciting but hopefully helpful for some. This is just meant to give an idea of the workflow. With a workflow of any decent style digging into a new device becomes easier. More details on target shown: https://berlin.ccc.de/wiki/Frtizbox7170

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