 Welcome to this lecture on VHDL in the digital system design with PLDs and FPGA codes. In the last lecture we have seen the sequential construct case when and the loops, the generate loops and the for loops. And we have also started looking at the VHDL modeling of the sequential elements like flip-flops, latches and so on. So, let us run through the last lectures part quickly. So, let us turn to the slide, this is the syntax of the case when this is equivalent to the width select of the concurrent statement. The syntax is that case an input signal is and when value 1 value of this select signal numerical value you do the assignments statements ok. Various appropriate statements can come here and when value 2 then you say when others which is others means whatever is not included in this is combined together in others. So, the rule is that mutually exclusive values of select signal or mutually exclusive values should be specified and exactly like which select it is a nothing but a truth table. We are specifying the output the either the numerical values or in terms of some other input for the all possible values of some group of signal or some signal because you could if you have 3 inputs you could even combine them into a single vector and write this it is possible to do that. It is equivalent to width select but there is a difference you can specify the multiple outputs in each case. You can do the nesting that means a case can be nested within suppose you say when value 1 you can have another case statement ok or you can write a nif within one of the when you know one of the choices. So, you can have very complex combinational circuit specified by this structure this syntax. We have seen an example suppose we have value 1 value 2 if we have a and b specified then the equation is x is a and decode of value 1 or say c and decode of value 2 or like that it goes ok. And if you miss anything suppose you fail to specify x here then for that value it is an implied latch there will be a feedback. So, you need to take care same as an if you could mix case with if or complex kind of structure. So, here I am showing we have an input signal select. So, case cell is when value 1 I am saying if condition 2 condition 2 is some as we discussed it is some Boolean condition composing of some inputs ok. And why get say else if it goes like that. So, if you look at this part then the equation is y is a and condition 2 and sorry and decode of select equal to value 1 and condition 2 as I said it can be composed of the or of many product terms it expands it is a very kind of little abstract way of saying that the equation. But it can expand and we have seen an example of a case when construct we have taken a 1 to 4 demultiplexer each is 4 bit you know the input is 4 bit outputs are 4 bit. So, if the select line is 2 bits because there are 4 outputs if it is 0 then y goes to a 1 y goes to b and so on. So, that is the library declaration this is a entity wherein we have y which is a 4 bit vector s 2 bit vector and a b c d are the outputs which are 4 bit vector. And this is architecture declaration region before the begin we have nothing to declare in the statement region. We are going to use a case when so this is a sequential syntax so you have to use a process and in the sensitivity list input should be there and so y and s has to be in the sensitivity list then we are going to use the select line for all the values of select line we are going to specify the output that is a most natural thing for a multiplexer or a demultiplexer that is a natural way of describing the behaviour. So, that is shown here process s y this is select line this is a input begin case s is and when s is 0 0 we say a gets y and we have to specify b c d everything ok. Similarly for 0 1 b gets y and c gets y d gets y for 1 1 rest all is 0 0 and we can say when others everything is 0 you could even write others here because this is mainly for simulation and we can combine 1 1 with others only thing is that if you happen to give some unexpected values like z z to the select line then it is difficult to debug this 1 1 with the other cases and all that. And one more thing what I have found is that some people some students think inactive means tri-state and they tri-state it is a very dangerous thing to tri-state it because you have an output a single output which is just one output which is going to many input if you tri-state it means that this lines are floating it is connected with the high resistance to VDD high resistance ground. So, it is not strong drive so the input is kind of floating and the various inputs which is driven by this output can treat it as depending on the some noise pickup it can start switching ok. So, do not tri-state it unless it is a bus and even in the case of bus when everything is tri-stated it has to be pulled up or pulled down weekly for a proper state otherwise it is dangerous to have a bus tri-stated particularly an output tri-stated. So, please understand that and one problem with this code is that everywhere you have to write all the outputs it can be kind of cumbersome to track it and all that. So, there is a better way that is at the beginning you make everything 0 and in choices you make only whatever is required ok. That is no issue because you know that as far as simulator is concerned when event happens it goes from top to bottom. So, A gets say suppose the select line was 00 then A gets 00 but immediately in the same kind of the process computation A gets Y so that is replaced. So, they are not at say t plus delta A gets Y it is correct and synthesis tool should make out that it is at the beginning it is initialised to 0. So, synthesis tool will look at the code part and will infer this kind of behaviour there should not be a problem. But I said that I want you that do not take this kind here to an extreme play with delta cycle play with all kinds of initialisation and hoping that your reasoning would be kind of understood by synthesis tool. But definitely the tools are getting smarter ok. Tools are getting smarter means that the tool vendors are kind of accommodating more and more novice engineers or dummies and many times we are happy that you write some kind of arbitrary code and the tool is making sense out of it ok. That in my opinion is not a very good trend in the sense that because there is no rule specified you know you do something and you get most of the time things correct because the tool vendors know that what all kinds of possibilities are there they are trying to incorporate. But sometime reasoning wise it does not make much sense. So, do not be very happy that you write something and the tools make sense out of it. I mean better stick to rules and what is most you know kind of reasonable stick with it than you know take too much liberty with these kind of syntax. And then we have seen the loops the concurrent loops are generate and the sequential loop is for loop and generate is used for with equations that means if you have a kind of regular modular structure repeated in equation or in components that can be easily compressed by the generate construct that is the idea behind it. And we have seen as an example a ripple adder 8 bit ripple adder here and you know that the basic building block is a full adder wherein there are inputs are 3 a b and c in 2 outputs are there the sum is a x or b x or c and the carry out is a b or b c or ac ok. That means more than 2 or more inputs are 1 then the carry is 1. And when we try to make a ripple adder you know that a 0 b 0 and c 0 comes here sum 0 is output. The output of the first stage is carry 1 which is fed into the carry input of the second state then you get sum 1 carry 2 and it goes on ok. So, if you write an entity you should have 2 inputs which is 8 bit which goes from a 7 down to 0 b 7 down to 0 these are the inputs and the outputs are you know the sum 7 down to 0 ok. And if you want you can include this carry as part of the sum you can say sum 8 down to 0 it does not matter how you define. And we need an internal signal maybe this I missed in the last class because this an internal signal carry which is 8 down to 0 because we have for convenience we are naming this carry. And definitely this carry 0 can be if you want defined as a carry in and this carry 8 can be kind of assigned to sum 8 or carry out depending on your need. But that is how the entity is declared then you can write a equation in generate loop which say for i in 0 to 7 generate say here sum of i is a of i x or bi x or carry i. So, it is sum 0 is a 0 b 0 carry 0 and carry i plus 1 is ai bi or ai or bi and ci this is nothing but ai ci and bi ci ok that when you expand and here you see that when for the 0th loop these are 0s and this is 1. So, you get a carry 1 as output in the next iteration for the sum the carry 1 is the input so naturally this happens ok. Now with regard to component instantiation you write an entity and architecture to implement this but now you write a top level code I suggest you write the code for it with component declared as a full adder of this particular full adder we have written. Then you define a signal called carry which is a you know 9 bit then you do this kind of component instantiation through generate loop for i in 0 to 7 generate then give a label you say full add that is the entity name of this port map and I am assuming it is in ports are defined in this order carry a b sum and carry out. So, you say carry i ai bi sum i and carry i plus 1. So, this also naturally it will happen the 0th iteration it is carry 0 a 0 b 0 sum 0 is output carry 1 is output and the next iteration comes the carry 1 is the input. So, this output of the first stage goes as the input of the second stage and you get this structure by this simple statement and as I said this can be used very easily when the structure is very symmetric or balanced or regular but if you have any regular structure like say you imagine carry look at adder it is little more complex the first stage is small the second stage is bigger than the first one it have more inputs and the third stage will have much more inputs like second stage will have you know the not only a 1 b 1 it will have a 0 b 0 also as input and carry 0. So, as it comes down it expands and it is little tough to write a generate a loop for that it is maybe not possible also but you can write a for loop which is sequential we will see that maybe or you try to from whatever I say I suggest you work it out. You try to make an 8 bit carry look at adder using either the generate loop or the sequential loop you might need little more input on that maybe I will give as we go along. And you can have conditional generates some condition if some condition is true then you can say generate this is true for generating some regular structures like as I said maybe the carry look at adder you have to try it I have not tried it. Because once again one thing connected with that I want to make mention many a times the hardware when we write design we do not worry about the length of the code okay like in a software you write say c code then you know that if somebody as you have an algorithm you are trying to implement. Somebody has implemented that algorithm in say 200 lines and somebody else has written the same algorithm in 100 lines say without loops and all that it is not I am not talking about loops then it is for sure that that c code with 100 lines will execute faster complete faster than the c code with the 200 lines. But in when you talk about hardware this need not be true because the hardware is not trying to execute your line it is going to synthesize some circuit out of the written code. So it may happen that somebody write an hardware description of a circuit which is longer than somebody else but it might turn out that this whatever is written longer will produce a smaller faster circuit it is possible okay. Ask me for an example but then if you care you can work it out okay there is no issue. So when you are designing hardware using hardware description language you have to worry need not be the number of lines of code okay. So maybe because you know that we many a times work with 8 bit, 16 bit, 32 bit, 64 bit even if you need to copy paste something modify something sometime it is not worthwhile to try to write very concise loops which can work for you know 8 bit, 16 bit, 32 bit, 64 bit and 1024 bit God knows when a 128 bit processor comes or it is required or the such memories sizes are possible may come but then it is not a great need to write loops and compress the code and sometime when compressing you could write a very complex loop to come out with the regular structure you know you can take great pain to make it very generic and all that. But sometime the readable TV goes down sometime it is not worth the effort you know how much time it takes suppose you take an 8 bit the carry look ahead adder as an example but maybe in like in VLSI you do not look use carry look ahead adder but then it is not a great effort to copy paste and modify it might take 10 minutes to correctly code it does not really does not matter. So I just mentioned this because it may be it is the right place to mention it that is all. So yeah so let us come back to it. So sequential loop the syntax is for i in something 0 to 7 loop instead of generate n loop and you write statement here okay that is the syntax and here I am showing a for loop like it is a if reset is 1 for i in 0 to 7 before i is other 0 n loop okay there are other ways of writing this you could write without a loop if you want that is not what but it is just an example and this is quite synthesizable there is no issue because of as I said the FIFO each location is initialized to 0 and this is 8 bit location and FIFO has maybe so many entries maybe 256 entries or 2k entries it does not matter. It essentially means that all the flip-flops used in FIFO the reset is connected together and when it is asserted it becomes 0. So there is nothing it is not a great it is very easy to synthesize and people make very generic statement like loop is not synthesizable which is not true which as I said it essentially means that you have an algorithm where loop is there if you directly translate that into VHDL you may not get the circuit which implements that algorithm. That is the meaning when somebody say makes a sweeping statement the problem is that many times the speakers themselves does not understand what they are saying what they are probably they are repeating something they have heard. So that is also do not get worried too much about it and here also in the loop also you have conditional loops you can say while some expression is true then you can loop and loop and one example is that in the case of test bench you would have written test vectors in a file and normally you read line by line and the top level code will be like this the outer loop will be like this while not n file vector file and this n file is a procedure or a function which say when you reach the end of the file then loop if you have not reached the end of the vector file keep reading the lines and do whatever is required that is the meaning of it that is one place it is quite useful not for synthesis this is useful in simulation for verification. You have loop control the exit that means wherever you say exit can be exited not very useful you know kind of the plain exit because that means you are not using that loop after that when you encounter exit but you can say on a condition when some condition is met you can exit as I said it can make some irregular structures or you can write if condition one then exit. Next is skipping the loop again a conditional skipping may be useful it is similar to the sequential language you could even write instead of next when condition you could write if condition then next end if and we have looked at the sequential circuit elements the modelling and we looked at the flip-flop behavior is that if a clock comes active clock comes the tree is transferred to the queue and we have written we have written a process with the clock in the sensitivity list this you know kind of catch the edge the transitions any event happens on this and in the code you write if clock is equal to one along with this event and this clock is equal to one will make it kind of the positive edge then you say q equal to d and you say end if that means if this condition is not met you remember that you know that is it is a perfect code for simulator but as I said the synthesis to look at the code within the process body and that says if clock is one q gets d that means as long as the clock is one q is d and it will become a transparent latch okay and this end if is the one which is specifying the memory element so we are using that implied memory to kind of describe the behavior of the flip-flop. So there is a compatibility problem with this code like this works this is a flip-flop for simulator but it is a latch for synthesis tool. So essentially to write a flip-flop for you know the synthesis tool you need to bring in the event on the clock and that is by specifying like this you say a clock tick event that is any event on the clock and clock is equal to one q gets d end if but the problem for the simulator is that there is a redundancy like this says that if there is a event on the clock but once again it comes to the code that is repeated but it is still okay because we cannot do without this sensitivity list. So for the synthesis tool we write clock tick event and clock is equal to one and this kind of takes care of the event on the clock as far as synthesis tool is concerned. For simulator there is a redundancy that the simulator starts computation when there is an event on the clock and once again it is repeated but it is okay because this is a code where there is compatibility between synthesis and simulation. Earlier code is dangerous in the sense that it works as a flip-flop for simulation and latch for synthesis. This works as a flip-flop for both simulation and synthesis there are two things to remember that when you say clock tick event and clock is equal to one. So we are kind of reasoning out the behavior saying that it means the positive edge okay. So now if you think you know if you hunt around the syntax of VHDL and come with some other ways of describing this particular condition it may not work with the synthesis tool because this is accepted as a template for the positive edge okay. So it is not that everything every possible way you try to represent this kind of behavior the synthesis tool will understand because that is just software even if you apply kind of machine learning to it there will be less possibility that so you should think that your when you say synthesis tool it is just a set of algorithms or software which try to make sense out of all the code you write. So you should stick to the standard rules of the game not try to invent kind of ingenious ways of describing the behavior and hoping that that will be kind of accepted as that particular behavior okay. And another problem here is that when you say clock tick event it could mean any event it is not that 0 to 1 because we use standard logic and you know that an example is that when you start simulation normally everything is kind of initialized as u if it is not initialized properly. So it may happen that the clock is flagged as u and when you start applying the clock it becomes transit 1 or 0 such a thing can happen then this can be is a valid condition as a kind of it is a u to 1 and 1 then this can get latched that means there is no problem in the real hardware it does not happen in the real life. But in simulation this can happen and that can be problematic because suppose you have a counter which is counting something and if this happens it will start counting at the beginning only. There is a miscount at the beginning but when you in real life you look at it that the count will be 1 less. So this you should be very careful there is no harm writing the code like that but when you simulate make sure that the behavior of the simulation and the behavior of the real circuit is identical and particularly with initialization and mis-trigger and all that. So that you get what you are hoping and what you are expecting and you do not kind of otherwise maybe you are hoping that you know the behavior properly but you do not know why that happens in simulation. You do something else to sort it out without understanding the problem then that will work may not work with the real life circuit. So always keep very you know alert on the initial part of the simulation all initialization should be proper particularly with this respect to this kind of data types it initial values the code you write and all that. So but there is a way to overcome that the problem is with this attribute clock tick event is an predefined attribute which only means an event on clock okay it is not that it is 0 to 1 or 1 to 0 but way to avoid that is that there is a function in standard logic 1164 package there are two functions one is called rising edge in the bracket clock and falling edge bracket clock this correctly you know returns a Boolean true if there is a transition on clock from 0 to 1. Similarly falling edge will return a true if there is a falling edge or negative edge transition on the clock only problem is that and you write you know instead of if clock event clock is equal to 1 you write if rising edge clock and it is a the return value of that function is a Boolean true or false. So if rising edge clock you can write the only problem is that in terms of computation each time such a thing encounters this particular function is called. So if you take a maybe some 1% or 2% of the computation time could be extra may not be a big deal with the person they kind of computing power that is only kind of negative or the fault part of it. And the question is that can we have the concurrent statement which specify which by which you can write this code the flip-flop okay. So this says that if clock tick event and clock is equal to 1 then Q gets D end if okay. So naturally you know that when else is equal and do if so if you try to do this you can say Q gets D when clock tick event and clock is equal to 1. And you know that when as an else part you do not say that okay then you get the equivalent concurrent statement. So Q gets D when clock tick event and clock is equal to 1 then you get the flip-flop using concurrent statement at least the simple flip-flop with the concurrent statement. So let us come to the D latch now the earlier we wrote a code for simulator the flip-flop code for simulator then it happened to be a latch force in this tool. So let us put that let us look at the latch functionality so it is that if clock is 1 then whatever is at the D will come on the Q when the clock goes low it remembers okay. So the code as far as the synthesis tool is concerned you say process clock begin if clock is 1 then Q gets D end if the synthesis tool looks only at this if clock is 1 then Q gets D end if. So this part is correct you know but for simulator see if you write only the clock in the sensitivity list. So this condition is checked only if there is an event on the clock okay if there is an event either goes from low to high or high to low then the clock is 1 is checked and Q is assigned D. But you know that when the clock is 1 if D changes this code will not make the Q D as far as simulator is concerned. So basically because it is not sensitive to D so for the simulator to get a latch you have to make the input D in the sensitivity list. So that is the code for the correct code for latch as far as simulator is concerned for synthesis tool absolutely no problem because it looks at this code it is perfectly okay whatever you write here. So that is the code process clock D begin if clock is 1 then Q gets D end if it works because if there is an event on the clock. So it comes and checked clock is 1 then Q is reflected after sometime the clock remains same but there is a change in D. So that comes here if clock is 1 the Q gets D but if clock is 0 suppose there is an event on D and clock is 0 like this you know there is an event on D, clock is 0 nothing happens it remembers because event on D it is written clock is 1 Q gets D clock is 0 nothing happens because of end if it retains the old value. So this is the code for transfer and latch which is compatible both for simulator and the synthesis tool. So we have looked at the latch code and the flip flop code there are some intricacies some details you need to understand. So I suggest that you know grasp this concept clearly so that you are clear because once you are clear because we are kind of come to the core part of the VHDL as far as synthesis is concerned. So we are kind of completing we have completed the sequential sorry the combinational circuit perfectly because you know how to what is the meaning of which select when else if then case when loops all that you know so as far as combinational circuit is concerned and now we are in sequential circuit main thing is the registers and the combinational circuits. So we have learned how the combinational circuit can be coded now we have we are learning how the registers of flip flop can be coded. So this together should work only thing is that maybe what need to be learn is that maybe can we combine these together so that you get less code or something like that that we will see. But we are kind of coming to a as far as synthesis is concerned we are dealing with the most of it. So please understand the concept well so that you can design properly. So here the question is that can we have an concurrent statement equivalent to this like here the again if the main the crux of the coding is if clock is 1 Q gets the end if okay. So you can say Q gets the when clock is 1 and terminate it you do not say end if so that gives an implied latch and it works perfectly. So equivalent concurrent statement is that Q gets the when clock is 1 okay that means whenever there is an event on and you know that as far as the concurrent statement is concerned the simulator computes whenever there is an event on the right hand side. So if there is an event on D event on clock this will be kind of computed. So which say that if there is an event on D event on clock then this will be computed that say if clock is 1 Q gets D otherwise if clock is 0 it remembers. So this works perfectly with regard to this and there is another syntax like we have looked at this particular syntax as far as latch is concerned but there is another way of writing it instead of writing the signals in the sensitivity list you could write use a weight statement. So that is what is shown here please look at the code and try to make sense out of it. So in this code you have no sensitivity list and you say process without any qualification and here you write the code and you say weight on clock and D okay. So normally when you have a process the weight goes is that at the beginning it computes once then it waits for event on the kind of these signals. So it is similar like at the beginning it is computed 1 then it is waiting on for any event on clock and D if there is an event on clock and D it goes and compute once from top to bottom and again wait for event. It is nothing it is exactly identical either you specify the clock and D here or at the end you say weight on whatever was here mind you you should not do both then it does not work because there is a it waits for an kind of event on this computes it again it waits for event on that and even happens it comes back and gets stuck there. So either you should use weight statement or sensitivity list not both. So let us maybe it is a right time to look at the kind of the syntax of this weight statement and there are 3 kind of types of weight. You can as we looked at before you can say weight on a list of signal sensitivity list you can say weight until some condition is true okay or you can say wait for some expression in terms of time you know you can say wait for 10 nanosecond okay like that. So this is what we have seen weight on we have seen you say weight on clock and D that means weight for some event on clock and D. It can be used for both for synthesis and simulation no issue some as part of the simulation you want to like you are writing a test bench you are waiting for some event on a clock to continue with the test bench you can do that and you can write this weight until count is 10 that means you come to some place you have some counting happens you can say weight until count is 10 okay absolutely no problem with the simulation and for synthesis you have to think okay. If in the code you can really make sense that it you can easily for yourself work out the structure for synthesis then it works otherwise be very careful and wait for 10 nanosecond it is only for simulation wherever you say it waits so just do not think that you assign some output and you say wait for 10 nanosecond the synthesis tool will give you a delay of 10 nanosecond or something like that. And you can combine these wait on and wait until with the four and things like that here wait on clock for 70 nanosecond okay it can be used for simulation it means that wait for an event on clock or 70 nanosecond I mean for 70 nanosecond you wait on clock I mean at 10 nanosecond if there is an event on the clock continue otherwise till 70 nanosecond the simulate of wait for an event otherwise it continues exactly same like same like this you have say wait until sum is greater than 100 for 50 nanosecond you say that wait for sum to be greater than 100 but that you do wait for such an event only 450 nanosecond if that does not happen 450 nanosecond you continue as if the event as happened useful for simulation it is may not be it is not synthesizable but it is useful very useful in test spend simulations and things like that. So let us come to this part then we have looked at the code for a flip flop without considering the reset and the code was like this clock begin if clock tick event and clock is equal to 1 q gets the end if end process okay. Now we know that you know practically we need to reset that is one point in design you should have a reset for flip flop okay we will maybe briefly touch upon it at this part because if you do not reset properly there is no guarantee that first of all we do not know whether the q will be 1 or 0 and also there is something sometime the strange thing can happen it can get stuck in between and all that. So you need a good reset and you know the asynchronous reset asynchronous means that when you say synchronous it means that it is synchronous with the clock asynchronous means any time you assert this any times you make it 1 this goes to 0 irrespective of the clock clock may be high or low or the activate come there are some timing requirement with respect to this clock but let us ignore that part okay. In real life there is some timing restriction with respect to the clock we will we have not learned the basics regarding that so we will ignore it for a while. So if you assert this the q become 0 and if it is like so it has a priority over the clock okay any time this is asserted then the q become 0 if it is 0 then it operates like a normal flip flop if clock comes d gets q. So let us think how to incorporate that in this code a reasonable behavior so naturally that means that no more the process we are looking for both simulator and synthesis tool together and so basically the reset is asynchronous. So the reset has to be in the sensitivity list because any time reset happens then the q has to go to 0 so we need to write the reset okay assume that we call it RST or something like that we need to write the RST here. Now it has priority over this business so that code has to come before that okay so we what we do is that we write reset here and we are going to say if reset is 1 then q gets 0 else if clock tick event clock is equal to 1 then q gets d end if okay. So that is what is the right code for asynchronous reset process clock and clock, reset begin if reset is 1 then q gets 0 and if there are this is a single bit if you have a register parallel register you say q get other 0 everything is made 0 else if clock tick event clock is equal to 1 then q gets d end if mind you you cannot say else because then everything is completed we do not have kind of implied large so that is why else if is specified here because we want to avoid the else then only that memory part is kind of specified. So there is no else if clock tick event clock is equal to 1 end if so that rightly kind of model the behavior of asynchronous reset. So that is it that is the code and that is the most useful code for a flip flop or a register there is no difference with parallel register you just make the queues kind of wide with the width whatever you require then you gets and the d is equal to that then instead of 0 you write other 0 then you get the code for the registers which is with asynchronous reset. So can we have the concurrent statement for a flip flop with asynchronous reset if you think yes we can say we can use when else which is equal and do the if then we say q gets 0 when reset is 1 else q gets d if else q gets d clock event clock is equal to 1. So you can say that you know q gets 0 when reset is 1 else q gets d when clock event clock is equal to 1. You can terminate without saying further else so that should give you a flip flop with asynchronous reset you can try this with you know with the synthesis tool you are using I will definitely show a demo of the tool. Now let us look at please look at this code first we will talk about the behavior of it. So this say that process clock I am not showing the reset you can add reset it makes no difference but which say begin if clock tick event and clock is equal to 1 then q gets ax or b okay. Now this says that when the clock comes q will get some input you know we normally write q gets d which say that q gets ax or b okay it is a perfect code it will simulate it will synthesize synthesis tool will generate a circuit for it. So we know that what happens when the clock comes when the clock comes d gets to q. So if this has to happen what we are saying is that when the clock gets q gets ax or b means definitely if that has to happen we know that the clock comes d is the one which get transferred to q. So naturally there has to be an exclusive or gate here with input a and b then only this behavior will happen and that is what you are going to get if you write a code like this you will get an exclusive or gate at the d input of the flip flop okay. So when the clock comes the q gets ax or b that is what is the meaning here what it says is that you could write a single process for a flip flop with some logic preceding it okay. So you could write one process and underneath clock d given and clock is equal to 1 you write q gets some combinant circuit that comes before the flip flop and as I said it need not be here it is a single bit it can be a raw of registers with a much more complex circuit and you can code it using a single process. So that is the meaning of it a single process can called registers preceded by any combinant circuit okay. So let us generalize it let us say you write a process I am not showing reset you can add reset to it just to make you know if I add reset then I have a problem of the statement going below my screen that is why I avoid reset and you can add it. So here process clock if clock d given and clock is equal to 1 that is a end if. Now you write any code for combinant circuit does not matter you know it need not be very simple statement like that you know you can write say a k is some select signal is then you say when 0000 then you say if you write anything you want as far as synthesis tool can make sense out of it you write a very complex behavior then what happens is that that happens like this you get a flip flop or a set of registers and depending on what you write and then you get whatever that combinant circuit you have written the code for that comes before okay. So it is very convenient way of coding a register and a combinant circuit preceding it okay not something after it. So you can always combine some combinant circuit followed with a register in a single so it is very convenient way of writing the RTL code a register transfer logic code I have avoided the jargons but that is what it is you know that is this is nothing but the RTL code that is what I have been describing all along even in the digital design I was emphasizing that. So here one danger you should understand that anything you write anything you assign suppose you write Z and an assignment operator Z will become a flip flop or register. So any assignment you make under this within this body you will get a flip flop free so very be very careful you know some people happily write code without thinking about it and that will have lot of side effect okay. So if you do not realize any assignment you make at that output of that assignment will be a flip flop and that could be unintended okay maybe you are trying to put say there is a sequential circuit and from the present state you are decoding something and if you write the decoding part within this clock tick event clock is equal to 1. You will get a set of registers or flip flop at the output of it and you simulate that in view you will find that for whatever reason you may not know the real you may not verify the what actual circuit you have got out of it you go into simulation you will find that the decoded circuit comes with a delay and then you do some adjustment to counter that delay okay. And you can end up in real soup with that and that is dangerous so you should now thoroughly understand anything you write here you will get a flip flop that is also good because you want to put some circuit complex circuit here before set of registers just write if clock tick event clock is equal to 1 then you write the code for it that you will get it any assignment will have a this one kind of flip flop and you could write that code using any constructed doesn't matter this is a sequential statement so you can use if then case when for so use any of the construct and happily write the code that naturally comes here. So that is what is like I have told today basically we have looked at the code for we have talked about the flip flop for synthesis and simulation and there is a issue with clock tick event because it can represent the uninvented event. So you could use rising edge and falling edge you can have equivalent concurrent statement for flip flops and for the latch as far as simulator is concerned we need D in the sensitivity list. So this works as a code for latch for both for synthesis and simulation you could have equivalent concurrent statement like this and you could use instead of sensitivity list wait on but not both and these are the wait syntax is wait on wait until wait for wait for is definitely for simulation. The combination you have to think whether it makes sense in synthesis we have seen how to incorporate asynchronous reset basically we write put reset in the sensitivity list before the clock event you write if then you get asynchronous reset. You can have concurrent statement equivalent concurrent statement and when you write something a combinational behaviour here you will get a combinational circuit before it and that shows how to write a register preceding the combinational circuit you write the code like that. So please go through this part thoroughly understand it grasp the concept well thank you I wish you all the best.