 So, we will start with the wherever we left last time and I think I was I planned to do buffer delta network analysis now. So, this is basically buffer delta how this whole thing will be analyzed by creating a simulation model as well as analytical thing and then we will be comparing it with the delta network which was there which we had done earlier and then of course, the cross bar. So, before we do this there are certain properties which were not evident, but now I think I am opening up one by one all of them. So, first one is a lemma actually which comes from there. So, if you have carefully observed the structure you can immediately know that this statement is correct and formally there is no proof required on this. So, this is basically 2 raise power n by 2 raise power n delta network there is a unique path from each network input link. So, when I am talking about a network input link it is the whole delta network the input to that when I am talking about a switch input link that is a input to switch in any one of the stage. So, network input and switch input are two different things actually similarly it is true for the output from each in network input link to each network output link which is obvious actually now. So, this was the definition which was given for in general for Banyan network there has to be exactly one path from each input to each output and that also means that has to be unique they are not multiple options. So, this is actually going to be true from each input to output there will be 2 raise power n possible each input to all the outputs there will be exactly 2 raise power n paths which are possible because they are 2 raise power n outputs. And this is obvious because from the first one this for a binary system remember I am not talking about a by b cross bars being used in between, but this is also true even for that. So, this case which we are discussing is actually buffer delta is path length is constant yeah path length will be constant from each input to each output that is true in terms of number of hops. So, it will be exactly equal to number of a stages minus 1 those many hops will be required for transmission from any input link to any output link or whatever n stages which are there. So, if you keep on expanding their total n stages each time you are multiplying it by 2. So, from each input you are going to generate exactly 2 raise power n paths and they are exactly 2 raise power n outputs there has to be exactly one a path available between each input and output which has to be unique. So, this essentially proofs come from there is by definition. Now, second one is more important observations this I observation I have not actually told earlier. Now, this one is a theorem as per the paper I am just using the same notation. This says that you consider a switch m m is a switch actually in the intermediate stage and this can be true in general for any kind of delta network a raise power n by b raise power n delta network also it will be true. But I am giving a very general statement here in stage s k. So, stages are actually going from s 0 s 1 to s n minus 1. So, that is the way the stages are defined total n stages. So, remember stages are numbered from 0 to n minus 1 from source to destination. Since paper is about 2 raise power n is a binary system. So, I am specifying 2 raise power n by 2 is prime, but this is true in general actually this statement will be true in general and this actually helps us in making the estimates blocking probabilities and all that thing can be estimated from here itself. And as I told k can take a value, but it will never be equal to n it is always less than n. Now, what I am writing is an input to a switch not input to the network. So, when I talk about the input to the switch k is always less than minus when it is never equal to there has to be exactly n stages. So, equivalently there is going to be also an output. So, I am writing technically 2 statements in one statement. So, you can replace whatever is there in the bracket also. So, I can read let i x and i y b 2 inputs or I can say let o x and o y b be the outputs. So, this I think a very standard thing this is about the switch. So, remember you take any switch in any stage there are if it is 2 raise power n by 2 raise power n every switch is binary. So, there is one top and one bottom there are 2 links input links is similar there are 2 output links. So, you can call them i x i y and o x o y whatever it is and now I think I need to I should draw this a flatter statement is fine it is clear, but usually what will happen is there will be a switch I am actually taking a for example, 8 by 8. So, let me make an 8 by 8 and I will give an example with that and I can take any arbitrary configuration of a delta network. So, I can take a shuffle or inverse bends both are fine. So, let me take a shuffle you take any switch from anywhere you take for example, this switch this switch can reach here. So, these 2 inputs can reach to this switch. So, I call this set in capital I of x this is I of x this will be I of y. So, this can reach here. So, these 2 this set is I of y number of inputs to the network which can reach to this particular switch is this on the output side. Similarly, this is one and this is one pair this you can call o of x and this you can call o of y this set and this is smaller o of x o y. So, I am talking about these sets let I of x o of x here and I of y o of y y b the set remember is a b the set it is not individual inputs and it is not the input to the switch it is input to the network. So, that is what it means to which I x I have to change the language will lead actually. So, in this case now important observation the 3 points which are important observation the first thing is your part a which is the conclusion that your set I x or o x and I y or o y are disjoint this set and this set will not have any overlap this set and this set will also not have any overlap overlap means there is nothing common between them they are disjoint sets which is obvious because there is always a unique path from each to each output. So, what if this is the path this can reach here and none of these inputs I should be able to reach through this path because there is uniqueness property path has to be unique. So, I cannot reach to these inputs through any other path except this. So, the first fundamental principle for Bunyan network itself ensures that this is true. So, sets will be disjoint and of course, the cardinality of the set will be how much you count how many number of the stages are there before this you are in a stage s k remember. So, how many stages are there before that 0 1 2 3 k minus 1 k stages are there. So, number of elements which will be there in this I x and I y both will be 2 raise power k obviously. So, I x is equal to I y will be 2 raise power k that is a first observation and similarly they should be after k how many stages are there you have till n minus 1. So, n minus 1 minus k those many stages are there. So, you must be expanding through that. So, cardinality for that will be 2 raise power n minus 1 minus k and most important thing that if you take a set I x union I y any input which is forming which is from this input from this particular set is a union of 2 sets any input in this if that you want to connect it to O x union O y this has to pass through this switch there is another option this has to pass through this switch. So, all members which are from this set if any one of them have to be connected to any member of this set the path goes through this particular switch that is again intuitive observation it is going to be true. And of course, the last one exactly how many paths will be passing through the switch this is going to be true here you can actually put you have 2 actually k will be because this is 0 1. So, 2 raise power 1 is 2. So, membership is 2 membership is 2. So, 0 1 2 which is n minus 1. So, 2 minus 1 is 1. So, again output memberships is 2 2. So, total number of elements which you can cover in I x is 2 raise power k I y is 2 raise power k. So, total number of input link input network links which you can reach is 2 raise power k plus 1. Obviously, total number of output links which you can reach from this switch is 2 raise power again multiply this by 2 n minus 1 minus k. So, when multiply by 2 it is plus 1. So, it is n minus k total number of possible paths you multiply 2 raise power n plus 1. So, every switch will have these many paths passing through it 2 raise power n plus 1 paths will be passing through every switch and total number of paths is 2 raise power n square because total number of input is 2 raise power n output 2 raise power n multiplied those are total number of possible paths which can be there. But from each switch this much will be there and of course, you can actually compute how many switches are there based on that you multiply by that that has to be equal to 2 raise power n square. At least you understand these many paths will be passing through a switch. So, how many switches I can reach from here input side I can reach this and I can reach this this is 2 raise power k this is 2 raise power k. So, 2 into 2 raise power k actually those many I can reach. So, which is nothing but 2 raise power k plus 1 on the output side if you take one link I will be able to reach 2 raise power n minus 1 k see look at the cardinality of the set. So, from the other link also I can go to 2 raise power n minus 1 minus k total number of output links which I can reach is multiply this by 2 which is like adding 1 in the exponent. So, it is 2 raise power n minus k. So, I know these many outputs I can reach through this switch these many inputs I can reach through this switch multiply these 2 those k will be the total paths passing through the switch. So, multiply these 2 these 2 raise power n plus 1 and this is independent of the stage remember it is independent of the stage and it is true it is going to be same for all switches it is going to be same for all switches actually while total number of possible paths which are existing in a switches 2 raise power n on this side multiplied by 2 raise power n on this side. So, it is 2 raise power 2 n total number of possible paths which can exist I think this this is there is a problem here this is not correct actually this is not correct this for all permutations all permutations are not permitted. So, it has to be different one it has to be it because this is 2 each possible thing now you take from here this is one path second. So, that 2 raise power n possible thing. So, total number of possible paths which are there from this input is how many 2 raise power n and total number of inputs are 2 raise power n. So, it has to be 2 raise power n into 2 raise power n. But all possible combinations may not be simultaneously may not be permitted that is a different question see that is a simultaneous permutation thing which you are looking at not the possibility of paths, but technically every input can be connected to every output, but the moment you set up a path some other paths will not be possible. So, we were looking at that when we are using factorial method we were actually considering that particular fact that is suppose there is no connection being set when I set this path to here. So, there has to be at least one path will which will get occupied and I can do it in n possible ways I can set up the connection, but possible paths I am talking about possible paths or connect the wires or possible ways in which paths can exist that is 2 raise power n square only. So, it is 2 raise power n square n 2 2 raise power 2 n. So, each switch actually the number of paths which can pass through see all of them cannot there can be exactly 2 paths which are permitted out of these possible paths which is passing through a switches only 2 raise power n plus 1, but only 2 paths will be permitted at any point of time depending on whether switches in cross or bar state. If it is in cross state then also 2 will be permitted in bar also 2 will be permitted remaining combinations will not be allowed, but possibility of all paths is 2 raise power n plus 1 and total number of switches here is 2 raise power n whole thing divide by 2 2 raise power n minus 1. So, 2 raise power n plus 1 multiplied by 2 raise power n minus 1 will give you this only 2 raise power n 2 n actually if you look at all things in the stage. So, all possible number of paths passing through a stage has to be equal to this which has to be constant important thing number of paths which a switch can pass through a switch is independent of a stage you take whichever switch in whichever stage it is same. So, this fact actually was not explicitly told earlier. So, this comes from this now before we go for this buffered system we actually have to make certain assumptions. So, without which we cannot hold. So, let me come to the assumptions now. This way 2 for banyan network is also banyan network. Yeah, it is true for banyan networks only thing banyan network you can you have to have you cannot have that uniform tag for reaching to an output for same output depending on it put you might require a different tag. Delta networks a common tag is good enough which defines the output port. So, what is the difference between exactly banyan network and delta network except tag? There is no other difference it is only tag which is the difference. Yeah, but then if you are using banyan what I did in banyan network I have always said in a stage the packet switch are coming in they have to come from the same output ID of the switches in the previous stage. So, in this switch for example, if you look at this I am getting 0 I am also getting a 0 this is a delta. So, this is also subclass of a banyan. If this condition you do not impose it is a banyan network. So, it is not a clause or anything there is exactly one unique path which is available. So, for 2 raise power n by 2 raise power n built using 2 by 2 you require n stages obviously for banyan network there will be exactly one path by design. So, first one is is a basic assumption I think which is obvious that each packet which is going to arrive at the network input link at here. So, we are not bothered about there is going to be a interface card or not. We are simply saying this is going to there is going to be a packet which will contain a label and a payload and label will identify to which output the packet has to go. So, that is the first and foremost assumption which is obvious. So, I am not writing it. So, I just simply say each packet at input consists of a label plus payload we call it also a tag usually interface processor will insert this tag. So, I am not bothered about the interface processor usually you look at IP packet header and then based on that decide what tag has to be inserted after looking at routing table. So, this being done this is an assumption here and of course, this is important condition of maximum loading exist. So, condition of maximum loading actually means at the input there will be a buffer only one packet can be stored here. So, at the input only at the input of the input links of the network not of the switches I am talking about. So, sometimes it is possible that buffers will not be occupied here, but at the input there is exactly one buffer one packet the movement this buffer becomes empty immediately a packet will be coming that is the maximum loading condition. So, traffic is always available at the input to be pushed into the switching matrix. Each switcher or the whole network? Not a switch there will be only one buffer for one buffer for each input port each input ports there are buffers inside also in buffer delta. So, we are saying 1 into 2 is power of n minus 1 buffers are there 2 is power n buffers at this point 2 is power n buffers here 2 is power n buffers here for a buffer delta situation if it is a unbuffered delta the earlier case then these buffers are not existing buffers are only here that is a maximum loading condition when p will be equal to 1 technically and of course, the output link if there is a packet it will be almost instantaneously taken out buffer will be emptied immediately ultimately packet is hopping it is being read one after another it is not a crossbar. So, at the moment it comes here it is immediately taken out there is no readout time readout time is 0. So, that is another assumption which is taken in fact interesting part is when the buffers are going to be here. So, you will find that sometimes buffers are here, but you cannot fill this buffer even if it is empty because these two guys made a conflict and they have both wanted to come here. So, one of them was pushed here other one was left in the buffer. So, one buffer emptied so packet came in, but no packet actually moved here in this buffer. So, here the probability that buffer will be occupied will is always equal to 1 as you move across the probability that buffer will be occupied will start reducing from 1 to a smaller value as stage is increased and ultimately if I know what is the buffer occupancy probability here that is a throughput performance under maximum loading condition that is what we are going to do ultimately. And of course, the third one is is a important thing that all input links are independent of each other and they independently choose an output port there is no correlation every packet coming in is independent. So, that is the important thing now this is something new at every switch when two packets come in you have to detect whether to which outgoing port it has to go by looking at the tag a digit in the tag has to be looked and once you have identified which outgoing port it has to be read out. So, usually there will be a buffer here it means there is going to be a one packet buffer and it has to be read out. So, if they both want to go here there is a selection time and then after that it will be passed it will be read out actually to the outgoing port it will go to the next buffer unbuffer delta technically means if there is a conflict one of them will be simply dropped. So, fresh packet is always allowed to come in that is what it means a buffer delta you will keep it there you will not allow other packet to come in. So, what happens is unbuffer delta technically means if you decide this packet has to go you simply transmit do not bother about whether the buffer ahead is empty or not empty because if there is a conflict one of them will anyway will be dropped at every stage this is what is going to happen. Buffer delta will not allow this it will keep the packet in the buffer it will not drop it. So, the packet from the previous stage cannot come here assumption is a random choice here it is random choice and remember the arrival rates here are also independent why they are independent because the input set i x and i y they are disjoint and I have assumed that all inputs here are independent of each other. So, take off the independent inputs to take one set take another set and if they are disjoint sets. So, these inputs also have to be independent of each other. So, this independence actually holds through all the all the stages because this independence of this i x and i y set is true for all switches in all stages is a consequence of that actually. Sir, in buffer delta sir we are not allowing the packet to be dropped in the intermediate stages. Yes. That means, the buffer will keep on filling if you move towards left and that means the packet will be dropped at input stage. I am using maximum loading condition there is some infinite buffer at the input I am not bothered. So, you are not bothered about that there is always a packet available when the buffer empties that is a that is a maximum loading condition. So, maximum loading condition may happen at your utilization factor which is when it is less than 1 it is possible, but inside you will have unit buffers in that case. So, delay now consists of this is basically independent arrivals at the input and equiprobable selection of output. The D part is there are two parts one is known as T select there are two times other one is known as T pass. So, this is the time when the selection is made after reading the tag and second time it is T pass that is one T slot actually and when the minimum delay will happen is when I am using unbuffered delta if there are two packets if there is a conflict one of them is permitted other one is dropped. So, how much time will take from input to output? So, this T select plus T pass multiplied by number of stages that is a minimum delay which a packet can suffer. So, this multiplied by n is min D or the minimum delay in this case. Sir, what is T pass actually? T pass is in a switch when the packets are there you have to first of all select to which outgoing port these have to go. That is T select. That is that time taken is T select and after that the packets will be passed or it dropped actually one of the two. So, that is the time in which the packet will be transmitted out is like store and forward is not circuit switching remember you have to receive the complete packet then you have to transmit after reception you do not start the transmission immediately you have to make some decision. So, on time actually scale if you put if I put a time scale like this. So, you receive a packet packet reception has completed here you will take some time to decide this is T select and then you will start transmitting the packet packet is finished. So, this is your T pass usually we will assume one of them to be 0 actually ultimately for doing the simulation thing, but real life this is the way it is. See most of this cannot be analyzed in with close form solutions it has to be done through simulation actually, but for certain cases certain kind of bounds can at least be estimated that is possible. So, in case of when the network is without buffering all packets will require will be delivered in this case or they will either be dropped actually one of the two things will happen either they will pass through in this time or they will be dropped they will be lost. Sir the pass system will be less than from one stage to other stage or the difference itself is which one the difference that is the propagation time that is going to be small actually. So, you can assume it to be horizontal line almost it is like a horizontal line it is like a horizontal line this is one first previous stage next stage. So, unbuffered this is what is going to happen, but for buffering this switch now can be modeled as a patrinette. So, patrinette model is will be of this kind again I think some of you have not read patrinette. So, I will try to explain what is it because each one of you have not done a course on communication networks earlier. So, patrinette is basically you have some kind of token buffers this is basically used for finite state machine depiction is for that thing. So, if there is a token here and I connect it to something called where the decision firing will take place. So, for example, there are two tokens. So, this firing can only take place when both tokens are available if there is only one token there is no firing possible actually and when firing happens all the tokens from on the input side will get consumed and they will fill up the tokens on all outgoing sites and we then put certain restrictions this what I will do. For example, then I can put a token here I can put a token here for example. So, if there are two tokens here there are no no tokens. So, condition is has been met for the firing and I will end up in getting two tokens here which then can be further connected I can also now put a time here is known a delayed firing actually I can put a time time patrinette we call it. So, when the condition is satisfied for firing after that there will be a delay and after that delay only the token will be generated on the outgoing token holding token holders. So, I can build up I think lot of machines in this fashion. So, I had done earlier I think one of the rattling control protocol was implemented this way in the previous semester. So, that is basically the fundamental, but now let us build up the switch because I am now doing backward propagation of the buffer status in a buffer delta if the buffer is busy I have to tell the previous stage that buffer is busy you cannot send any packet to me packet only can come if the buffer is empty. So, I have to build up the patrinette model for understanding this. So, actual implementation it means there is going to be a backward signal path also we shall give the status back if you do actual implementation of buffer delta otherwise you cannot do that actually. So, I will use two colors here one for the data and one for the control path. So, data will contain now two paths and this is known as input buffer there is nothing like an output buffer because output buffer for this switch is nothing, but the input buffer of the switch in the next stage input buffer in the next stage is nothing, but the output buffer for this and then of course if a packet comes in there is some time which it takes for making the selection which outgoing port it has to go. Once the packet is here in the buffer this will cause what we call a selection process. So, there will be a we call it T select will be the period for this. Now, this packet can go to up as well as can go to down both ways. So, there will be I have to now build up technically four things after this time T select depending on now the firing will depend on outcome of firing will depend on the bit which is controlling the routing if that bit says it has to go to bottom. So, this will the both of them. So, one of them will not fire because here I am doing a selection process. So, whatever is outgoing buffer which is connected outgoing token holder which is connected to this particular firing edge will not get a token because that will depend on the selection thing bit it is a bit controlled. So, that is not explicitly mentioned, but that is how actually it is. So, this in turn will then known as output request buffer. So, they are requesting the output if this has to go to here this will time this will actually be fired up this will not be that is decide by bit if the bit controlled is 0 it will come here if it is 1 it will come here if it is 0 it will go here it will 1 it will come here. So, this output request buffer there will be four of them. So, one of these will always be active not both similarly, one of these will be active not both of them or other way around know it is possible both of them can be active both of them can be on at any point of time. If there is only a conflict then only one of them will be. So, you will keep on holding and try next time if there is a conflict basically what happens this is 0 and this is 0 both of them will come here both of them should fire up I should actually hold up output request buffer I think both models are possible I will I will explain this this is one particular part. Now, this is the input buffer for the next switch in the next stage and usually I will have the status actually coming here we call it a successor buffer empty flag if this buffer is empty this will be set actually immediately. So, they are linked together there will be two such things we will use this color for so arrows are important here same thing this will be for the previous stage whatever you are seeing here is for the next stage switch similar thing also has to happen here there is a backward propagation of the control signal because of that. So, for example, if this guy selected the upper one it will pass the packet to the outgoing thing and this buffer will become empty actually in this case. So, I have to get back this will come here in fact, this should be I like it and of course, if this one passes through instead of this one. So, this token will get consumed and I will get I will set this particular flag in this case and then they will talk back further. So, backward propagation is there. So, this T select and only one of them should be there actually both of them cannot be there. So, that I think is taken care of by this conflict resolution T select. So, if both of them want to go to the top both of them will come here only one of them will be fired up other one cannot be. So, it will remain there as it is in that state and after T select this output request will be there and this will pass through when this condition is met and as this packet is going out this buffer status flag will be reset and this can then communicate back. So, new packet can come from again in this direction usually T passes a time in which the whole packet will be passed on to this buffer this will also include usually this signal time. Backward propagation signal time will can be included in that it does not matter every time when you are forwarding a packet signal is coming back. So, include both of them combining them does not make any impact. So, that is how it will be actually modeled as this is a pattern at model for the buffer delta system actually for a 2 by 2 if it is a n by n then it is of course, going to be tricky. Now, what you are going to analyze when you want to do a performance analysis. So, in any network one of the most important thing which you need to do is throughput performance. So, you have to analyze it under maximum loading condition ideally if it is possible you keep on changing your input arrival rate or input probability of getting a packet in a slot and then do the analysis. Second thing which is important is known as turn around time. So, this time is nothing but the time difference between two instance the first instance is when the packet is arriving at the input port or input link of the network not of the switch of the network and when it reaches to the output link of the network the gap between that is what is your turn around time. So, minimum turn around time will be min D or minimum delay. Similarly, maximum throughput will be what you will get with a buffer delta unbuffered delta actually. So, that is a benchmark which can be taken and based on that you can do a create a normalization of whatever exactly you will compute. So, I think I will close now and then we have to do now basically unbuffered delta analysis first. So, this actually I could have done it earlier also, but I am doing it now along with then cross bar and then of course, the analysis of this buffer delta system and then we can basically make the comparison of the three.