 Hello and welcome to this presentation which describes the effect of low power modes on GPDMA and LPDMA. To save power while the LPDMA or GPDMA executes programmed linked list transfers, the DMA controller hardware automatically manages its own clock gating and generates a clock request output signal to the RCC whenever the device is in run, sleep or stop mode. When used in low power modes, a CPU wake-up can be requested on completion of a specific channel transfer. Alternatively, the DMA can autonomously perform a next LLI transfer. This table summarizes the effect of low power modes on the GPDMA and LPDMA. Sleep mode has no effect on the DMA, which remains functional. An interrupt generated by the DMA controller can cause the exit from sleep mode. In stop zero and stop one, both the LPDMA and the GPDMA remain functional. Transfers can occur in low power background autonomous mode, including linked transfers. An interrupt generated by the DMA controller can cause the exit from stop zero and stop one modes. In stop two, the GPDMA is powered down, while the LPDMA remains fully functional. Transfers can occur in low power background autonomous mode within the smart run domain. In stop three and standby, the LPDMA and the GPDMA are powered down. They must be reinitialized when exiting these modes. In addition to this presentation, you can refer to the other presentations on the GPDMA and LPDMA, DMA overview, DMA transfers hardware and software views, DMA's circular buffering and double buffering, DMA link list, DMA 2D addressing, DMA register file, DMA error reporting, DMA input output LLI control. You can also refer to the presentation on power management.