 Hello, I'm Drew Festini. I'm sorry about the delay there. It seems like there are some issues I'm having to dial in from my phone. So I wanted to talk to you today about both of my favorite things, which are Linux and open source hardware, and how RISC-5 plays into that. I've made some changes to this slide, but they're not in this system, and I can't screen share right now. So if you go to that URL there, you'll see the latest ones, including what's coming up at ELC with RISC-5. So you can click on that link there and see it. But real quick, tomorrow, there's going to be a keynote from Krista Sanovich from Berkeley, who's the main person behind RISC-5. Cam Raj will also be talking about the software ecosystem tomorrow. And then on Thursday, Kalista Redman, who's the CEO of RISC-5 International, will be doing an Ask and Ask expert session. So if you click on that link for the PDF there for the slides, you'll see it all there because these are a little bit outdated. So a little bit about me. I designed Open Source Hardware Project for a PCB manufacturing service in the U.S. Also part of the Beagle Boat or Dog Foundation, which some of you may be familiar with, the Beagle Bone or the Pocket Beagle. Also part of the Open Source Hardware Association. And one of the things that might be interesting to people that are developing hardware is they have a certification program for Open Source Hardware that you can go through to sell certification program, and then you get a nice little logo with your serial number for your project. Also recently, after Invited Role back in February, joined the new RISC-5 Ambassador Program. So you can visit the RISC-5 website to find out more about that. So I am, let me proceed here. I'm actually from Chicago, but I moved to Berlin last year. So I've started a embedded Linux meetup here in Berlin. Found hiatus right now. But when we're able to, we'll start meeting again. So if there's anyone in Germany reach out and I can let you know when we might be doing another one. Or if people are interested, we can do a virtual one. Specific to RISC-5, there's a bunch of different meetups all around the world. Some of the active ones are Munich doing virtual ones. Bay Area is also doing virtual ones. So if you go to RISC-5.org slash locally, you can see all the different meetups happening there. So I mentioned, I don't want to talk about Linux on Open Source Hardware with RISC-5. So real quick, I wanted to define what Open Source Hardware means. So this is hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design. So this is the community-developed definition of Open Source Hardware that the Open Source Hardware Association or OSHVL hosts on our website. And I mostly work with electronics. Looks like we have some nasty formatting issues there. I created these slides with Open Office, but this is the PowerPoint export. So if you go back to the PDF link that I had earlier and it'll come up again, you can hit grab the PDF of the slides. So anyways, for electronics, which is mostly what I work with for Open Source Hardware, we'll be talking about the schematics, forward layout, in the original CAD file, so the editable source file like I use KeyCAN, for example. No, it doesn't have to be an Open Source tool. So it could be something like Altium, for example, and then also the bill and materials. So these are the files that you'd be sharing for Open Source Hardware. And the whole point here is to enable collaborative development on the hardware design. I talked more about Open Source Hardware and options for running Linux on Open Source Hardware. I did talk back in December at 3063, which is a big hacker conference here in Germany. Again, apologies for the formatting. It doesn't look like it worked so well. So there's the link to the PDF again if you want to pull up the PDF of the slides. So, RISC-5, is it the instruction set for everything? So when you write a C++ program, it gets compiled into instructions that the processor executes. So how does the compiler know what instructions the CPU understands? So this is defined by the instruction set architecture or the ISA. So it's a standard, a set of rules that define the task that the processor can perform. So the example that you've probably heard of is X86. So Intel AMD, which probably most of our laptops and desktops are running in most servers. And then ARM, which all of us have an ARM processor in our phones most likely. But both of these are proprietary and they need commercial licensing to use them. So RISC-5 is a free and open instruction set that came out of a team at UC Berkeley. So about 10 years ago, they were doing computer architecture research and they wanted an instruction set that they could use for doing that research. And they didn't want to deal with licensing of commercial ISA like Intel or ARM. So they decided to make a new clean room ISA based on all the things they've learned in the past. So the things that I don't have on this set of slides is sometimes I could question, why is it RISC-V as in RISC-5? So it's the fifth RISC instruction set to come out of Berkeley. The original one being back in the early 80s. And David Patterson from UC Berkeley is one of the people that was the co-creator of the original RISC back in the 80s. And he gives a great talk that goes into the kind of the historical context for RISC and RISC-5 and this talk called Instruction Sets Wants to Be Free. And then Krzysztof Anowicz, who's the professor that kind of jump-started the whole RISC-5 project. He gives the State of the Union once or twice a year. So this is the most recent one. But he is also speaking tomorrow morning giving a keynote. So definitely check that out. So what makes RISC-5 special? So one of the key things here is that it's simple in that it's a clean design that was based on all the insight that the team at Berkeley had over decades of designing instruction sets. An idea here is that it's modular. So it's something that can scale from a microcontroller all the way up to a supercomputer. And one of the ways it does this is by breaking things up into extensions. So let me jump ahead to the next slide. Let me jump ahead to one more. Oh, do I not have it in there? Oh, I apologize. The slides that I had are slightly different than this. So the base ISA is just a 32-bit integer ISA. So that's all the base RISC-5 ISA is. And you can go to the pilot program right now for that. And it'll run in 20 years on some fancy supercomputer that's RISC-5. So the idea here is we build up with extensions to the instruction set. So beyond that, there's like multiply, atomic, floating point. So these are different things that can be added on. For example, in the case of Linux, it requires some of those extensions for Linux to be able to run on RISC-5. And the key thing here is once those extensions are frozen in the communities, then they stay that way. So while there may be future extensions, instructions that was designed to allow you to both have extensions through community in the future and also have the area to have extensions that are made by the vendors that are designing the processors. And probably the most important thing with an instruction set is the software ecosystem. That's probably one of the main reasons why we're still using X86 right now. And the RISC-5 software ecosystem is pretty solid right now. Definitely the software to some degree is kind of jumped ahead of the hardware design right now. So we have support in GCC and Clang, G-Lib C, Linux kernel has support, Zephyr. So all the sort of things that you would expect to see on X86 or ARM are kind of there. And the other interesting thing is there's both open source implementations that you can use and there's also commercial implementation. So Rocket and Boom are some of the original RISC-5 designs that came out of Berkeley. Risky and Arian are designs that came out of the PULP team at ETH CERC. And both of those are being used to build upon both open source implementations and implementations that vendors are doing. Another really notable one is Western Digital has the Swerve Core, which is kind of meant for microcontroller sort of applications. Inside 5 is one of the startup sets creating a lot of cores that can be licensed for SOC's that companies might build. Ooh, that is quite small there. Another bit of formatting problem. But as I was saying, the point here is it for it to be an extensible instruction set that can go from a microcontroller to a supercomputer. And while it was created at Berkeley, the RISC-5 foundation now hosts the standard on RISC-5.org. It should actually be RISC-5 International now. So you'll notice a lot of references to RISC-5 foundation. A new organization called RISC-5 International is a Swiss-based organization to eliminate any of the political considerations because it used to be based in the U.S. There's over 400 members now. It keeps on growing. It gives the latest numbers on Thursday, but it includes companies and universities. And even you as an individual, you can join the RISC-5 International as an individual member. One of the ways I've stayed up on what's happening is the YouTube channel for the RISC-5 foundation has tons of talks. They have workshops and summits every year. So it's a great source of knowledge if you want to learn more. And then one of the really exciting things is companies like NVIDIA and Western Digital are planning to ship millions of devices with RISC-5. So like with Western Digital, they're replacing the little controller in all their different disk drives and storage products to have RISC-5-based microcontrollers. NVIDIA is also replacing some of the management and controller cores in their graphics cards with RISC-5. So one thing that this can do is help avoid the licensing fees for a core. But it's also above that. So with ARM, only a few companies have microarchitectural licenses like Qualcomm and Apple. So everyone else is just licensing a core from ARM. They don't have the freedom to change the microarchitecture if they want to. So RISC-5 allows you to leverage existing open-source implementations like Boom and Rocket from Berkeley or the designs from the PULP team ETH Zurich or SWIR from Western Digital. It allows you to change the microarchitecture to what best suits your product. So there's freedom there when it comes to the implementation of the instruction set as well. Let's see. Got to the next slide here. So before I do that, I wanted to make one point here that oftentimes people hear RISC-5 and they think it means open-source. So RISC-5 is just an instruction set specification. And that is open-source under Creative Commons so anyone can use it if they want to. But the implementations of RISC-5 are both open-source ones and they're both proprietary ones. So just because it says RISC-5 doesn't mean the actual design of the chip is all open-source. But in order for us to have open-source chips, which is something I'm very excited about, we need to have an open-source instruction set because we couldn't take the ARM instruction set or the Intel instruction set and design an open-source chip around that because those instruction sets are proprietary. So I mentioned industry. So one of the interesting organizations and one of the first to get going with RISC-5 was Lovic. So this is a not-for-profit organization based in the UK. It was started by some of the people behind Raspberry Pi. One of the board members was the main software developers, Andrew Bradbury. The idea here is they wanted to create an open-source system on chip that you could use for something like a smart phone or a single-board computer. So I think this is a really exciting goal. They're still working on it, but one of the things you may have heard from them more recently is they're working with Google on this security processor project called OpenPython that's using a RISC-5 course from ETH Zurich. I wrote an article about RISC-5 earlier this year in a magazine called Hack Space Magazine. So especially if you want to kind of introduce RISC-5 to someone who's too familiar with computer architecture, this might be a nice overview. So one of the first companies, one of the first startups that came out of this RISC-5 phenomenon was Sly-5. So it was founded by some of the people at Berkeley that designed the RISC-5 architecture. And a few years ago at ELC, they were one of the big sponsors and they had recently come out with this microcontroller called the AP-310. So actually that's not new. It's over on the smaller chip on the lower right-hand side there. So this was a 32-bit microcontroller. It was really exciting at the time. However, my main interest is Linux. So this is not quite good enough to run Linux. So let's talk about chips that can run Linux. RISC-5 chips that can run Linux. And there again is the link on that slide there because the formatting of these slides is not ideal and also there's some newer information in there. So if you want to grab that link there, you'll be able to see them. So the first one that was kind of a big excitement for everyone was back in 2018-55. They just launched this new Pentechor 64-bit RISC-5 SoC. And then they made a web board called the High-5 Unleashed. So this is really exciting. This is still probably the best board you can get if you want to run Linux on RISC-5. It's got four 64-bit cores. It's got a bunch of DVR memories. So it's a real nice board. The problem is High-5 is the IP company, a hardware design company that are actually in kind of making chips. So this was just kind of a proof of concept. So there was only, I think, maybe $100 made and they were $1,000. So it's both expensive and pretty limited, though it is still probably the best option for Linux on RISC-5. And one of the places you'll see it being used is people that are working on distros like Fedora and Davian. And you can even have a full desktop with RISC-5 here. So this is with the High-5 Unleashed board and also some pretty expensive FPGA cards and a PCI Express adapter. We can actually run a full GNOME desktop here. This is Fedora. And David, he's one of the people from High-5 that I've been talking to. He actually has one of these set up that he does work for Fedora. So that, a really expensive rear board is not super practical. So one of the other things that we can do is use QMU. Fedora has support for RISC-5 on it. And Aliser from Western Digital has done a really good job getting all that working. So you can actually, without any hardware, go run the Fedora RISC-5 port QMU on your computer or your server. And you can also run Davian. So Davian also has support as well. So we can use the High-5 board, which is pretty expensive and hard to get. We can use QMU on our Intel powerful laptop or desktop or server. But that's not super exciting, especially if you like embedded boards. So one of the things that's quite exciting right now is this board. So this is a board with the Kendraight K210 system match it. And this is from a company called Pipeed. And last year and also this year, some people including Damian Lamall at Western Digital have been hacking away to get this thing to run Linux. The catch here is that it only has 8 megabytes of SRAM. So if you look for the Pipeed Max bit, you can get that board. It's only $13. This is a dual core 64-bit RISC-5 processor running at 4 megahertz. And it has 8 megabytes of SRAM, which is a lot of SRAM for microcontrollers but not so much for Linux. The other unfortunate thing here is that it does have an MMU, but the MMU is an older spec, so it's not supported by Linux. So basically right now you can get a build root instance or you can get a build root fork from Damian, which will soon go upstream and you can run busybox. But right now we're kind of stuck. There needs to be more work to make it more useful. But you can test out Udude and OpenSDI and a bunch of other in the Linux kernel on this board. So for $13, it's definitely worth getting you to have interest in playing ROC Linux on RISC-5. And if you go to the PDF link, I have more updated slides there. As of Linux 5.8, when that comes out, it'll be fully supported. And Udude patches were just posted on the mailing list. So soon there should be support for this board and the Kendra processor in Udude. All there now in Linux. So it'll be interesting to see where this goes because the hardware is cheap. A lot of people will get their hands on it. And there's another little graphic of it there, a photo of it there running Linux. So you can see I have this is back in February. It was running Linux 5.6, which is the mainline at the time. And we're using six of the eight megabytes. So not a lot of room to do stuff, but still interesting to experiment with. And this is another version of the board that has a wireless Wi-Fi chip set on it as well. So you could potentially, through serial, connect to network services. But again, memory becomes a real issue with trying to do more than just running busy rocks. And Psyped has an image that you can download there if you don't want to build it yourself. So things that are coming up in 2020, well, it's already June. So I believe later this year, maybe September, August or September, Microchip's going to be coming out with the PolarFire SoC. So this is a FPGA chip with a hard-writ 5-core, and I believe it has four hard-writ 5-cores. So in the slides, I have a little more information to PDF that I've been mentioning. But if you type in Microchip PolarFire SoC, you can find that information about it. It's not out yet, but it's coming soon. And last week, Microchip just announced that they're going to be doing a dev board for it called the Icicle board. So that's going to be on CrowdSupply. You can go to CrowdSupply right now and look for the Icicle board, and you can type in your email address, and it'll let you know when that contains those lives. It's going to be less expensive than the 55 board, but maybe like half as expensive, which, depending on your frame of reference, might be very expensive because it's not going to be like the Icicle and Raspberry Pi price, but at least it's something that will be available. And the PolarFire SoC is going to be a real chip that's available to distribution. So we'll see other boards probably that use this, and those might be more cost-optimized. The other thing that's really exciting is back at the RISC-5 Summit in December, there was an announcement that the Open Harbor Group, which is another industry organization with companies like NXT and Silicon Labs, were working on open-source designs essentially to build an SoC. So the one that they announced here, let me go to the next slide, I think you have an image, is called the CoreV Chassis SoC. So this, you can think of it as one of the NXP from when we free-scaled IMX chips, but with the ARM core ripped out and RISC-5 core dropped in. So with this SoC, now it's just going to tape out in the second half of this year as a test chip, and then there will probably be a limited run of dev boards. But I think if it works out, we might see someone like NXP pull this out as an actual product. And if we can get to that point, then I think we can definitely start making more affordable dev boards like sub-$100 dev boards that have a real hard RISC-5 SoC, but still kind of waiting on that. So it has to be a little patient. But one thing we can do right now, we don't have to wait for the silicon chips to hit the market, is we can use FPGAs. So I don't have a lot of time here, but a great talk from a conference last year was from Megan Locks from Sci-Fi where she talks about combining both FPGAs and RISC-5s. So I'll just talk a little bit about the basics of FPGAs. So in FPGAs, there's a field program vocabulary, and you can think of it as a sea or an ocean of logic elements in a side bit chip that we can consider to be any sort of digital logic that we want it to be, including a processor. So we can have what's called a soft processor core loaded into the FPGA. One of the things that's been really exciting in the last few years is there's not open-source tool chains. So FPGA vendor tool chains were kind of notoriously bulky and not so nice to work with. So there's now a few FPGAs that work with open-source tools started with the last 40. But it's a bit too small for us to fit a RISC-5 core in it that can run Linux. But then the other thing that came along called Project Trellis which supports a more powerful FPGA called the ECP-5 from Lattice. And this one is actually big enough for us to be able to fit Linux into it, fit a RISC-5 processor that's capable of running Linux into it. Okay, it looks like people can actually hear me because I'm seeing some questions. It's not particularly interactive. It's like other conferences I've done so far virtually. So I see some interesting questions I'll get to at the end of the talk. So we've had support for Lattice, a couple of the Lattice parts. But the majority of the FPGA market is Xilinx or Altera Intel. Now the good news for Xilinx is for some of the Xilinx parts to series 7 there is soon going to be open-source support for that. It's already kind of there if you want to get into the repos and play around with it. But that means in the future we'll be able to use only free software tools to build a really capable like multi-core RISC-5 Linux system on Xilinx. I wrote another article that's kind of an overview of the FPGAs and the whole phenomenon of the open FPGA tool chain. So one of the projects I want to talk about kind of specifically here at the end is a little experiment that me and some other people did to get Linux running on a conference badge with RISC-5. So there's this really fun hardware hacking conference every year called the Hackaday Supercon. It happens in November in Los Angeles. And this year like is the trend now if you go to one of these hardware conferences you get a electronic kind of name badge to hack on. The one they had this year was in this Game Boy form back there. And it had the ECP-5 FPGA which is the one that's supported by open source tools and is big enough for us to fit a proper RISC-5 core that can run Linux. So this is us hacking on it in the alley here at the conference. Some of the people are actually here at ELC. Actually I think Michael Welling is actually giving a talk right now about STI. So Michael and Tim Ansel and Sean Cross and Jacob Creed and we all kind of hung together over the weekend to get Linux running on this. So the first approach was that it had 16 megabytes of SRAM built into it. However we weren't able to get that to work. However because it was a hardware hacking conference Jacob had ahead of time seen the design of the badge and designed this expansion board which gave us 32 megabytes of SD RAM. So this proved to be enough memory and also it was DRAM which makes it a little bit easier for Linux that we were able to get it to run. So real quick here the design of it if you can conceptualize. So remember the front there kind of looked like that Game Boy. And then on the back there's actually an expansion slot for hardware cartridges so to speak. So this is the DRAM cartridge that slides into the back there. And we were able to then get Linux running. But how did we do that? So real quick I was kind of soft core and it's kind of hard to conceptualize maybe. So you can think of this as a bird guide of all those little gates in the FPGA zoomed out. Like the one that we were using I think had 45,000 logic elements that we can program. So this is what it looks like when we've configured it to be a Linux capable RISC-5 core. And there's still space left. So that's the good news is we can still add new functionality, new peripherals if we wanted to. So I don't come from a chip design background. And I do some more board level hardware design. So not too familiar with all the different things the languages that are used for processor design. So we actually used Python in this project and that was really great. So if you're interested in how one might use Python to design hardware you can check out this talk here from Tim where he talks about a really interesting project where they built this open source hardware to be able to record open source conferences. Maybe this one someday. And one of the reasons for that is that Tim thinks that Python's a really powerful language. And using this framework called Nijen we can actually generate what is normally used for chip design to verilog very easily. Here's just a little snippet of what it looks like which if you've done any verilogs or VHDL you might see that kind of translates there to the Python syntax. I'm not sure how if you will see this but you can go to the URL there if it's too small. But this is a side-by-side comparison of what Nijen looks like. So Nijen is a essentially a hardware description language that's written in Python. So instead of using verilogs or VHDL which are the traditional hardware description language that people in industry will use to design processors, we can do it in Python. And you can see here the comparison of I think it's a D flipflop which is a very basic digital circuit both done in Python with that Nijen framework and then done in the traditional verilog. So on Python Nijen we add in LIDAC. So LIDAC is a framework that gives us a bunch of different IP cores which you can think of as peripherals that we need for building a system on chip in the FPGA. So you can check it out on GitHub there. Enjoy Digital is his name is Florence and he's one of the main people behind this project. So just to go over it again we have this Nijen framework that allows us to do what we would normally do is verilog or VHDL in Python instead. And then on top of that we have LIDAC which is this framework that allows us to build these different IP modules in Nijen and then glue them all together into an FOSC which is a system on chip which is normally what you're used to in one of the single board computers or a phone. I don't know if you can see that there but it's a little bit of an ASCII diagram there of how this comes together. So we have our open source FPGA tool chain. We have that Nijen framework for Python which in Python. And then LIDAC gives this different functionality like Ethernet controller, SOTA controller, DRAM controller, USD, a bunch of different peripherals. In this project we just used the DRAM controller and the serial controller. Now beyond that, okay, so we have these different hardware IP that we can string together but how do we actually get Linux on it? We need a processor. So we use the VexRiskV which is a nice open source 32-bit RIS5 implementation and this processor is actually capable of running Linux. So there's a project that's called Linux on LIDAC's VexRisk that glues this all together for us. So if you have one of these boards if you go to the URL there it'll list a bunch of different FPGA development boards. If you have one of those boards you can just clone this repo run through the builds and you'll have Linux booting on your FPGA board on this RIS5 core. So that is quite new for me to get one of those FPGA boards and I'll go over a few options in a moment. Here's what it looks like with Linux booting on the soft RIS5 core that's inside the ECC5 FPGA connected through a serial port to my computer if you didn't have to display there working at the time. So we have a little serial port and we can interact with the busybox instance that's running on that soft core inside the Linux. So this is all done with free software. No proprietary tool changes involved. So when we got back from the conference it would be good to add back the support that we have together to the Linux on Linux project. This is probably not particularly useful to people that were not at the conference but if you want to look at what does it look like to add a new board to Linux on Linux this is maybe a good reference point and I don't know if you'll be able to see that there but I'll give you an idea of what the syntax looks like. So this is a file where we're describing the pins that we have on our FPGA and how they connect to the different ports on the badge. And this is normally something that's done in Verilog in this case it's done in Python thanks to me, Jen. And one of the things that I thought was particularly useful since I'm not super proficient with Verilog was I'm able to look at this and get a much better feel for what's happening to nature of Python to be able to just import these modules and just extend and add what we need for our specific board. For example this is how it loads the upstream which is essentially the binary you could think of that you would have from a programming tool chain we load it onto the FPGA so we just load it like copy a similar board and then just tweak it for the specifics for our board. So another good example of that nice extensibility that Python gives us is we have this SD RAM chip and no one had used it before so all we had to do was take light DRAM which is the LightX DRAM controller and just extend it with the specifics for our DRAM chip which we got from the data sheet. So we didn't have to go right around DRAM controller in Verilog or deal with a bunch of Verilog to understand we just can do it all in a nice object nature of Python. And one of the points Tim will make is there's a lot more software engineers and hardware engineers and one way to get more people into chip design especially with the great open source tools that are coming out now is by making it more easier for software engineers to get into the ways that hardware is developed so Python is a nice way of doing that so you don't have to learn a new language like Verilog or VHDL. Oh and then the other nice thing which I encourage you if you're interested in FPGAs and Linux check out Linux on LightX because enjoy digital whose form is super responsive so what we had Linux booting it was taking 300 seconds which is not very fun. And I posted a issue and within a few hours he was like oh here's a fix and it now booted in 30 seconds. This was by loading it over serial it boots faster now because we can use it from the flash but anyways open up an issue within a few hours got a 10x performance improvement so I thought that was pretty awesome. And another example just to underscore why I think Legion and LightX using Python are really nice so this is a part of the change that for it made to make it go faster. I'm not super familiar with this design but I can kind of see here from the diff that he made the L2 cache wider. And for me understanding Python it was much easier than having to go through some Verilog so just kind of my opinion I think Python put interesting for doing hardware design. And we finally did get the LCD working in the end. Greg Davil is an awesome hardware hacker in Australia has it running in this tweet. So you don't have this badge if you weren't at the conference but if you want to play around with stuff what boards can you get? So these would be boards with that ECP5 FPBA from Lattice which is supported by the open source tool chain and it's big enough to have a Linux capable core. So one board is the Radiona ULX 3S and that is from a hacker space in Croatia called Radiona and they did a crowdfunding campaign on crowd supply a few months ago so you can check that out if you're interested in that board and then another board that I quite like a lot is the orange crowd from Greg. So this has 128 megabytes of DDR RAM so that's quite enough for us to do some interesting things with Linux. It also has an SD card and support is just landed recently for us to be able to boot Linux from the SD card. So we can actually have a proper like RudaFS and we have plenty of RAM to run in Linux so I think it will be quite interesting. It's already running, you can check it out. And he also did a campaign on Gluthcats which is a different website. Matt just finished I think he'll be giving more information soon on how to purchase it now that's ended but if you go to the link in the slide there it takes you to the GitHub that's a good place to file for more information and if you're just giving to FPGAs one that's big enough to run a Linux-capable core might not be the best route so this little board here is called the FOMU and it's a great way to get started with FPGAs. There's a nice self-paced tutorial that takes you through different ways of programming FPGA including Litex. So it's a good way to get some experience before you jump into something like Linux on Litex with a bigger FPGA. It also sits inside your USB port which is kind of fun so you can do it wherever you go and if you don't have any hardware one of the really nice pieces of software is called Renode for Matt and Micro and it's an open source project that's essentially a batteries included emulator for embedded boards. So you can go to renode.io and you'll see on there a bunch of different dev boards. There's more than this but for example that sci-fi on leech board is a really expensive board that's pretty rare. It's in there. Several FPGA boards are in there as well so what this does is it allows us to use our laptop or desktop or even server and we can run this emulator. It's a fork of QMU but it hasn't had a lot of stuff added to it. So here is a little photo of me on my laptop running renode and it's emulating that sci-fi on leech board. It's that really expensive board. I have the same environment on my laptop here and because it's running like on a modern Core i7 it's actually pretty responsive so it's a really nice way of getting involved with RISC-5 if you don't have any hardware at all. You can also use QMU but if you want to kind of emulate specific boards renode is a really nice way to do that. It looks like I have come to the end. Please do hit that URL because the slides that are on github are formatted properly and also have a lot more information. One of the things that has not been here is last week at the RISC-5 Munich Meetup we are in Topol. I'll give a really interesting talk about how they get involved in the RISC-5 Linux kernel development and he talks about some of the to-dos that are still needed. It makes the point that RISC-5 is pretty new and it's relatively simple compared to the other architectures that are supported in Linux so if you want to dig in and start working and get some experience with kernel development RISC-5 is a good place to look. It's simple enough that you can maybe fit it on to your head unlike ARM or Intel. I think we do have some questions here. Real quick they are in the slides but not these PowerPoint slides but the PDF. A really great book is called the RISC-5 Reader. If you want to have a short 100 page book that gives you the speed with what RISC-5 is and the different extensions, that's a great resource. The RISC-5 Reader you'll find it on Amazon. We have some questions here. I saw Robert they say think maybe I had a title so going back to the Microchip Polar Fire Associate which is that PGA with the hard RISC-5 cores. It's similar to the Xilin sync. You can think of it that way. Definitely get in touch with Microchip if you're interested but I believe that should be coming Q3 this year both as the chip and then also the Icicle dev board that you can try to get started. Hello and don't forget Kam Raj talked tomorrow about the ecosystem for RISC-5. He's asking when can we expect Beaglebone RPI range RISC-5 Actually maybe I should be doing something with these questions. Should I be answering them? So the impediments there to having a sub $100 board is a SOC that's affordable. Thanks for a lot of the companies are IP only companies like Sci-Fi so they just basically make test chips. Other companies like Western Digital are just doing them for internal use. So the open hardware group if that turns into an NXP product I think that could definitely be something that opens the chapters that could be something that we could do. The Polar Fire Associate I think still might be too expensive because I have so I'm actually pretty excited to see what Kendra does. So if Kendra was to come out with one that had an external memory bus then we could have a proper system. So right now basically we're winning an SEC that basically sold as a real product that we can buy and build boards around. I do think we'll see that in 2021 that we'll see $100 or less boards that can run for risk 5 on a hard SOC. Let me see here I'm not quite sure I'm supposed to be typing in text answers but I'll just answer these with audio. So someone asked what is your I guess I'm supposed to be typing. Okay the engineer says I can just talk verbally so before time runs out I will do that. By the way in the Slack we now have one for risk 5. So if you look in the Slack it's like number 2 dash risk 5 so we can do more questions and answers in there as well. And don't forget there's keynote tomorrow and then Kendra. What is your estimate of the effort required to develop a low power risk 5 core? So check out ETH Zurich they have the PULP team there which is parallel ultra low power. So they've been doing a lot of work on energy efficient risk 5 cores and all the work that they've used open source. So that's an interesting thing to check out. In terms of companies I think there's a company called Greenways that's doing like low power sensor microcontrollers with risk 5. So definitely check out ETH Zurich PULP. Any idea if risk 5 can be done in the team to be on board? So I believe that's the balance part. Definitely if you check the Linux on Lydex repo which I showed earlier there's a bunch of boards in there solo of them are Xilinx so if it's not listed there it's probably just a matter of getting all the specifics of the boards in there but the Xilinx part should be supported. They're supported with the Xilinx toolchain which is a giant thing. It's like 40 gigabytes but the simple flow project is very close to having some of those working with the open source toolchain so you don't necessarily have to use the Xilinx proprietary toolchain if you wait a little bit. By the way with the pink Z1 board that you mentioned there I would say go ahead and open up an issue on the Linux on Lydex with repo and I'm sure enjoy visual which is a foreign will probably respond. Maybe that is all the questions all the rest of them are wondering where I was because I was having issues with doing it over web audio and I had to dial in so hopefully that wasn't too painful and please do check this slide. Are there more questions? There's a second page. It's just about me not being able to get it working. Yeah so if there's any more questions happy to take them here I think we're over the time anyway so thank you for attending hopefully I'll see you in the Slack this is not very interactive unfortunately because they're virtual but I definitely would love to have more interactive Q&A over in the Slack. I I guess this is done can the engineer hear me?