 Welcome to ST Microelectronics tutorial on power MOSFET parameters. In this session, we will review the dynamic data sheet parameters related to energy storage in the MOSFET. Here we have a table of dynamic parameters, meaning that they play a major role in understanding the MOSFET switching behavior. Next we come across the intrinsic capacitances. They are defined by sums of capacitances between MOSFET terminals as shown here. C-I-S-S or the input capacitance is the sum of the gate-to-drain and gate-to-source capacitances. C-O-S-S or the output capacitance is the sum of drain-to-source and gate-to-drain capacitances. And finally, C-R-S-S or reverse transfer capacitance is simply another name for the gate-to-drain capacitance alone. These capacitances must be specified under strict test conditions as they can vary dramatically. The capacitance versus drain voltage chart shown here is found near the rear of most power MOSFET data sheets to help the designer understand the dynamics of these parameters. Not all vendors will specify their dynamic capacitances under the same VDS, so be careful when comparing. Finally, it's worth noting that these parameters have very little variation over temperature. Let's examine how these capacitances relate to the switching performance of the power MOSFET. Here is shown a typical test setup and the ideal voltage and current waveforms of VDS, VGS and ID as the device transitions from off to on. We'll break down the transition into six switching states as seen here. Please note that we are not taking into consideration the effect of body-dialed recovery in this simplified example. In step one, there is no gate voltage applied and the device is off. The drain voltage is blocked from the source terminal and the device is not conducting a current. The switching transition begins at step two when a voltage is applied to the gate. The CISS is charged up to the threshold voltage VTH. Drain voltage is still blocked equal to our test setup VDD. Drain current nudges slightly above zero as the device reaches its threshold of conducting. Step three is the over threshold state where drain current really begins to flow. The drain voltage, however, still remains at VDD as CISS continues to charge. The current through the device is related to the transconductance or GFS as we are now operating in the linear region. Current will build up to its steady state peak while the gate voltage will be determined by this current times the transconductance. The VGS plateau is reached in step four. There is now a large effective increase in the input capacitance due to the Miller effect and VGS remains flat. The CRSS now begins to discharge allowing for the drain voltage to fall. The drain current remains constant and its peak steady state value. Step five shows the nonlinear drop of the drain voltage due to the CRSS effective dependence on VDS. Note that the energy discharging from COSS is dissipated internal to the MOSFET and is a source of switching loss. Upon discharge of the output capacitance we reach the ohmic state step six. Now the device is no longer blocking any drain voltage and the full drain current is conducting. The Miller effect disappears and the VGS increases to the value of voltage charging the input capacitance. Finally switching is complete. The transition from zero current conduction to zero voltage blocking is demonstrated here by the arrows on the curves plotted against VDS and IDS. We've seen that the charging of the intrinsic capacitances are how the MOSFET is controlled so we can consider it as a charge controlled device. Injecting and extracting charge to the gate is the fundamental method of turning it on and off. Switching performance is related to this capability of the gate driver. We'll now look specifically at gate charge and how it relates to the VGS. This is graphed in every MOSFET data sheet as shown here. Once again we see that the parameters must be specified under specific test conditions for gate voltage, test output voltage and drain current. The gate to source charge or QGS is the charge required to raise the gate source voltage from zero to the plateau voltage where the Miller effect begins. The gate to drain charge or QGD specifies the charge needed to move beyond the linear region of operation and into the ohmic state where drain voltage is no longer blocked. The total gate charge QG or QGTOTE determines the charge needed to raise the gate voltage from zero to typically the recommended driving voltage of the MOSFET, in this case 10 volts. QG is also often used as a benchmark for switching performance between devices, but again be wary of the test conditions under which it is specified. The last dynamic parameters we will discuss relate to the performance of the intrinsic body diode of a power MOSFET. In many applications such as soft switching power supplies, the effect of reverse recovery can be a significant source of loss. Again pay attention to the test conditions of the specifications. Reverse recovery occurs when the body diode transitions from conducting a forward current to blocking a reverse voltage. The diagram here depicts the behavior of the current through the diode during this transition. The recovery happens in two phases, A and B. During the A phase, the diode current has dropped to zero and the diode is now blocking voltage. However, the current conduction will overshoot into the opposite direction to a peak recovery current value specified as IRRM. The current then begins to fall in value back to zero during phase B. The cumulative time it takes for this recovery is specified as the TRR. The total recovery charge that must be dissipated is proportional to the TRR times the IRRM. This phenomena is highly temperature dependent and is often specified at both 25 degrees C and maximum operating junction temperature. That concludes our tutorial on dynamic MOSFET parameters. Thank you for listening. For more information, please go to www.st.com.