 Welcome to the session on JK flip-flop. In sequential logic circuit, at the end of the session, students will be able to explain the operations of JK flip-flop. Let us see what is JK flip-flop, a JK flip-flop has two inputs similar to that of SR flip-flop. We can say JK flip-flop is a refinement of SR flip-flop, JK means Jack and Kilby or Texas Instrument Engineer who invented this IC. The uncertainty in the state of an SR flip-flop when S equals to R equals to 1 can be eliminated by converting it into a JK flip-flop. The data inputs are J and K which are ended with Q bar and Q respectively. To obtain S and R inputs that is S equals to J into Q complement, R equals to K into Q. The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equals to logic level 1. The flip-flop is constructed in such a way that the output Q is ended with K and clock pulse. This arrangement is made so that the flip-flop is cleared during a clock pulse. Only if Q was previously 1 similarly Q bar is ended with J and clock pulse so that the flip-flop is cleared during the clock pulse only if Q complement was previously 1. The table is useful during the analysis of sequential circuits when the values of flip-flop inputs are known and we want to find the value of flip-flop output Q when both J and K are 0 the clock pulse has no effect on the output and the output of the flip-flop is the same as its previous value. This is because when both the J and K are 0 the output of their respective N gate becomes 0. When J equals to 0, K equals to 1 the output of the N gate is corresponding to J becomes 0 therefore Q becomes 0 this condition will reset the flip-flop. This represents the reset state of flip-flop when J equals to 1 K equals to 0 in this case the N gate corresponds to K becomes 1 therefore Q becomes 1 this condition will be set the flip-flop this represents the set state of flip-flop when J equals to K equals to 1 this will cause the output to complement again and again this complement operation continues until the clock pulse goes back to 0 since this condition is undesirable. We have to find a way to eliminate this condition the undesirable behavior can be eliminated by edge triggering of J K flip-flop or by using master slave J K flip-flop. The truth table for the J K flip-flop is the same as that of the SR flip-flop when J and K are replaced by S and R respectively except for the indeterminate case. Now when J equals to K equals to 1 and Q equals to 1 after a time interval delta t the output will change back to Q equals to 1 at the end of the clock pulse the value of Q is uncertain this situation is referred to as the race around condition. Therefore J K flip-flop if J equals to K equals to 1 for a long period of time then Q output will toggle as long as clock is high which makes the output of the flip-flop unstable or uncertain this problem is happens in race around condition in J K flip-flop this problem can be avoided by ensuring that the clock input is at logic 1 only for a very short time if the clock on or high time is less than the propagation delay of the flip-flop then racing can be avoided. So this race around condition can be avoided if T P should be less than delta t and it should be less than total time t a more practical way to avoid the problem is to use the master slave configuration. So in the flip-flop if it is made to toggle over one clock period then racing can be avoided this introduced the concept of master slave flip-flop. So a question what does the circle on the clock input of J K flip-flop mean you have the four options level enabled positive S trigger, negative S trigger, level trigger so please note your answer. So your answer is see the circle on the clock input of a J K flip-flop mean negative S trigger whereas the absence of triangle symbol implies that the flip-flop is level triggered. A master slave flip-flop is a system of two SR flip-flops one being designed as a master and the other is the slave. The master slave flip-flop is basically a combination of two J K flip-flops connected together in a series configuration out of these one act as a master and other as a slave. The output from the master flip-flop is connected to the two inputs of the slave flip-flop whose output is feedback to input of the master flip-flop. In addition to these two flip-flops the circuit also include an inverter. The inverter is connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other words if C P equals to 0 for a master flip-flop then C P equals to 1 for a slave flip-flop. For the working of MS J K flip-flop if J equals to 0 and K equals to 1 the master flip-flop q complement output of the master goes to the K input of the slave and the clock forces the slave to reset. Thus the slave copies the master. If J equals to 1 and K equals to 0, q output of the master goes to the J input of the slave and the negative transition of the clock sets the slave which copy the master. If J equals to 1 and K equals to 1 it toggles on the positive transition of the clock and thus the slave toggles on the negative transition of the clock. If J equals to 0 and K equals to 0 the flip-flop is disabled and q remains unchanged. This makes the master slave J K flip-flop a synchronous device as it only passes data with the timing of the clock signal. Now applications of J K flip-flop counters, frequency dividers, shift resistors, storage resistors. If J and K data inputs are different then the output q takes the values of J at the next clock edge. If J and K are both low then no change occurs. If J and K are both high at the clock edge then the output will toggle from one stage to the other and these are my references. Thank you.