 So, just a short introduction, my name is Rahim, so I've been working for ASTAR for quite some time, and as it can be, if you want to see my profile, you can go on LinkedIn, and I'll see you on Twitter. Okay, so to put things in context, I'd like to look or to refresh your mind, you remember we saw it for dealing with FPGA development cycle. So, again we've got this paper from which I extracted this figure on the right. So, a typical FPGA development consists of the software aspect and then the hardware aspect we are dealing with, really component, electronic components. From the software aspect we have this requirements specification, everywhere that we do we have always verification and checking if things are designed the way we want, and we have the design, implementation and integration valuation. And really when you look at the software aspect of the tool, we look into the design specification. RTL is this registered transfer level, which is basically designing circuit logic. So, using the hardware description, I think the choice mentioned is earlier using languages like very long, long years ago. Then we go into transmission to the gateway design, this is the synthesis part. Before that we can always look at the behavior simulation, we want to assess all the timings, all the clocks and all the signals. And then once we pass the gateway design, we go into the layout, which is this place and bit aspect, and this is really choosing which FPGA we want to implement the thing into. And then afterwards we have an FPGA bit stream, which is the file that is sent to the FPGA to program the component. So, I think, not to repeat too much, but the FPGA is shown on the left, so we have really a field programmable gate array. So, we have an array of, suppose it's gates, and within we have those logic blocks, a lot of logic that you can use, registers, etc. And the problem with the FPGA is that you have all these buses, the interconnect, that allow you to customize with the functionality within the FPGA. And then outside you have this IO group blocks, so some low-end FPGA have like really IO normal input output signals, but the IN can have perceived more advanced blocks from which you can do some new FPGA, etc. communication, high-speed blocks. And then the more the FPGA evolved over time, they added more block ram, DSP slides, etc. So, processing blocks from which you can exploit and basically increase the complexity of the design. So, today we are really, really interested in the synthesis and the place and route from the development software aspect. But we have to remember that this is an electric component that we programmed with, and it seems to be the kind of liaison between the hardware and software to get good. So, I put the paper here. This paper actually refers to some IEC standard, so it's always interesting to see that for some aspects. You also have those specifications. So, not all of the commercial tools for FPGA development are mostly free now, at least for Xilinx, which is now brought over by AMD. The tool is this one called Vivago, for Altera, which has been brought by Intel, and the tool is called Quartus. A lot of tools like this are the tools for human development. And then Gulen is the new quite recent FPGA from China, quite a small model. At this point, there's some, I mean, I'm really a Xilinx guy, so actually I really rarely use both of the FPGA. There's a lot of choice for us to choose, to use one. And then on the left, you can see the simulation, RTL analysis, and then this synthesis implementation, and then bitstream generation. So these are the standard tasks that those tools will do for you in the middle of the year, according to that problem. So FPGA programming is quite niche. It's not something that is really as popular as C++, and sometimes in here, it's more electronic people moving into the programmable aspects, and then we have the FPGA. FPGA is usually the transition between some accelerator that you want to make a nasty chip, and then you actually exploit the FPGA aspects to some test. So the focus of this talk is really new system, next PNR, in terms of the part of it earlier. So for me as a scientist, we really come up from that early paper, 2018-2019, where they introduced this free and open software architecture. Really architecting it through, because they want to really be as generic as possible, and then they want to have this framework, to have a flow for the placement of this simulation. And the early stage was really for that paper, using lattice and small size FPGAs, the ICE 40, and the Lattice 65. So these are the low end, I would call low end, not as low quality, but really small resources, and we hobby price the FPGAs. And really this paper, I think we did a lot of hype, and really started with the open source framework for FPG. So I actually made available the PDF, it's on my GitHub somewhere, so you can click and go through these things. Simply, your CIS can really be compiled from source, so instead of having a tool that you download from Dylings, it's a 50 gig with massive files that you install, and half of the thing you install is sometimes not used, because they make you download like some intrastale or whatever, private, or you never use. Your CIS and the PNR part is really smaller, and you really, from the field of open source, have access to everything and see what they are doing, contribute, etc. And then it supports mainly very long and system PNR, but there is some initial attempt to do PFTL, and actually to this your CIS, they have also some little project, additional project that cannot specialize, so called the famous one is Trellis, which is used for the Lattice 65 FPGAs. And then maybe also your top later on, dealing with the RISC file, so you also have the Pico RB32 RISC processor, so everybody kind of heard about the RISC file, the inpution set. 32 is for the 32 bit, and the N is for the distribution division, and the C is for the compression structure. The RB32, imagine the other processor that you basically know and can change, remove or add a specific instruction by yourself, and not like the PNR4 or whatever, you really have access to all the source to build, modify, and they really need to look at aspects of security, so this is really useful for a lot of the RISC file development. So one of the additional project that is from this F4 PGA, is this project, especially for myself dealing with many science like PGS, this is a project I tried to document, the bit stream of those FPGAs. If you use your own, and you have a certain design, you create this bit stream, that bit stream is really the kind of natural property of Xilin, and first you sort of try to reverse engineer that bit stream to identify what you modify in the design. So for this, you can actually help to contribute. If you have a specific FPGA that they don't have in the catalog at the moment, you can basically use those mini-tests, experiment and fuzzers, which basically help to generate small designs and have them to study the bit stream, and ultimately this basically brings you to this project, to generate properly the bit stream. So at the beginning, you have this aspect of you are reversing, reversing, generating the bit stream. Personally, I still use the bit stream as a tool, but ultimately maybe some of these big companies will be doing more and more open source, and they will see the appeal of having a community. Of course, for Xilin, they have such a large variety of FPGAs that you have to focus on specific ones. So the most popular FPGAs are the ones at the moment. So the next tool is the next PNR. So PNR is the place I moved to. So you have the same. You have a different project. I store trellis outside at the lab, and then for the Intel site on 5, there's some experimental tools. So you have a part of groups of people who are specifically focused on both. So you can go, I think for the technical presentation, there's no point going into too much, like even demoing because it's too short. But later on, you can basically try to look into those FPGAs. The Corwin and Lattice, they are quite small FPGAs, where Xilin and maybe Intel, AMD and Intel now, they can be some quite big FPGAs. So to introduce quickly, also we have an FPGA community Singapore. So we have a Facebook group, and recently we've had the Hyperware XRPGA day. So everybody is welcome to join those days where we introduce FPGA on works. If you want to explain to a certain person, you can come and they will talk about applications. And over the summer, this summer, we can try to have a session specifically on those users who try to have really proper tutorials. Additionally, to finish, we also have a session called Paper We Love, I think with teammate at the back and organizing this in the class. So for the FPGA aspect, we have those two papers, complete open-source design flow for grouping. I will have this FPGA, but we can still buy one from AliExpress, or whatever source that has this. And then we can go through the kind of steps. When you read the paper, they explain what we suspect to do some testing. So this session is not due to go too deep, but it's due to use this new movement, quite driven by the RISC-5 actually, from my point of view, that with the open-source, from which you can learn, and from which you can also develop specific aspects to optimize, to improve aspects, in terms of security, in terms of other things. So yeah, I think N was presented to me earlier. So if you have any questions, I'd be grateful, I don't want to spend too much time because I've already used one a little bit. Yeah. Thank you very much. Thank you very much. Are there any questions? We have one minute left. Anybody? All right, no questions? Oh, one question, there you go. If someone wants to get started with those tools, what is the best way to get started? So you think, you say, do they have to provide them consoles, or how that's going to be? Yeah, usually if you beat up and you make, you clone the archive, and then there's a whole sequence of make, etc. And then afterwards when you have those tools, they go through some very basic examples. And that's why there's a couple of videos on YouTube that are now discovered, and actually they go through some examples. So I will add this at another slide. To be honest, compared to the normal VivaDo, if you're used to those that flow programming, this one is more of a Linux part when you script a lot, but you cannot automate a lot of things. Thank you.