 So, in the we have seen in the last lecture we saw about we learned how to read the design into design compiler we studied some coding techniques we saw actually. So, let us just look a spend a few minutes at this look up. So, we have seen that we popular that we saw what link target in the last lecture we saw how to read the web log into design compiler we saw how to hold R2L course into this. Now, in this lecture we will look at how to define the design environment. Before we come to the most important part of setting the design environment we should see how the environment is designed and what environment we synthesize the design. So, this presentation is divided into two parts the first part we will see how to partition a design, what is the partition design and the second part we will see the how to define what are what are what is meant by design environment and how do we set the design environment. Let us first look at the two terminologies specific to design compiler or I will say now they are common to all these materials we will see what how what these terminologies are and how they are used in type of tool. So, first let us look at design what is what do we mean by design in the context of an individual design. So, design is a circuit distribution that performs logical functions. So, for example, we are designing an input CPU. So, that is a design course for synthesis that that is a design course in relation and so on. The designs are described in various formats such as DSD or well lost logic levels designs are presented with all sets of Boudin equation, gate level design. So, a design let us say an 8 bit CPU, 8 bit microprocessor it can be represented in a well lost LPM after synthesis we will get the gate level net mean. So, it can also be represented in this format as part of it as a electro connected file. So, a design is a CPU, but the representation depends on your usage. If you want to use it for RTL simulation you have to use the well locked design, if you want to use it for timing analysis you have to use a net mean format. Designs can existently compile in different day of another or they can be subdesigned in a larger design by that definition designs are either flat or hierarchical. Flat designs do not contain any subdesign they have only one structural design. However, they may contain laboratory cells. For example, a simple design like a full adder or a half adder will contain list of laboratory cells essentially for example, you can contain hand gate or gate, but inside it does not contain any other design. So, that is a flat design. On the other hand all complex designs are more or less hierarchical. They contain they contain one or more designs of a subdesign each subdesign can further contain subdesign. So, it is a kind of a design hierarchical at this level. Usually RTL is in that format although net list can be flat or can be hierarchical we will see many examples during this course. Let us come to design objects. So, here is one example. So, there is a design called top which has force a b input force a b 3 b and top output force out which is a bus to big bus. So, when you talk in terms of parameters this top level description is called a design. The force the input output force or simply called force, but the force of the designs which are instantiated inside the top level design are called pins. So, the difference between pin and force is that, force are pins of the top level and all the force of subdesign are called pins. So, please be very clear about the difference between force and pins. Force are always when you talk about when you say something is a force you mean either it is an input or an output at the top level. A pin is usually a pin is associated with something within inside the top level not at the bottom level. So, here there are two designs two subdesign and two subdesign which we also we can also also call that is encoder and LH5. U 1 is an instance of encoder, U 4 is an instance of that LH5, U 2 is an instance of INV, U 3 again is an instance of INV. So, designs are top encoder and LH5 please note we are not calling an inverter a design. Why because we differentiate between design by design means say either a combination of health or an RTL design IN inverter here is a standard for component. References are again encoder H5. So, now inverter now here although inverter is not called a design it can be a reference. We will see the difference between reference and design. Usually when you go to when you talk about other tools apart from design compiler you will not get term like reference it is always design that is being used. Again instances are instantiations of any design or reference. So, these are the descriptive more descriptive definitions. So, a design consists of instance, next, course and things it can contain some subdesigns and other itself. Most important thing the active design the design that you are working on inside design compiler is called the current design. In fact, this is also some other current design also some other. So, you want to set something to you want to set some design if you want to work on you can use the current design. Most of the commands. So, let us say you want to query what all ports are there in the design. So, most of such commands will work on the current design. They operate in the context of the current design. Reference is a library component of a design again see it is reference is a library component or a design. So, reference can also be used for a design that can be used as an element in building other systems. It can be a simple logic gate or a more complex design. One design can contain multiple occurrences of the reference and each occurrence is called an instance. The idea of reference is that it lets you optimize every cell in a single design without affecting the other design. This is called this is a unique feature that means, for example see this design although the reference inverter is same in both the cases, but the instances U2 and U3 are different. The loading on U2 U2 and U3 will be different the inputs driving U2 and U3 are different. So, the design compiler will optimize U2 and U3 differently based on their own input and output function. This is what it means here. Instance or cell is an occurrence of a reference in a circuit of a reference. Each instance should be unique name. A design obviously can contain multiple instances like we saw two instances of inverter. Each instance also a same reference, but has a unique name to distinguish between. It is you can also call it a cell. So, a cell a design instance which is not hierarchical is called a lead cell. For instance one encoder is would be more or less a complex circuit. It will contain two logic gates. Similarly, H5 will have some blocks. So, encoder and H5 are hierarchical design. They are some designs, but they are hierarchical in nature. On the other hand INV is not hierarchical. It is the there is no other hierarchy in the environment. That is why we call it a lead cell. A lead cell you can the free where a tree contains branches, branches contain lead. Lead is the last hierarchical last non hierarchical unit. That is why it is called a lead cell. There is also a command called parent instance. A unique instance of a library cell is called a lead cell. Some commands will work within the context of hierarchical instance of a parent design. Quotes are inputs and outputs of a design. They can be input, output or in out. Pins are inputs and outputs of a design. So, nets are wire that connects codes to pins and pins to each other. So, here for example, this can be a wire that connects code to this design that this q 0 to INV input is a wire. Again INV output to p 0 is a wire in so on. So, please be very clear. If you are confused then read more about it. Mostly people are confused between port and pin. Just read these descriptions here and then you can read more on the design from pilot manual. So, this example tells what is the difference between the cells in a design or the clarifies other. So, here the x-ray is a design. It contains two references 9 2 and multiplier. So, the design that are loaded inside design compiler are 9 2 and multiplier where u 1, u 2 and u 3 are instances of 9 2 and u 4 is an instance of multiplier. So, 9 2 is instantiated three times multiplier instantiated ones. So, the references of 9 2 and multiplier and the x-ray design are independent of same references. That means, if you have another design which again has a reference 9 2, this reference would be different from that reference. And plus if you go down further this instance although in terms of functionality RTL even it is same as u 1 is same as u 2 is same as u 2 is same as functionality. But when it goes back and the boundary conditions of u 1, u 2 and u 3 are different from each other. So, they will be optimised in this. Now, let us talk about a very important concept called partitioning for partitioning. What does partitioning mean? Partitioning means dividing your design according to different design goals such that it aids synthesis and in turn it aids performance in any. So, the metric here can be that let us say some design is taking a big complex design is taking a lot of time in synthesis. What you could do is you could partition it into smaller designs and synthesise them separately to avoid to save on run time. That it might also help you in terms of performance in any. So, for partitioning a design effectively can enhance the synthesis result, it can reduce the compile time. Compile time here means this time and simplify the constraint and split time. Partitioning affects block block sizes although design compiler has no linear block size limit. But obviously, as we keep on giving the complexity in RTL, the compile time will keep on increasing. So, there are there again to understand if we make the blocks too small, if we make too many modules when we are actually stopping design compiler from utilizing from we are creating artificial boundaries that will restrict effective optimization. Again on the other hand if we make very large block sizes and keep everything inside one module the run time will be moved. So, these are following important points which can be kept in mind for partitioning. Partitioning for designs we use keeping related combination of each other and so on. We will see them unbiased. Let us look at this first one partitioning for design review. Now, what does design review means? Design review means that let us say I am making a circuit called full adder. Now, I know that full adder is a very generic circuit. Lot of designs a lot of designs can use this. So, I should be very careful in designing such blocks that can be reduced from one design to another design, one project to another project, one application to another application. So, design reviews is reduced time to market by reducing the design integration is excellent. So, we should partition it carefully such that such designs can be are easy to be used. In fact, the whole industry is right now design reviews is a very important concept now and chip teams usually pick up designs from different teams just hook them up and they can come out with a circuit for the cell mobile phone over the TV very quickly in a matter of like let us say 3 or 4 months. So, this is enabled by design review. So, the important points are that for such designs we should probably define in document the design interface. We should try and use the sanitize interface in the case wherever possible. The SDN code should be parameterized depending on let us say you are making a generic 8 bit or the 8 bit microprocessor. So, you should let us say you should make something parametric for example, you could make the number of generic registers to be parametric you could give the flexibility to the user to have let us say 8 generic registers or 10 generic registers depending on the application you will need for. So, SDN code should be parameterized. So, this is this is when it comes to the planning of the design you are writing when you design something you should first analyze whether this it can be used by a different project or a different tip and then design it accordingly. I think very important thing which is which is applicable for a lot of levels with even related combination of this together. Now, by default design compiler cannot optimize cannot move logic across hierarchical boundaries. So, hierarchical boundaries I mean across very long modules if we talk about very long therefore, it is very important to keep related combination logic together. If the related combination logic is together then design compiler can use all its algorithms to algorithms to optimize the design. So, for best results that two strategies first is grouping related combination logic and its destination registers together. So, when working with the complete combination file therefore, design compiler has the flexibility to move logic resulting in a smaller and faster design. It also simplifies time interval streams we will see how and it enables sequential optimization. We will see as we progress in this course we will see how do we define the timing constraint and how does keeping combination logic together with people from the part will help in making the job easier. Second thing is eliminate blue logic. Blue logic is the combination logic that connects block for example, you have a structure design we saw an example in the last lecture where you have an accumulator where you have an add another register band. So, now we should try and avoid blue logic at the top level. So, the top level will simply connect the designs together and if we have blue logic at the top level we have again have boundaries we have sub design to design compiler will not optimize the blue logic effectively. We said we should move this logic into one of the block either the source block or the target block. Now, this gives flexibility again to design compiler to optimize block. So, now let us let us look at this figure. So, you have these three boundaries three designs the dotted line here tells us what are the module definition. Now, see this is a critical path critical path means it is I mean critical that is this is the path that has maximum delay. So, this is a big combination cloud again this is a big combination cloud. Now, here design compiler can optimize within this and within this, but again same thing it can optimize in the within this or within this. Now, if we make this into one boundary we combine on these together then design compiler can optimize all these three combination clouds together and we definitely gives it more flexibility. This is a very important concept of registering lock outputs. This helps in simplifying the timing constraints is a very important thing to make sure that all the outputs of your design come out of a register and there should be minimal or no combination logic between the register and the output. We will see how does this make our job easier when we write the constraint. The dry strength on the inputs to an individual block always equals the dry strength of the average input type. We will see the importance of this particular measure let us keep this at 9 for now. The so for example, if we are defining input delay time constraints here, if there is a combination logic between this register and this output then it will have a pattern. Therefore, we should make sure that there is no or minimal combination logic between output and the register is right. So, this is the output and this is the register and there is minimal or no combination logic between these two components. When we study set input delay commands and set output delay commands then we will understand that this makes the job of defining these delays very much easier. So, many there are there are few tools out there which actually read in your RTL it will tell that you have these and these problems before even going through through through once a student 5 lakhs. So, when you actually read in your design in 5 lakhs 5 lakhs will actually tell you whether all your outputs are registered or not. Next part is my design goal. Now let us say you have one example is that you have a design part of the design which is very very time critical very much time critical and there is some other part of the design where you are very much concerned about the area. Now since these two have difference and competing goals it is better to keep their own different having them that on one of the design you can focus on the design part and other design you can focus on the area part. So, one example here is so, we shows idea is to isolate a non-critical speed constraint from the critical speed constraint of it. We see in advanced synthesis concept how can we actually take a small part of the designing and then we see to work more on it in terms of area and in terms of power. So, one was the earlier one was a design goal now this was a compiled technique. Now when we see when you look at the compiled command the command that actually performs the optimization it has lot of options available one such option is enables it to actually use multiple stages in the design as opposed to flattening the design one in one. So, when we increase the number of stages we are increasingly we are decreasing the area but increasing the performance when we flatten the design a lot we are increasing the performance and reducing the area. So, these are again two competing goals. So, one example is that highly structured logic such as array detection perpetually which uses lot of XORs is better suited to structuring, but random logic is better suited to flattening. So, since these two are different type of goals these type of design should be kept perpetually other guideline is keeping shareable resources together. The design compiler is actually pretty good at sharing resources such as adders or multipliers, but resource sharing can only occur if the resources belong to the same where not all these goals. Although even if it belong to different all these goals they can you can tell design compiler to you to actually do resource sharing, but that is again a separate set of commands. So, the main design design compiler work out with the box for you it is best to actually do the resource sharing in the RK system by including any same all these goals. Now, here see our example of coding in the first part of the code A plus B is going to list one pin of the mark, the CTN selects which goes to the register input either A plus B or C plus B. See the second example now in this the RTL is arranged in such a manner that the mark here is moved ahead. So, that it selects the CTN selects between either VNB or VND and then there is only one other. Obviously, the second at the second instance is a better RTL design plus that the resource sharing is done right at the RTL. So, that even if we code in in the we code as given in the example one here in case of unshared resources if these A, B, C and D if these two additions are done in the same on this block then design compiler will give you this type of a input. It will know that it can share resources so, that it will it will move the mark ahead and replace these two idles by a single line. Even user defined resources with the logic data right now there can be a few complex blocks in your design which are user defined functions procedure or macro cells. Now, whenever there are such cases now obviously, design compiler will not automatically create multiple instances of these since it does not understand the complexity is it does not let design if the function is not simple for example, there is a very special memory. Now, this this special memory can never be installed it can only be instantiate. So, it should be the part of your RTL instance instance. Now, design compiler will not create multiple instances of this to resolve any timing problem or reloading problem. So, what we should do is that we should keep this resources together with the logic data right since that later if you find that let us say you have one user defined resources and it drives it drives let us say a net called parity error that is a send out of that is a large send out of them. Now, if we keep this in the same hierarchy and if you later realize that this complex resource is not able to drive such a load we could create multiple instance easily and switch the load. This is again a slightly more complexly problem it is not you will not come come across this problem very early in the design stores or when you are doing the smart encoding by learning learning the process this is a there is a more advanced problem since it involves some complex resources like special memory or matrix again isolating special function this is more applicable for different designs or even at the chip level where you will want to separate your prognosis logic your patch the boundaries can any asynchronous logic. So, all these different types of logic should be in separate hierarchy. So, this is how a chip is made you will be a chip will have a top level that has separate parts a cross initial logic will be a separate module boundary stand will be a separate module any asynchronous logic will be a separate module again core logic would be divided into different function there will be a CPU a video processor unit a peripheral unit and so on. So, that was all about the line partitioning till now this concept was only theoretical, but when you start coding you will start appreciating the the value of each of those principles later in the frame. So, if you miss success you do not register your output you will find at the data space that you are having problems in the final time condition and then you will go back and do not register the output. So, it is good to know the success beforehand that you can actually use an example. Now, let us look at let us look at the optimization priority as stress the fact earlier that the design goals often something for example, area timing and power they are consisting design goals. The optimization engine of design compiler must resolve something and therefore, the priority comes into this. So, DC design compiler priority is first it will focus on fixing DRC only when it fixes DRC it knows that it is the timing it can it can believe in the timing. So, DRC is always number one next comes the timing obviously, the design should be performance even if it has a slightly more power over in it then comes the power last comes in this is the default priority these these priorities can be modified with set cost priority, but it is not a very popular choice because this priority is very low in the nature how this is based on the facts of how designers perceive that all designers want their design to be. So, one example any any any processor that works for a handler device obviously, the DRC has to be meeting first all the design goals to be met before we can talk about performance then the most important factor for a prospective is the speed. So, if you are targeting a 1 gigahertz processor it should meet 1 gigahertz and therefore, it should meet time as 1 gigahertz. Now, since it is a handle design like a mobile power becomes very important to use the battery operator design. So, next comes power obviously, area is also very important because it should be smaller in area, but area is secondary when compared to power and timing. So, I have not seen many people using language set cost priority, but it is good to know that this variety can be changed can be modified. Now, before talking about timing so, on the previous slide we saw that design compiler will first fix VRT and then go on to fix timing. So, what are the factors that affect timing constraints that we describe and delays available from register to register, input to register, register and so on. We see a lot more of this in the next lecture, but more important is the first important thing is the conditions under which the delays are calculated are do not are not described by the function. For example, when you define a clock or you define an input delay or an output delay please do not talk about the sufficient necessary conditions under which delay calculation would be removed. Because all all the delays depend on all the delays of the design depend on the capacitance if for example, the delay of a gate depends on the capacitance the gate sees on the output that capacitance will be comprised of the internet gate capacitance plus the net capacitance plus the thermal capacitance plus it also depends on the input transmission time it depends on what is the voltage, what is the temperature, what is the process we are talking about and so on. So, now in this lecture we are focusing on the second we are focusing on the environmental conditions this is what I am learning environmental conditions. So, we look at all these things we look at how to provide input constraints input environmental conditions, we will see how to set the operating conditions, we will see how to since synthesis at the synthesis level we do not have the information about the net since the design is not routed nor the place is not routed, we will see how to estimate the wire the interconnect data. We will see the output loading conditions how to set them this is called all these conditions combined together that is the operating conditions, the interconnect data, the input boundary conditions and output boundary conditions combined together is called the design only. So, so we look at the core cases of how to specify input condition, how to specify output loading, how to set the PVT condition, how to set the characteristic action. Let us first look at the this part of the operating conditions. So, the operating conditions I have also gone through this earlier let me just quickly go through it again. The operating conditions include the following parameters process voltage and temperature. These are not fixed values these are everything is arranged. For example, process is again arranged on slow flow to pass fast voltage is again arranged which is typically minus 10 percent of the target PVT to plus 10 percent of the target PVT, temperature is again arranged it could be from 0 degree to 25 degree. So, the chip is intended to operate in all the stages and in all the possible combinations. So, the process variation is a it accounts for the deviation in the commitment of the fabrication process not every transistor not every PMOS of every PMOS not every PMOS of every NMOS on that chip there are now billions of PMOS and NMOS on that chip and not every one is expected to behave in a similar number some will be faster some will be slow. So, this is this effect this physical effect is modeled by the process variation. Usually it is treated as a percentage variation in the performance calculation. So, you could say that one way of modeling it puts you could say that let us say that typical speed of the the inverter let us say that typical value of inverter is x. So, the worst case will be 20 percent more. So, the worst case will be 1.2 although this is a very simplistic model and the present day models are much more complex. Supply voltage variation it can vary from the ideal value during day to day operation it models that physical effect. Often a complex calculation using a chip in special water is employed, but again a simplistic model would be to to make sure that the chip works at minus 10 percent of input. Temperature variation is unavoidable in every day operation of a design each part not all parts of the chip can have same temperature and for example using a mobile phone if you talk for half an hour the temperature will be 1 to 2 the temperature of the chip if you choose your phone stand by the temperature will decrease. So, the temperature depends on the usage mode let us different again the in a mobile phone the CPU because the processor part keeps on working all the time. So, it it will get a higher sensitivity compared to the video decoder part because video decoder part will only work when you are watching a video. So, if this physical effect is a is a model using temperature variation. So, it could again be a linear linear model or a other much more complex model. So, the idea is that for synthesis since synthesis is the idea is to optimize a design for maximum performance. So, we should choose the corner in such a way that it is the worst conditions for the operation of the chip. So, when you talk about operating condition we should synthesize it at a slow corner because now at a slow corner slow process corner the delays will be more. So, it will be a limiting factor in terms of performance again we should choose a higher temperature in most of the technologies I say most because some technologies have a negative temperature effect where when the temperature is less the delays are more. So, let us not worry about that in most of the technologies higher temperature means higher delay. So, we should choose a higher temperature again we should choose a lower voltage why because lower voltage means slower devices. So, typically almost always you would choose slow corner high temperature and low voltage. If your design is optimized and meets the performance criteria in this corner it will meet the performance criteria in any corner. So, most of the libraries. So, when you use your when you start a synthesis you will see that the synopsis 90 millimeter generate library will have predefined set of operating conditions. So, how to know what operating conditions are? First we should have the library read inside the inside the design compiler. So, if you want to just see what operating conditions are you can follow the example you can say read clip read file and you can read the dv and you can type a command called report clip report clip will tell you it will give you a reference format it will tell you what all operating conditions are available. It will tell you the process factor this is the factor that is multiplied by the delay part it will tell you the temperature and the voltage it will tell you what is the interconnect model. Again if your library is already loaded you can use a command called list names it will tell you what are libraries are there then you can again do a report clip on that particular library. So, now the command to set operating condition is this set operating conditions WC call here is the operating condition name that is implemented in the library and you can design compiler what library is this operating condition. This is the way you set operating condition. Again the key thing is here is to remember that you always choose the worst case problem worst case delay problem for security. Next comes the interconnect part. Now at synthesis level we do not have any or if there is no accurate interconnect data anything has to be an estimate. So, one type one model to estimate interconnect is called a Weiler model it is a very popular model Weiler model is the simplest method of estimation. So, that we call it WLN WLN gets a rough value of the total wire cap based on the size of the chip and the fan of the chip. So, for each net now this data is WLN. So, what we will do is for each net if we go to this WLN and see what this net. So, there will be different Weiler model Weiler model. So, it will see that for a particular fan out it will go to that listing. So, that listing will contain it will tell you the typical value of the capital system for different values of capital. For example, if the fan of the of 10 it will tell what the capital or the capital gap. The design compiler will see it will pick up that if the cap value from there which is not accurate it is different. So, for each net Weiler model of the Weiler model obtains two values a resistance value and a capital value. WLNs are not specific to each design and based on statistical value. So, what happens in industry is to pick up that will we choose a particular technology and we will choose the standard and as any vendor. That vendor based on the history of the device will give a set of WLNs for that particular technology. And WLN for one technology will be different than WLN for another. Because the resistance and capacitance value they change from technology to technology. So, now one is what Weiler model to choose? Second is what is the mode? So, design compiler supports three modes for determining which Weiler model to use for nets that cross heritable model. Now, most in most of the cases your design will have hierarchy. So, design compiler has three WLN mode. One is the top in this case for each net DC will simply use the Weiler model that is used by the top level of the design. The tool ignores any Weiler model set on the lower designs with the head Weiler body command. You can use the stock mode if you are planning to start in the design. If you are planning that the complete design all the hierarchies will be removed after then we can use this. Obviously, this is the most proved form of Weiler mode. Second is enclosed. So, now DC will look at the net and it will look for the design that completely encloses this net completely and it will use the Weiler model for that design. You can use enclosed if the design has similar logical and significant hierarchy. Now, it is segmented. This is the most accurate or most accurate estimate also. So, it will divide the net into segments and for each segment use the Weiler mode for the design that contains this net. Let us look at the figure to understand this better. Now, we are talking about this net. So, let us say there are 3 Weiler mode available. There are 3 or 4 Weiler mode available to us. So, 3 cross 50, 40 cross 50, 40 cross 20, 30 cross 30. Each of these Weiler mode as the name filters depends on the area. So, the most popular instrumentation is that you have different Weiler mode for different areas. So, let us say your chip area is 20 cross 20 you will use the Weiler mode based on 20 cross 20. 50 cross 50 Weiler mode will have more resistance and more capacitance compared to a 20 cross 20 Weiler mode. Now, when we talk about this net, if we set the Weiler mode to be top, DC will still choose a 50 cross 50 model for this net since we said it is top. For any type in the design, it will not choose 20 cross 20, 30 cross 30 or 40 cross 20. Obviously, this is more that simple meter and it is very simple meter as the implementation mode. When we go to enclose, we go to slightly more accurate implementation. It will see it will look for the smallest design that encloses this mode. 20 cross 20 does not enclose this net completely, 30 cross 30 also does not. 40 cross 40 encloses this net completely. So, these are three segments 1, 2 and 3. So, it will choose the Weiler mode to be the Weiler mode to be 40 cross 40 if the mode is encoded. Again for the segmented one, it will choose 20 cross 20 for this segment of the net, for this segment, it will choose 40 cross 40 for this segment and 30 cross 40 for this segment. So, first you choose what is the Weiler mode, usually it will be area based or high note based and second you choose the mode. So, most of the libraries have redefined Weiler mode models, you can open up your 19-hour details of the library and verify it. You can use report list. Report list will also tell what is the Weiler mode, the report will be function like this, the one given on it on the right hand side. It will tell what are Weiler models are available. It will tell for example, here 05 plus 05 is the Weiler mode. It has some values of R, C, then flow. It tells for what is around, what is the length. Also, it gives automatic selection of Weiler model based on the weiler. This is one nice feature in the Weiler model, where you could have, you could specify the net area and then the tool that for a block which is up to this area, use this Weiler model. Between this and this, use this Weiler model. So, there will be different Weiler models here and the tool can be used based on the area. For hierarchical design, what Weiler model will it apply depends on the mode which is in the top enclosure segment. This slide here tells about what are the commands. So, the default Weiler model library attributes define the default Weiler model for the library. As you saw an example, this slide, some ladders support automatic area based Weiler selection. So, it uses that feature and it can select a Weiler model based on the profile set area. You can, you can turn this off auto Weiler selection if you want to specify the Weiler option. Since automatic Weiler selection can increase the runtime. Since for electrical design has lot of hierarchy, many of these hierarchy will be small. So, it will pick up small Weiler model. Again for larger blocks it will pick larger Weiler based Weiler model. So, it has not only different lines of Weiler models for different parts of the design. This can increase in runtime. If you want to set this off, you can use this Weiler model. The library can also define a default Weiler mode. If the mode is not defined, design compiler will choose the top mode top. So, these two commands set Weiler model and set Weiler mode. These two can be used to select these explicitly. You can say what Weiler model to use or and what Weiler mode to use. So, the Weiler model we choose for a design depends on how the design is implemented. So, it is best to look at the technology library supplied by the technical department to define the best Weiler model. The report design and report timing commands can be used to see what is the Weiler model used. We will see more of these commands later in the lecture. To remove the Weiler model, we can use this command report Weiler model, remove Weiler model. Now all the commands and discussing these lectures, please go back to your example design whatever you are synthesizing during your expending. And use these commands to verify that use the command reports for example. So, verify that your financial library indeed contains some Weiler models. Use these commands check Weiler model, check Weiler mode, do a lot of experiments till you are comfortable with the control. So, these are the assignments for any any command I discuss. Discuss please go back to the health, to the man page experiment with it to learn about it. So, we saw the operating condition part which defines the EP of the design. We saw how to estimate the interconnectation. Now the two things remaining are the input boundary and the output boundary. So, let us look at the input boundary first. So, the most important thing regarding input boundary is that we should model something called the input transition. So, for modeling input transition there are two ways. One is that we tell DC that each of my input has some transmission some positive transmission. If we do not specify this the DC will assume the transition to be 0 and it is wrong it is optimistic. Because any your design will be driven by some cell and the transition will never be 0. It will be greater than 0 for all the factors. So, all the setting case we can choose we can tell the nine from pilot lab and expecting my input to be driven by this cell. In that case DC will use the driving characteristics of this thing. So, even if the input transition here is 0 there will be some transition here. There will be some transition at the input why because we specify we told DC that there is a driving career. What is the effect? Driving for transitions on the input port affect the cell delay of the gates. So, transitions here will affect the delay calculation of the combination of the gates. Therefore, it is very important to accurately model transition times of all inputs. How do we do that? Two very famous commands by the call DC will assume 0 drive resistance on input ports means infinite drive strength drive resistance. So, that the term drive strength is less important of drive resistance. So, 0 drive resistance means infinite drive strength that means that port can drive any cap or any resistance which is not obviously possible. To set real estate drive strength we use one of the following commands set driving strength or set input function. We use the set driving strength command to specify the drive characteristic. Now, we have to tell for example, when we use this set driving strength command we tell DC that I am expecting this input that this will be driven by a project score from this library. So, DC so, this command is compatible with all delay models including NMDM and PSYDM delay models. So, this command associates the library pin with an input port. So, that the delay calculators can accurately model their drive compatibility of an external driver. What we did here is that we told DC that this particular type of cell for example, a project score drives my input strength. Now, DC will use the characteristics of this command to calculate a reasonable transmission time of the input. Or if you do not know if you cannot estimate what kind of cell width value input to directly give a value some value at 7 percent. What will that value be? We will see. Now, we see the output boundary. So, the the capacitor load on the output port affected transmission time obviously, if you assume the load to be 0 here it is not realistic and it will affect the optimization in this class. So, the central if for example, this class is driving if you is driving the output directly output directly and we assume a 0 load at a this can affect the optimization of this cell this sequence of cell. Since, the boundary conditions are not accurately. How do we model this? We model this using a set load command. Directly we tell DC that my output out drives for example, a cap of 20 percent of. So, this is the command set load the cap value will again come from the library and the output port. By default if you do not do this it will assume 0 capacitor load and it is not correct it is not accurate. So, this how does this set for example, you have this this sequential cell you have let us say 3 different type of drives in your library x 1, x 2 and x n. Based on the load here if the load is 0 here and you do not specify set load DC will assume a 0 load it will use an x 1 clock x 1 drive set clock. However, let us say when you go to back end or somebody else uses a design any connects let us say 4 inverter here. Now, this x 1 will not help the transition will be very very bad because it will not be able to drive this much this much load. So, so it is good to estimate that and apply that estimated value as set load. So, that DC what it will do now it will mainly observe the critical x 1 x 2 this will enable the guy who is using your design the guy who uses a design will see good transition numbers coming out of a design right. Now, the question is that I have my design I do not know what happens at the input boundary or the output boundary I am not aware of that I do not know in what conditions my design will be. Conditions need input and output boundary conditions not the operating conditions I know the operating conditions are more like this, but I do not know what kind of cells will drive my input I do not know what kind of sign out my output will drive. How do we estimate in such cases estimation is called low budget this estimation is called low budget. So, how do we create a low budget at the inputs at the inputs we assume that there will be a D prime why because this is the worst we should be prepared for the worst. So, you could assume that a buff x a buffer of the lowest span or an inverter of the lowest span is driving my input and you can set driving set accordingly or if you do not want to set a driving set you can apply the transition number. Now, what transition number you could apply you could apply remember if you look up table we saw in the magnitude space there a buffer for example, an x 1 buffer has a maximum level of transition you could apply that maximum transition at the input. So, that will be a worst case transition for this input. So, assume a reason driving the inputs to be conservative or set a high value the maximum value of the input of the transition from the look up table of a value. Let us say input capacitance of input port ideally I would say that if you have done the job well in the worst case the second is not in dynamic unit this is very important estimate the number of other major blocks the output may happen right. So, the output estimate if you cannot estimate then what you do? You apply a load here which is if it can be the maximum load your combination cell here can drive. So, for example, you have three blocks x 1 x 2 x 3 choose what maximum load your exported right and set load that set load here that one what DC will do now it will it will it will know that if you are driving this must load and it will always to make sure the dry strength port of that of the register that is done here. So, you are on the same side. So, now what do these these constraints do the input constraint input transition time will let design compiler correctly calculate the delay of the logic here at the input boundary with an output load will enable design compiler to instantiate a higher drive cell here at this point. So, you are safe on both the input side and the output. I will summarize again what all things you need to specify correctly we have the operating of the design in my mind. So, this is the figure. So, we saw how to set the operating condition operating condition sets the ppt of the design we process both the design always choose the worst case. We saw how to estimate the interconnect R and C values we use set viral model we use a viral model that is part of a library most in most of the cases although there is something called custom viral model. So, for a particular chip your backend team or library team can come up with a custom viral model which is specific to your chip this is like in a specific topic altogether but it was the case when you can you can use that custom viral model you use commands like set driving cell or set input function do not worry about the set drive command set drive is not used specifically now it is either set driving cell or set input function and the input side although you could also set load at the input but it but it will help again. So, set driving cell and set load go together you can set the driving cell and you can set the load. So, that will help DC in calculating the function time of the input or you could use set input function again as the output we just set load or you can also set fan out load if you know about kind of fan out load. Set fan out load set load is a is a capacitor number set fan out load is a simply number that how many fan out will it drive. So, in the next lecture we will now we will look at the tiny constraints that talks input relation output. Thank you.