 Assistant Professor, Electronics and Telecommunication Engineering, Walchin Institute of Technology SolarPort. Today, we will discuss the IC-74C926, whose function name is Counter and Seventh Segment Display Circuit, which is mostly used for frequency measurement, learning outcome. At the end of this session, students will be able to describe key features and applications of IC-74C926, which is a counter and Seventh Segment Display Circuit contents. We will start from logic diagram of IC-74C926. Then, we will see how the counter operation takes place. Finally, we will see the Seventh Segment Display operation and its interface. In this logic diagram, we see the main component is it consists of four decayed counters. As we see here, this is a decayed counter 1, 2, 3 and 4. This counter counts the clock pulses connected to this clock input. The binary number of this count is available on these four lines. The output of this counter is connected to an output latch, which is a 4-bit latch for each counter. Mainly, this is what the circuit. We can reset the counter by using this reset input circuitry. When this reset is active high, when we connect logic 1 to this reset input, these counters are reset to 0. When the clock pulse is applied, at the negative edge of a clock pulse, this counter counts in upward direction. This is a unit's counter, this is a 10's counter, this is a 100's counter and this is a 1000's counter. After that, we get a carry out signal, which is generated out of most significant counter, which is used for cascading other Seventh Force C926 if you want to count more than the number counted by this counter. In addition to that, it consists of a multiplexer and it is connected to an internal clock. Multiplexing of this Seventh Segment Display is done by using this multiplexer. These are the A out, B out, C out and D out. There are four displays that we can connect. Each Seventh Segment Display displays the count in these counters. Whatever the count is there, which is latched and which is given to the BCD to Seventh Segment Decoder. There is a internally, there is a BCD to Seventh Segment Decoder as well as the drivers are present in this block. Here, we have additional two controls associated with this latch. One is a display select and this is a latch enable. Latch enable is a active high signal. When we make this equal to 1, whatever the counter outputs are there, these are latched, means stored in these latches. So, this way, we can see the block diagram of 7, 4, C, 9, 2, 6. So, this is a BCD input and there are seven segment outputs are there. This is a segment output B, C, D, E, F and G and also which latch output is given to the BCD to Seventh Segment Decoder is decided by this multiplexer. For example, if you want this units digit is to be displayed, then the latch output of this is given to the BCD to Seventh Segment Decoder and correspondingly the D output is activated, so that we can activate that Seventh Segment Display. So, this is what the block diagram. I have taken this figure from fairchildsemi.com website. Let us see the description. It is a CMOS counter with four digit decimal counter having internal output latches as we saw earlier. Each counter has got internal 4-bit latch. It has internal multiplexer with four multiplexing outputs and free running oscillator which requires no external clock. There is internal clock which drives the multiplexer for display circuit and which has got four outputs and this IC supply voltage works on a supply voltage ranging from three volts to six volts. So, it supports wide range of input supply voltage. This is what the description of input pin, reset is input pin as I said earlier. It is a asynchronous input and it is active high. When we reset this, when we make this input high, the counters are reset to zero. As we saw earlier, which is connected to latch, when it is high, displays output of the counter as it is, but when it is low, it displays output of latch. So, here when this display select is low, output of latch is displayed. That means latch data is displayed, but if you want to display whatever is present in the counter, then we have to make this display select is equal to high. Then this is a latch enable. This is again active high. When it is high, counter contents flow through latch. Latch enable. When we make it high, counter contents flow through latch and when it is low, counter contents are latched and clock input to the counter is a negative edge sensitive. Let us have a question. What is the maximum count the IC74C926 can reach? You pause the video and answer the question. The question is what is the maximum count the IC74C926 can reach? Since it consists of four decay counters, the counters when they are reset, the counter content becomes all zero. That means 0, 0, 0, 0, 4 zeros and since they are decay counters, each digit can reach up to 9. That means all the digits maximum value can be 9. So, the maximum value is 9, 9, 9, 9. So, it is 9999 is the maximum count the IC74C926 can reach. Let us see now the carryout operation. How carryout operation can be used for cascading the IC74C926. So, this is a clock signal. This clock is connected to the counters and carryout becomes logic high when the count value in the counter reaches 6000. It remains high till the counter reaches its final value and its final value is 9999. At that time it becomes again zero. So, whenever carryout reaches zero from 1, we can say that counter has reached its final value and this signal can be used for cascading the another IC74C926. Then that is why we say here carryout is used for cascading of counters. Then we can see the segment output. There are seven segments and these seven segments can source a current of 40 milliampere each. Then this is a digit output. Digit output means a out, b out, c out and d out. These are also used for driving display which can source a maximum current output of 1 milliampere. Here this is a a out multiplexing display circuitry. This is a a out diagram. That means a out becomes high. Whenever it becomes low, b out becomes high. It remains high for this much time. Again it becomes low. Whenever this becomes low, c out becomes high. It remains high for some time and then becomes low. After it becomes low, d out becomes high. That means activated one after the other. a out is first, then b out, c out and d out. So, this way we can display the four digit seven segment display using multiplexing technique where this t given is a clock connected to the multiplexer. That is why it is 1 by f max. Code goes to all the seven segment displays. Only that particular display will be active whose this transistor connected will be on. That means, for example, if d is on, on means if this d output is logic 1, this is a NPN transistor. Logic 1 means high voltage is there. So, this transistor becomes on and since it is a common cathode array display, common cathode terminal is connected to ground. So, whatever the number present on these seven segments will be displayed here. Whereas, these are not displayed here because c is 0, b is also 0, a is 0 when d is 1. So this way, after some time this is made on and the digit corresponding to this will be output here at that time. So, this way we can do the multiplexing of the display. This is what segment identification. This is segment a, b, c, d, e, f and g. So, how we can display 0? So, we can display 0 by making on all the segments except this g. So, this way for one we can make on segments b and c. These are my references. The IC 7, 4, C 9, 2, 6, data sheet from www.fairchildsemi.com and one more paper I have written. So, I have chosen for taking the contents design and implementation and performance analysis of a low cost optical tachometer by SM Bakibilla. Thank you very much.