 Hello and welcome to this presentation of the system overview of the watchdog timers for the STM32-H7X5 and STM32-H7X7 MCU lines. STM32-H7X5 and STM32-H7X7 microcontrollers feature four embedded watchdog blocks which offer a combination of high safety, timing accuracy and flexibility. Option bytes can be used to adapt the behavior of the watchdogs to the user application. The embedded watchdog blocks feature two independent watchdogs, IWDG1 and 2, and two window watchdogs, WWDG1 and 2, each dedicated to a CPU. Each CPU can receive an interrupt if the other CPU has been reset due to a window watchdog timeout, and each CPU can receive the early interrupt of its dedicated window watchdog. Watchdog functions can be configured through option bytes. Watchdogs IWDG1 and WWDG1 are dedicated to CPU1, while watchdogs IWDG2 and WWDG2 are dedicated to CPU2. Both watchdog peripherals, independent and window, allow detecting and resolving malfunctions due to software or hardware failures. The window watchdogs or WWDG1 and 2 clocks are derived from the APB clocks and have a configurable time window that can be programmed to detect abnormally late or early application behavior. The WWDGs are best suited for monitoring software execution. Each WWDG provides a reset and an early interrupt signal. The independent watchdogs IWDG1 and 2 are clocked by the low-speed clock, or LSI, and thus stay active even if the main clock fails. They are consequently best suited for applications which require the watchdog to run totally independently of the main application. The IWDGs are ideal solutions to recover from unexpected software or hardware failures. Each core can enable the window watchdog clocks via the RCC block. Setting the WWDG1EN bit in the RCC APB3ENR register enables the WWDG1 block clock, while setting the WWDG2EN bit in the RCC APB1LENR register enables the WWDG2 block clock. The software cannot stop WWDG1 and WWDG2 downcounting by setting WWDG1EN and WWDG2EN bit to zero, respectively. Note that none of the cores can enable the window watchdog managed by the other core. The independent watchdogs do not need their clock to be enabled by the RCC block. IWDG1 is implicitly allocated to CPU1 and IWDG2 to CPU2. An option byte allows IWDG1 and IWDG2 watchdogs to be automatically enabled after a system reset. A WWDG block is frozen when the corresponding CPU enters the CSTOP mode. When the domain enters D standby state, the WWDG block located in this domain is reset. IWDG blocks always remain enabled once enabled. Two option bytes allow freezing IWDG downcounting. IWDGFZSTOP option byte allows freezing IWDG1 and 2 downcounting when the CPU1 or CPU2 is entering CSTOP mode or deeper low power mode, DSTOP, DSTANDBY or product standby mode. And IWDGFZSTANDBY option byte allows freezing IWDG1 and 2 downcounting only when the product enters standby mode. Please refer to these peripheral trainings for more information if needed. Reset and clock control or RCC. System window watchdog or WWDG or independent watchdog or IWDG.