 Hello, and welcome to this presentation of the STM32G0 system memory's protection. It will cover the different means for protecting code and data. Memory protections have been designed for different purposes. A read protection, for example, will prevent the dumping of embedded software code through an external access and will protect the developer's intellectual property. A write protection will prevent certain flash sectors from being accidentally erased by a load overflow in a software or data update procedure. STM32G0 microcontrollers provide several features for protecting code and data located in flash memory and backup registers. In addition to these typical memory protections, the STM32G0 also introduces a new mechanism to ensure the safe execution of sensitive firmware. The following slides will describe all these protection features. The following means are provided for code protection purposes. RDP, stand for Readout Protection. PC ROP, stand for Proprietary Code Readout Protection. WRP, stand for Write Protection. Secure User Memory Protection is a new feature of STM32G0 microcontrollers. It ensures the safe execution of sensitive applications in addition to code and data protection. Readout Protection, or RDP, is a global mechanism that prevents external read access to flash memory, option bytes, and backup registers. An external access can be gained by using a JTAG connector, a serial wire port, or the boot software embedded in SRAM. Three levels of RDP protection are defined from Level 0, which offers no protection at all, to Level 2, which has full and permanent protection. Protection levels will be described in the following slides. PC ROP is a memory access protection against code dumping. It is used to protect the intellectual property of the code. The protected firmware remains executable, but read and write access performed by the CPU executing malicious third-party code, like Trojan horse, are prohibited. The Write Protection mechanism prevents accidental or malicious write and erase operations. Secure User Memory is a flash memory area with a specific protection mechanism to ensure the safe execution of sensitive firmware, in addition to code and data protection. All protection mechanisms are configurable via the STM32G0 option bytes. When the lowest RDP level, Level 0, is set, the device has no protection. If no write protection is set, all read or write operations on the flash memory and the backup registers are possible in all boot configurations. Option bytes are also changeable in this level. Level 0 is the factory default level. In Level 1, read protection is set for the flash memory and the backup registers. In this level, protected memories are only accessible when booting from user flash memory. Whenever a debugger access is detected or boot is not set to a user flash memory area, any access to the protected memories generates a system hard fault, which blocks all code execution until the next power-on reset. Note that option bytes can still be modified in this level, making it possible to remove the protection. This mechanism is explained in the next slide. We have seen in the previous slide that it is possible to modify option bytes in Level 1. It is then possible to remove the protection by changing the protection level to Level 0. This protection level regression will cause the flash memory and the backup registers to be mass erased. Flash areas protected by PC Rop or configured as secure user memory can be erased or left unchanged depending on their erase policy configuration. Readout protection Level 2 provides the same protection as in Level 1, but the protection becomes permanent. Option bytes cannot be modified, so once the RDP protection is set to this level, there is no way to modify it and level regression with mass erase mechanism is no longer possible. This level must only be considered in the final product when the development stage is completed. Note that to ensure that there are no back doors, this protection cannot be bypassed even at ST factory. This slide shows the possible transitions between each readout protection level. It is always possible to raise the protection level, but regression is only possible between Level 1 and Level 0 with the consequence of a full user flash erase operation. Note that the RDP level is coded in one option byte. Level 0 is coded by a 0xAA value. Level 2 is coded by a 0xCC value and Level 1 is coded by any value other than 0xAA or 0xCC. This table summarizes the different types of access authorized for the flash memory and backup registers according to the readout protection level, configured boot mode and with debug access as seen in previous slides. PCrop means proprietary code readout protection. Third parties may develop and sell specific software IPs for STM32 microcontrollers and original equipment manufacturers may use them when developing their own application code. In order to protect the software intellectual property, the code must not be copied or read. The PCrop's purpose is to protect the confidentiality of third-party software intellectual property code against malicious users independent of the RDP level setting. The protected firmware can only be executed by the Cortex M0 plus core. Any other access like DMA, debug and data read, write and erase is strictly prohibited. To be compliant with this constraint, the firmware must be compiled with the appropriate compilation option. For example, minus execute only for KyleTools. Without this option, constraints are interleaved with functions in the read-only section called the literal pool. The Cortex M0 plus MPU does not support execute-only access permissions. The proprietary code readout protected areas in flash memory are defined through the option bytes. Two PCrop areas can be defined. Each area is configured with a granularity of 512 bytes and can be set from 512 bytes up to the full bank. The areas are protected against data accesses. Note that sectors protected with the PCrop feature are also protected against the write access, offering protection against unwanted sector write or erase operations. The PCrop protection can only be removed by an RDP level regression from level 1 to level 0. When executed, this mechanism triggers a full mass erase of the flash memory. Depending on the PCrop RDP option bit, the PCrop areas are erased when the RDP protection is changed from level 1 to level 0. The write protection protects code and non-volatile data from unwanted or accidental erasure. This protection is only available on the flash memory. The write protection can be set on a selection of flash memory sectors only. There are 64 sectors of 2K bytes in STM32G0 microcontrollers. When a sector is protected, it cannot be erased or programmed. Any attempt to write access, the sector will cause a flash memory error. If at least one sector is write protected, a mass erase of the flash memory cannot be performed. The protection needs to be removed first. The purpose of the secureable memory is to store code and data available during the boot time that become inaccessible once the boot program sets a control bit. The typical use case consists in performing an authentication and possibly decryption of the software image present in the flash memory by using cryptographic keys contained in the secureable memory. The authentication and decryption programs are also stored in the secureable memory. Option bits are used to set the size of the secureable memory in page units. Base address is always 0x08 million, which corresponds to Cortex M0 plus reset vectors. When the SEC size field in the option bytes is equal to 0, secureable memory is not implemented. This field can only be modified in RDP level 0. When software sets the SEC PROT bit in the flash CR register, the secureable memory is no longer accessible. In case of secure boot, used to perform image authentication and decryption, the SEC PROT bit is set to 1 when the authentication is successful, just before branching to the first instruction of the image. Once the SEC PROT bit is set, it cannot be cleared by software. The only way to clear this bit is to apply a reset. Of course, code present in the secureable memory may decide to erase a part or the secureable memory. Furthermore, changing the flash read protection level from level 1 to level 0 triggers the erasure of the secureable memory. Note that the code present in the secureable can also be protected against read and write accesses by mapping it into proprietary code readout protection or PC-ROP areas. Changing the RDP level from level 1 to level 0 will erase these PC-ROP areas, whatever the value of the PC-ROP RDP bit. Only the contents of PC-ROP areas outside the secureable memory address range will be preserved. Taking control of the Cortex M0 Plus by using invasive debug can be temporarily disabled by programming appropriately the DBG SWEN control bit. For instance, the secure boot can decide to clear this bit by performing authentication and decryption and then to set this bit to 1 to re-enable invasive debug once the authentication is successful. In the STM32G0 three different boot modes can be selected. Boot from embedded SRAM boot from system memory and boot from main flash memory. Executing a secure boot from secureable memory implies that the boot area is the flash memory. To disable the other boot areas the boot lock option bit has to be set in the flash SECR register. This option bit can be set unconditionally. However, resetting is possible only when RDP level is 0 or RDP is changed from level 1 to level 0 which causes a full mass erase. Please refer to the flash memory training to learn more about the memory architecture, option bytes, and flash memory operations.