 So, let us get started in the last lecture we had seen you know the different scenarios for scaling and we had also discussed about the non scaling factors. So, today we will get started with the discussion now that we know we have to scale the CMOS technology what are the challenges in scaling right, what are the some new effects that will come into picture only when we miniaturize the transistor. So, the first effect that we are going to talk about is what is called short channel effect. This is a very classic problem wherein the threshold voltage of the transistor as you know which is a very important metric for a MOS transistor that starts rolling off that is the threshold voltage starts decreasing as you start miniaturizing the transistor below may be a micron or so certainly in the nanometer region you know your threshold voltage will decrease very dramatically. And to that end first let us get started with the understanding the threshold voltage in classical transistor that is what we call long channel transistor. So, we will sort of revisit the threshold voltage equation we will actually derive the threshold voltage equation for a simple long channel case. And then from there go on to discuss what I called short channel effect as I mentioned in particular Vth roll off. I use this you know symbol Vth do not confuse it with the thermal voltage here it essentially represents threshold voltage right. Now, given that there is a threshold voltage variation then we will look at a very simple model based on what is called charge sharing right. This model was first proposed way back in 74 by Yao and co workers and hence it is also called Yao's model. Yao's model to predict the threshold voltage in miniaturized transistor which is different from the threshold voltage classical equation that you would have seen in a long channel transistor. So, let us set this as the goal for today's lecture. So, let us first get started with the threshold voltage equation for long channel transistor. So, before that you know we will have to understand some basic aspects here when I am talking about a long channel transistor. You see the source and drain are really placed far apart the distance between source and drain is huge. And then of course, you have the oxide silicon oxide and your gate electrode right this is your structure right and you apply voltage here. And here we are considering n channel transistor and as a result of that we have p silicon substrate here which has a doping concentration acceptor impurities let us say Na ok. For example, this Na may be of the order of 10 to the 15 per centimeter cube ok. So, when we look at this long channel transistor it suffices us to really look at what is called a one dimensional picture right meaning that the source and drain are really so far apart from each other that if you were to just focus on so called MOS capacitor that is metal oxide semiconductor is a capacitor right you have an insulator in between. Oftentimes we also call this as an MIS diode you see diode is a two terminal device and this also happens to be a two terminal device because you have a body or p silicon is one terminal and gate voltage is another terminal right. So, all we need to do is only look at a very simple MOS structure which has p silicon substrate and an SiO2 and a gate electrode right this is a picture that we are going to focus for the initial part of this lecture. Now if you recall what is threshold voltage threshold voltage is a condition wherein we are going to alter the p type doping which is essentially holes or majority carriers if you recall if 10 to the 15 is the doping concentration then my whole concentration is also equal to 10 to the 15 per centimeter cube whereas my electron concentration remember what is it and is Ni square by p right and the thermal equilibrium this relation holds good as you know at room temperature Ni is about 10 to the 10 per centimeter cube right 1.4 10 to the 10 let us approximate it to 10 to the 10 per centimeter cube. So, Ni square is 10 to the 20 and p is 10 to the 15 and hence my N is essentially 10 to the 5 centimeter cube right they are really minority very very small concentration of electrons we need to create a electron channel you see in MOS transistor right we need to invert the whole population here and convert that into an electron population we define an inversion voltage Vth such that the electron concentration right electron concentration which is N at surface remember only at the surface we are only talking of a surface channel device right we do not care about what is the electron concentration deep in the bulk electron concentration at the surface should be same as the whole concentration that you began with right which is 10 to the 15 per centimeter cube in other words N surface should go all the way up to 10 to the 15 per centimeter cube ok and that is what we do when we apply a positive gate voltage we will actually see this picture in a little more detail by using what is called energy band diagram today, but the fact is simplistic way of explaining that is you apply a positive voltage that will attract more electrons to the surface and you start increasing the electron population at the surface. So, 10 to the 5 electron which was initial concentration starts going up slowly right and eventually you reach the 10 per 5 it becomes 10 to the 15 and that is the voltage on gate at which we have reached the inversion condition and that is the threshold voltage of the transistor ok. So, that is essentially what we mean by threshold voltage right. So, now let us look at what is called the energy band picture right what we mean by energy band picture is that you know we have silicon which has you know valence band and conduction band it has a band gap as you know E g of about 1.12 electron volt at room temperature and you know we typically you know locate the middle of this band gap and call it as E i E i is exactly in between the E c conduction band and the valence band that you have ok. Now, if it is p-type doped semiconductor as you know then the Fermi level right the Fermi level will be in the lower half of the band gap I typically show the Fermi level with this symbol here and the distance between the intrinsic level and the Fermi level is given by what is called a bulk potential we denote it as phi b which is essentially given by this relation k t over q which is thermal voltage natural log of the doping concentration divided by n i ok that is the bulk potential that is essentially difference between the location of Fermi level and the intrinsic level when you have a intrinsic silicon that is no doping right your Fermi level will be right on top of E i there is no difference between E i and E f right that is essentially your intrinsic silicon right otherwise you know your Fermi level will move along the band gap that you have this is what you will have in p-type and in n-type the Fermi level will be on top of E i right and accordingly we also indicate that your electron concentration can be represented as you know it has an exponential relationship with respect to the location of the Fermi level right k is here Boltzmann constant and t is absolute temperature right. So, when your E f is equal to E i n is equal to n i where E f is below E i E f minus E i as you know is negative and n will be less than n i and on the other hand your p is given by n i E to the E i minus E f by k t in this case here E i is more than E f E i minus E f is positive of course, your whole concentration is more than electron concentration and your electron concentration would have gone below n i and as you can very clearly see from these equation your n p is essentially equal to n i square right these two exponent will cancel out your n p is equal to n i square. So, this is what you have. So, exact location as you know the distance between E i and E v is about 0.56 E v given that the band gap is 1.12 E v as you start doping the band gap I mean the Fermi level starts going down, but a very good rule of thumb to remember as far as bulk potential is concerned right. If you start increasing the doping concentration above the intrinsic level remember intrinsic level is 10 to the 10 correct 10 to the 10 per centimeter cube above intrinsic level if you start increasing the doping concentration by every order of magnitude like 10 to the 11, 10 to the 13 and so on and so forth right your bulk potential or the distance between E i and E f will increase by about 0.06 electron volt. This is a very good rule you do a exact calculation you will find that it is very close. In other words for 10 to the 11 this will come down by 0.06 E v for 10 to the 12 0.06 times 2 because it is two orders of magnitude away you see right then it is 0.12 E v and for 10 to the 13 it is 0.18 E v and so on and so forth right. So, in the previous case as you know we consider the doping concentration which is 10 to the 15 correct. So, for 10 to the 15 the location of the Fermi level will be 0.3 electron volt below intrinsic level because it is 5 times 0.06 approximately right which is 0.3 E v. So, then in the case of particular case that we have looked at p type silicon this will be about 0.3 electron volt that corresponds to a doping level of 10 to the 15 and this is how you will have a picture everywhere whether it is surface or in the bulk to begin with. In other words if we were to consider an energy band diagram going from the gate all the way to oxide and into the substrate we draw an energy band diagram again let me have that picture for you here p silicon this is oxide and this is gate. Let us suppose that we have used a gate we have a terminology called work function for this gate electrode that you are using work function essentially means it is the energy distance it is the energy difference between the vacuum level and Fermi level. In other words if you give so much energy to the electron which is sitting at the Fermi level of any metal you free that electron out of that metal and bring it to the vacuum right. So, that is essentially the meaning of work function and similarly we can define work function in silicon as well right silicon also it is the same the distance between the vacuum level and the Fermi level of silicon is what we called work function of silicon. And you know if we consider that this is a vacuum level energy level that is and I have this band diagram which I showed you there are electrons in conduction band and also electrons in the valence band which are closely bound electrons to the silicon and as I said this is intrinsic level and Fermi level is essentially below the mid gap for p type silicon. So, this distance here between the vacuum level and the Fermi level is what we call work function right you know this work function of silicon phi silicon and for work function of silicon is essentially this quantity plus half the band gap plus the bulk potential correct. And this quantity is what we call in the context of semiconductor electron affinity that is the distance between the vacuum level and the conduction band level is what we call electron affinity. Again it means that if you have an electron sitting in the conduction band you need to give only this much energy to free this electron in silicon the electron affinity happens to be 4.05 electron volt. And you know half the band gap as you know is 0.56 electron volt and for the doping concentration that we considered which is 0.3 electron volt right 10 to the 15 doping concentration. So, this distance finally is 0.3 electron volt correct. So, you know what is your work function for silicon then it is essentially 4.91 electron volt that is your work function of p type silicon which is doped with acceptor impurities of 10 to the 15 per centimeter cube. Let us for the time being assume that we are using a gate metal which has a work function of exactly 4.91 electron volt meaning there is no work function difference between the gate metal and the silicon. You know metals come with a variety of work functions right you have aluminum for example, whose work function is 4.1 electron you have a gold and platinum which have very high work function of the order of more than 5 electron volt right. So, let us assume a fictitious metal which has a work function of 4.91 electron volt there is no work function difference on the gate side and the substrate side. In other words this is a two terminal device this is one terminal and this is another terminal both have the same work function. Then if we were to look at this direction and sketch a band diagram going from the gate oxide and silicon right the band diagram would look something like this. On the left hand side I have gate and then I have silicon oxide right and then I have this silicon which is as we already have seen is a p type silicon correct it may not be exactly to the scale, but you know this is E c this is E i this is E f this is E v valence band right. The bands are flat you know conduction band is flat valence band is flat of course, Fermi level is flat and this is the gate work function I have chosen the gate whose work function the Fermi level on the gate is exactly same as the Fermi level on the silicon. So, there is not going to be any movement of the carrier from gate on to the silicon or from silicon into the gate right that is why we have chosen identical work function. Then we indicate the oxide that silicon oxide has a huge band gap that is why we call it as an insulator. The band gap of the silicon oxide we treat it as 9 electron volt that is huge and the electron affinity in silicon oxide is about 0.9 electron volt that is this is your vacuum level this is 0.9 electron volt and this as you know is 4.05 electron volt and there is this band offset here which is what we call a band offset that is an electron which is sitting in a conduction band of the silicon. See the huge barrier of about 3.15 electron volt to go in this direction that is why oxide is a very good insulator. Similarly, the holes which are sitting in here also see a huge band gap in fact the band offset for holes is even more than the band offset for electrons. You know you can go back and compute this as an exercise for yourself you can do it very easily because you know this is 9 electron volt you know this is 4.05 here and you know what is the band gap and you can compute the barrier for the holes right and you see that that will be more than 3.15 electron volt right. This is what you see in terms of energy bands right this is what we call as a flat band condition right. In other words we have chosen a condition we have chosen a metal such that V F B is equal to 0 meaning without doing anything without applying any gate voltage already the bands are aligned they are all flat. Align meaning they are flat there is no band bending this is the condition that we have. Now, what we need to do only at the surface remember that only at the surface we need to convert this p region into n region not in the bulk in the bulk nothing will happen in the bulk it will continue to remain as you know your p type silicon. In other words remember it is essentially the picture of the that we had this is p type silicon this is oxide and this is gate right that picture is sort of flipped around right I mean we are looking in this direction going from gate oxide into p type silicon. Now, let us see what happens I start applying positive voltage to the gate when I apply positive voltage and on 0 voltage then the two Fermi levels will not be aligned anymore because the electron energy on the gate side and the silicon side is not the same because you are applying a potential difference. In fact because we are looking at electron energy in the energy band diagram when I apply a positive voltage on the gate the electron energy will go down here the Fermi level on the gate side will go down compared to the Fermi level on the silicon side that will set up an electric field in the system. It is not very hard to imagine right I mean you apply voltage there is an oxide insulator right it is a capacitor structure applying positive voltage essentially means that I am putting positive charge on the gate this positive charge has to be balanced by equal and opposite negative charge on the substrate right. If you have a positive charge on the gate and negative charge in the silicon there is going to be an electric field that is going to be set up right and this electric field results in what is called a band bending the bands in the oxide start bending the bands in the silicon start bending. In fact whenever there is a gradient with respect to position in energy band diagram right there is an electric field ok. So, electric field and the energy band diagram gradient are related right and that is very easy to understand remember electric field is a negative derivative of potential right and the energy is here remember potential is defined with respect to positive test charge ok. Whereas, the energy is that we are drawing here are for electron these are electron energy and also these are not expressed in joules, but they are expressed in electron volt. In other words potential is related to this energy or electron volt right how is it related essentially potential is given as minus e over q ok where e is an electron volt q is charge, but charge is not in coulomb right charge is one electron right. So, when you have you know 4 electron volt divided by one electron you get 4 volt as the potential you see right. So, that is how potential and energy in the energy band diagram are related to each other this q is only for dimensional consistency you see because e is expressed in electron volt whereas, potential is expressed in volt. So, you are converting electron volt into volt by dividing by one electron that is about it ok. So, obviously now you can see if you replace psi with respect to minus e by q then you can immediately see that your electric fields are essentially related as d e by d x where x is the position ok. In the flat band condition e does not change with respect to x e is flat you see right and there is no electric field that is obvious right there are no charges no electric field, but whenever I have charges set up by applying the voltage now there has to be electric field and hence there has to be a gradient in band diagram ok. So, with this background now we can very easily sketch this band diagram under the condition that I have a non-zero positive voltage applied. So, what happens you have non-zero positive voltage applied and because of that you will have a condition which would essentially look like this ok. Remember we are applying a positive voltage right the Fermi level will be right up here because the energy of electrons on the silicon side is more than the energy of electrons this is the Fermi level on the gate side and this is Fermi level on the silicon side. So, what would then happen way away from the this region nothing will change right. So, this will be exactly like what you had this is p type E f is below E i by certain amount, but as I start approaching you know there is this band bending correct as you can see now the Fermi level which was closer to the valence band here has gone little further away from the valence band meaning the whole concentration here has decreased and electron concentration here has increased right. In fact conduction the conduction band this is conduction band right has come closer to the Fermi level right and hence electron concentration is slowly increasing as I start increasing the gate voltage electric field will be set up higher and higher more electric field will be set up and more band bending will take place right and this band bending how much this bands have bent at surface with respect to bulk is really the potential drop in silicon. You see it is essentially a series circuit of oxide and silicon when you apply a voltage part of that voltage will drop across oxide and part of that voltage will drop across silicon and this is what we call as surface potential psi s. So, as I start increasing the voltage I am applying positive voltage as you know I start increasing the voltage more positive charges are put here more negative charges have to come in here initially the negative charges are coming entirely by acceptor ionized impurities because electron concentration is very small. Although it is increasing remember compared to 10 to the 15 acceptor impurities this is very small, but as you start applying higher and higher voltage let us consider another case where v g is much higher then the bands will bend even further you see. Now you see the conduction band has come very close to Fermi level you will have a situation where electron concentration at the surface could reach as high as the whole concentration in the bulk and that is the condition we define as inversion condition. Now, let us understand what how much these bands should bend for inversion condition right we say that this surface potential psi s psi s should be equal to 2 times the bulk potential that we had. In other words this remember bulk potential right what is the bulk potential distance between Fermi level and intrinsic level you see right here it was p type and see here what has happened intrinsic level is essentially between e c and e v intrinsic level has come below the Fermi level by the same amount phi b right. Here your electron concentration is as much as your you know bulk concentration that you have whole concentration that you have in other words your bands have bent by phi b plus phi b is that correct right your band bending has to be 2 phi b in order to reach inversion condition. In other words inversion is a condition right inversion is a gate voltage v g when your v silicon which is also what we call surface potential is 2 times phi b that is your inversion condition. Now, this is the definition of inversion right your electron concentration at the surface is as much as whole concentration in the bulk. Now, we need to find out then what is the expression for threshold voltage right. So, remember I said it is a series circuit v g drop across partly across oxide and partly across silicon correct. So, v g for the oxide drop what we say is that it is a MOS capacitor right you have an oxide in between there is some positive charge on the gate and negative charge on the substrate you take this charge which we call a depletion charge right q d divided by c ox. So, you know charge by capacitance gives you the voltage across the oxide I am sorry this is oxide voltage right because oxide is a capacitor that you have q d by c ox right. So, then in other words your v g is q d by c ox plus v silicon an important point I want to highlight the dimensions here is coulomb per centimeter square and the c ox is farad per centimeter square right. We are looking at per centimeter square capacitance and per centimeter square depletion charge unit area depletion charge. Now, also it turns out q d remember is q times doping concentration n a times depletion width w d correct. You see dimensionally n a is number per centimeter cube multiply with charge you get coulomb per centimeter cube multiply with depletion width you get coulomb per centimeter square correct that is your q d. Now, as a result of that at any given applied voltage your gate voltage is equal to q n a correct w d divided by c ox plus v silicon. As I am increasing the gate voltage you remember initially v silicon was 0 flat band condition as you start increasing the gate voltage v silicon increase slowly and accordingly more and more acceptor impurities were uncovered and depletion width also started increasing accordingly right w d also started increasing your v ox is increasing v silicon is increasing because you are increasing a gate voltage part of it drops across oxide part of it drops across silicon it is as simple as that right fine. So, what is the inversion condition now inversion happens when v silicon is equal to 2 phi b correct. So, in other words v t h is equal to this part q n a w d I reach a maximum depletion width when I reach inversion it is slowly increasing and it reaches a maximum I denote it at w d max divided by c ox plus 2 phi b where phi b is a bulk potential. So, this is essentially your threshold voltage right because this is the gate voltage that I need to apply to create electron concentration at the surface which is same as the whole concentration in the bulk because the band bending now is 2 phi b and I have ensued that electron concentration condition that I set forth to begin with. And now what is w d max you can use your simple one sided junction approximation remember that your w d is always given by 2 epsilon silicon v across a depletion region what is the voltage across depletion region it is silicon voltage because depletion region is in silicon and v silicon is the drop across that silicon voltage right. So, v silicon is the voltage across the depletion region divided by q n a correct under inversion I reach w d is equal to w d max that is when v silicon is equal to 2 phi b. So, you replace v silicon by 2 phi b here you get w d max correct that is a maximum depletion width right. So, now you can you know substitute that here and then you will get an expression for your threshold voltage which is 2 phi b then you know what you had out here q n a by c ox we will replace w d max with the equation that we just wrote right. So, what is that 2 epsilon silicon what is v silicon times 2 phi b by q n a and this in turn becomes equal to 2 phi b plus 2 phi b. This is q n a and this root q n a and this is q n a. So, what you really get is that 4 epsilon silicon q n a phi b divided by c ox. So, this is the classical threshold voltage equation that you see in any textbook right. So, you know how it came about now right very easy to understand and derive this is a condition when I have voltage drop across silicon which has ensured 2 phi b band bending and hence at the surface my electron concentration jumped up to 10 to the 15 which is exactly equal to the whole concentration in the bulk silicon which is 10 to the 15 n a. And accordingly at that juncture this is the depletion charge that I have and hence this is the voltage drop across the oxide correct. And of course in reality I started with a fictitious metal which has a work function exactly equal to silicon work function, but in reality you will not have that situation in other words you will have a non-zero flat band voltage. It is analogous to a built in voltage in your diodes that is even when you do not have any external voltage applied there is a built in field due to the fact that the Fermi level on the gate and the Fermi level on the silicon are not aligned to begin with. And hence you have that correction term in equation that you see which goes as v f b plus 2 phi b then this equation this part 4 epsilon silicon q n a phi b divided by C ox. This v f b in ideal condition is 0, but in non-ideal condition you know you just look at what is v f b v f b in general is given as phi m minus phi s which is the work function on the metal minus work function on the silicon they are not aligned to begin with. If they are same it is 0, but in addition oxide may not be ideal as well oxide may have some charges inside to begin with and that can also modulate your flat band condition. If there is some charge in the oxide which we call fixed oxide charge then also even without applying external voltage you have a built in electric field that results in band bending. So, this is your v f b this is a correction term that you will put in and you have the classical long channel v t equation. Now look at this equation this equation says that v t depends apart from v f b let us not worry about it on doping concentration. Because phi b also depends on doping concentration higher the doping concentration higher is the v t not difficult to understand because instead of 10 to the 15 per centimeter cube you started with the p type which is 10 to the 18 per centimeter cube. You need to put in more effort on the gate to convert that minority carrier concentration which is 10 to the 2 to begin with to bring it all the way to 10 to the 18 you see and hence you need to apply more voltage on the gate. Obviously it is directly proportional to the doping concentration in addition c ox remember I said c ox is per unit area capacitance which is epsilon ox divided by t ox epsilon ox is relative permittivity of the oxide times free space permittivity divided by oxide thickness that gives you far at per centimeter square I have not multiplied that with the area that is a unit capacitance which also says threshold voltage is a strong function of oxide thickness. Because eventually t ox will go into the numerator epsilon ox over t ox larger the oxide thickness more is the threshold voltage again very not difficult to you know understand larger the oxide for the same voltage field is lower. So, I need to apply more voltage to get the right field in the silicon to create that band bending. But the point is that the classical v t equation tells you that the threshold voltage of the transistor is only a function of oxide thickness that you use to build a f e t and substrate doping concentration. It does not depend on width of the transistor it does not depend on length of the transistor right because length does not appear anywhere in the equation width does not appear anywhere in the equation. In other words if I were to build transistors of different length and take them in the lab and do a I V measurement and extract threshold voltage I should get a relation between v t versus length which looks flat. Because in v t equation you do not have l term appearing explicitly right this is what we had seen when we were building bigger transistors 100 micron 50 micron 10 micron 5 micron v t was exactly flat. But as we started decreasing the length especially you know sub micron region 0.5 micron 0.2 micron when we took these transistors in the lab and started measuring the threshold voltage it no longer stayed flat as per this expectation. But instead the v t starts doing this and this is what we call short channel effect S C E for short or also referred to as threshold voltage roll off the threshold voltage rolls off. So, much so that if you really do a very small transistor this is all remember n channel transistor which should have a positive threshold voltage it could be so much. So, that your n channel transistor is always on it has such a low threshold voltage and the same thing will happen even if it is a p channel transistor again you will have a negative threshold voltage which should have been flat all the way. But look no longer the case starts rolling off v t h starts decreasing for p channel transistors also right whether n channel or p channel does not matter v t decreases with decreasing length and this problem is very severe when we talk of 100 nanometer sub 100 nanometer transistors right. So, let us first understand you know why is this v t roll off and in order to understand that we just need to look at the picture that we have. We started with this n plus n plus region and this p region in a long channel transistor and now we are looking at a very short channel transistor n plus and p region. Remember whenever you have n plus p junction there is so called built in potential. In other words there is going to be a depletion region already even without applying any voltage external voltage right you know you have v g is equal to 0 because there is a p n junction there is already a built in potential and some of the region here right just at the edge of source and drain region is already depleted. Remember what do I need to do invert this transistor it is heavily peeped out I need to decrease the whole concentration I first need to create a depletion region remember our discussion earlier that is when the whole concentration is decreasing electron concentration is slowly increasing, but both electron and whole concentrations are much lower than the impurity concentration that is why we call it depletion region right because your n can be 10 power 10 p can be 10 power 10. So, your n p is equal to n i square, but you see both n and p are much smaller compared to 10 to the 15 which is my impurity concentration right that is what we call a depletion region, but nonetheless you see in the depletion region source and drain have already helped you to do some work because they have helped you to bring the electron concentration from 10 to the 5 which was a concentration in p type region to 10 to the 10. You need to do some extra work to bring it all the way to 10 to the 15 right because when I am talking of inversion I am talking of inverting this entire channel part of the channel entire channel has to first go through depletion and go to inversion, but the part of the channel is already depleted because of the built in potential from source and drain except that when the transistor is very long you see this depletion region is so small it is so minuscule compared to the total length of the transistor right. So, it really does not matter whether a very very small you know 0.1 percent or even smaller fraction is already depleted by source drain built in potential has no consequence because you still have such a large volume to be depleted and inverted, but when I scale the transistor you see now the depletion region can be a significant fraction of your channel length you see right. So, now I can no longer ignore this you know in other words your gate need not put in so much effort to invert the channel because source and drain have already helped you to invert the channel you see they are partly helped you right. And when you miniature as a transistor further depletion region becomes even significant fraction of the your channel length and hence you just need to apply much lower voltage not this voltage only this voltage to invert because 10 percent of the charge you know that is required here is supported by source and drain and here may be 50 percent of the charge is supported by source and drain region right because the transistor length is going down further depletion width is not changing depletion width is same for all length transistor because it is only dependent on the doping concentration correct and this is the reason for short channel effect. The fact that it is a 2 D device not just a 1 D device that we saw although it is a 2 D device when the lengths are very large I can make an 1 D approximation, but when the lengths are very small I cannot make that approximation and hence I do not need to apply so much gate voltage to invert the transistor and hence your threshold voltage is lower go to even smaller transistor your threshold voltage is even lower and hence lower the channel length lower is the threshold voltage. So this is essentially what is the reason for the short channel effect the source and drain built in potential already help you to invert the transistor when that region is significant fraction of your transistor which happens when the transistor length is small you have a lower threshold voltage because I do not need to you know put in so much effort to invert the transistor and in fact this is really explained with a very very simple model that Yaw and his co workers gave right you know this is what is called a charge sharing model let us suppose I have a transistor which has a source and drain region and we typically you know this is my junction depth xj this is n plus region and similarly here this is xj ok and this is also n plus region this is xj ok. Now typically when we talk of inversion right this is the transistor that we have you apply voltage right and this is the region where you are creating depletion correct this is your depletion width ok this let us say Wd Wd max under inversion condition ok Wd max is not necessarily equal to xj you know I am just do not they are not to scale here ok do not worry about that too much right. So, this is the depletion width which extends something like this wherever you have ok this depletion width extends like this and this is your length of the channel right typically your gate needs to support this entire charge ok this depletion charge now what we say is that part of the charge here in this triangle is supported by drain junction and part of this charge here is supported by the source junction and this is why we call a charge sharing model right there is this depletion charge that needs to be created first not entire depletion charge is supported by the gate part of that is supported by the built in voltage that you have here between the n plus p junction and other part is essentially supported you know by this region right. So, now in other words this when we remember when we did the Vth what was Vth 2 phi b plus Qd by C ox that Qd was essentially the charge in this rectangle that is what we had assumed earlier and that is indeed true when this is really large you see because these triangles are insignificant compared to the large region that we are looking at ok, but these triangles are no longer negligible compared to this region that we are looking at right. So, the Qd is not entirely supported by the gate only part of that it can be said that the charge in this trapezoid is supported by the gate and the charge in these two triangles are supported by the source and the drain ok. So, that is what we need to do right. So, in other words there is this delta right this is the delta this base of the triangle is what we are calling delta here and this of course you know the junctions are shown like this just to sort of you know drive home the point that when you actually build a transistor the junctions are made using diffusion and when you do the diffusion junctions actually spread laterally right. In fact, the exact picture of the transistor should look like this right this whole thing here is gate and this is your oxide here Si O 2 you do the implantation of the impurities and impurities and they diffuse when they diffuse they also diffuse laterally right. A simple approximation is that if you have a x j as a junction depth they essentially go as a radius which is x j laterally right. There is more lateral diffusion here as you start going down there is less lateral diffusion right and hence junctions have this approximate shape that is why we have that ok. And you know what we are looking at now is that this is if you look at this triangle that we have this triangle here is this is delta and this is x j and this is w d max and this one here is really x j plus w d max ok. So, now you can because this is x j and this is the depletion width that you have that is the w d max that you have this is the triangle that I am looking at this triangle this is the hypotenuse of the triangle which is x j plus w d max and this is w d max and this is delta plus x j what I am trying to get at is really what is delta if I find out what is delta then I can tell you exactly what is the change in threshold voltage how much did the threshold voltage decrease because of the charge sharing phenomenon that we are talking about ok. In other words what we can say here is that you know your q d by c ox term needs to be modified this second term only take that second term q d by c ox ok 1 over w l where w d max l where l is the length of the transistor and w d max is the depletion width that I have right here right the w d max times l minus the area of the two triangle. The fraction of the area that which is a trapezoid area really that needs to be supported by the gate ok. So, let me just rewrite that here just to avoid that mess right I had this q d by c ox here then w d max times l right l minus there are two triangles area of each triangle what is the area of each triangle right delta times the height which is w d max delta times w d correct. Now this is really the area what I am saying is that I am waiting q d by c ox ok by this fraction which is essentially because it is not you know the entire rectangle that is supported in the case when delta is equal to 0 as you can see this w d max l cancels with w d max l and that reduces to your classical v t equation which we had derived orally right only when this delta is becoming comparable to the l right and then it becomes important to consider this. In other words you can rewrite this c ox times w d max l w d max l into 1 minus ok. So, what you get here is delta over l because this is w d max this is w d max remember that right correct. So, what you have the second term in your v t is really q d over c ox into 1 minus delta divided by l as you know when delta is very very small compared to l this term can be completely ignored and that reduces to your classical equation. But when delta starts becoming comparable to l right in other words we are decreasing l you see when we are looking at different length transistor l is coming down very drastically and then at some point l starts becoming comparable to delta then I need to take this 1 minus delta over l term and as l starts decreasing you know the change in v t becomes more and more and the fact that your v t is decreasing with respect to l as we saw in the in the plot here is very well captured now by this simple model that says when l is decreasing further there is much more degradation in threshold voltage threshold voltage also starts decreasing. Now, what you can do I will leave that as an exercise you can go back and do this exercise yourself you know you take this you write the equation essentially as w d max square plus delta plus x j whole square is equal to x j plus w d max whole square and now simplify this equation further and further and eventually you will arrive at an expression which will give you the expression for delta. So, the expression for delta will essentially come I will not really derive this you can actually write using that expression that I had you can actually derive that it goes as 1 plus 2 w d max by x j minus 1 this is how the expression goes for delta. So, delta if your x j is small delta is also small and it turns out if your doping concentration is large your delta is also small so that is very important to recognize and qualitatively what we are saying essentially is that if I have this transistor this is junction depth x j and this is doping concentration. If your junction depth is small that is good for short channel effect meaning your v t does not decrease as much another way to think about is that you know short channel effect comes essentially because of two dimensional effect two dimensional effect meaning the drain starts influencing the channel deeper the drain more region of the channel is influenced by the drain shallower the drain it will not influence that bigger region of the channel this is another qualitative intuition that you can have similarly if you have very high doping concentration delta itself is small because high doping concentration will not let this depletion width spread so easily into this region if delta itself is small then you start seeing short channel effect at much lower channel length. In other words what I am trying to tell you is the following if you look at transistors with different designs let us say there is one transistor which shows a roll off which looks like this this is threshold voltage as a functional channel length. Let us say this has a junction depth of x j one I create a new transistor again different length transistors I measure experimentally in the lag if the junction depth is smaller x j two such that x j two is less than x j one x j two will not roll off as fast as x j one in fact this is also giving you intuition to design transistors if you want a better short channel behavior better roll off you do not want the v t to decrease as much you better design very shallow junction you figure out how to minimize diffusion of impurities in your source and drain junction then you can build a better transistor similarly if you have two different transistors and one transistor which has a roll off with n a one and I create another transistor which has higher doping concentration which is n a two that will probably have a roll off which looks like this n a two remember there is little difference that I have shown compared to this graph whereas, the two transistors had the same v t for long channel transistors but here if you increase doping concentration remember the classical v t equation which says for a long channel transistor if you have larger n a you should get larger threshold voltage right and that is why even when the transistor length is long like 10 micron you have much higher v t and this is a condition n a two greater than n a one. So, this has really given us some insight into really engineer the transistor. So, let me then summarize right so threshold voltage as you know is very important consideration in the transistor MOSFETs classical threshold voltage equation based on one d approximation says it only depends on doping concentration and the oxide thickness these are the only governing factors not on length of the transistor. But all of a sudden when we started building shorter transistor we actually measure the v t and we saw that the v t is no longer as predicted and that is because of the 2 d effect and a very simple model is a charge sharing model given by Yao and that also gives us some insight in designing the transistor. Let us stop the lecture here and we will continue in the next lecture.