 Hello and welcome to this presentation of the Advanced Control, General Purpose and Basic Timers embedded in STM32 microcontrollers. It covers their main features, which are useful for handling any timing-related events, generating waveforms and measuring the timing characteristics of input signals. The STM32 embeds multiple timers providing timing resources for software or hardware tasks. The software tasks mainly consist of providing time bases, timeout event generation and time triggers. The hardware tasks are related to IOs. The timers can generate waveforms on their outputs, measure incoming signal parameters and react to external events on their inputs. The STM32 timers are very versatile and provide multiple operating modes to offload the CPU from repetitive and time-critical tasks while minimizing interfacing circuitry needs. All STM32 timers are based on the same scalable architecture. Once the timer-operating principles are known, they're valid for any of the timers. This architecture includes interconnection features and allows several timers to be combined into larger configurations. Lastly, some of the timers feature specific functions for electrical motor control and digital power conversion, such as lighting or digital switched power mode supplies. Here are the key features of the STM32 timers. All timers are based on the same architecture and are available in several derivatives listed later in this presentation. The timers mainly differ in the number of inputs and outputs they have, from a minimal timer with two IOs, such as Tim14, to an advanced control version with 10 IOs, such as Tim1 and Tim3. Two slides at the end of this presentation list the features supported by each timer present in the STM32C0. Some features may not be present on the smallest timer derivatives, for example, DMA, synchronization, and up-down counting modes. Most of the timers can be linked and synchronized to build larger time-based timers, have a higher number of synchronous waveforms, or handle complex timings and waveforms. Within a timer, each and every channel can be configured independently as an input, typically for capture, or as an output, typically for a PWM. The timers can serve as a trigger for other peripherals, for instance to start ADC conversions or to monitor the internal clocks, thanks to the interconnect matrix. The clock and synchronization unit provides the reference clock to the timer kernel called CKPSC. The counter clock can be provided by the following clock sources. The internal clock or CKINT, external clock mode 1, external input pin, counting each rising or falling edge on a selected input or internal triggers, external clock mode 2, external trigger input ETR or triggers, and coder mode based on TI1-FP1 and TI1-FP2 coming from the channels. ETR is a trigger that can be asserted by ADC analog watchdogs, comparators, or Team 1 ETR input pin. ITR is a trigger that can be asserted by another timer. Internal trigger in and out are connected to the interconnect matrix referred to the related presentation. A rising edge of the selected trigger input or TRGI sets the TIF flag. When one timer is configured in master mode, it can be reset, start, stop, or clock the counter of another timer configured in slave mode. Timer 1 supports 6 independent channels for input capture, accept channels 5 and 6, output compare, PWM generation, edge and center aligned mode, one pulse mode output. When a capture or compare event occurs, the corresponding CCI flag is set. Shown on the left are the input stage and the input conditioning circuitry while on the right we have the output stage. Note that TI1 channel 1 to 4 pins appear on both sides to indicate they're both input and output capable. Channels 1 to 4 can be output on pins while channel 5 and 6 are only available inside the microcontroller, for instance for compound waveform generation or for ADC triggering. The timer 1 supports break inputs that can be used to automatically set the channel outputs in a predefined state whenever a break event occurs. The timer 1 also supports a dead time generator unit or DGG that inserts a dead time on PWM complementary outputs of channels 1 to 4. The purpose of the break function is to protect power switches driven by PWM signals. The two break inputs are usually connected to fault outputs of power stages and three phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state. A number of internal microcontroller events can also be selected to trigger an output shutdown. Regarding timer 1, the break features two channels. A break channel which gathers both system level fault, clock failure, parity error etc. and application fault from input pins and built-in comparator and can force the outputs to a predefined level either active or inactive after a dead time duration. A break 2 channel which only includes application faults can force the outputs to an active state. Timer 1 and timer 3 feature multiple clocking options. The clock and synchronization unit also responsible for timer chaining handles the clock for the counter. The default clock comes from the reset and clock controller or RCC. This timer clock ckint is the APB clock possibly multiplied by 2. External timer clocking makes it possible to count external events or to have a counting period externally adjusted. The clock source can be provided by other on-chip timers using one of the four internal trigger inputs, ITR 0 to ITR 3. Input pins 1 and 2 can also serve as external clocks with the option of including digital filters to remove spurious events. The external trigger input or ETR can be configured as an external clock with a digital filter, programmable edge sensitivity and a first basic prescalar stage to reduce the frequency of incoming signals as needed. The TI1FED edge detector input can also be used as the timer clock. A pulse is generated on both rising and falling edges of the TI1F signal. Although it was not intended for this, it can serve as a frequency doubler with an external clock, it counts twice per incoming clock period. Lastly, the quadrature signals from an encoder can be processed to provide a clock and a counting direction as described later in this presentation. This slide explains how to adjust the timer counting period. Each timer embeds a linear clock prescalar which divides the clock by any integer between 1 and 65,536. The counting pace can therefore be precisely adjusted. For instance, a division by 48 will yield a precise 1 MHz counting rate when the APB clock is 48 MHz. The auto reload register defines the counting period. In down counting mode, the counter is automatically reloaded with a period value when it underflows. In up counting mode, the counter rolls over and is reset when it exceeds the auto reload value. In center aligned mode, up and down counting, the counter counts from 0 to the auto reload value minus 1, generates a counter overflow event, then counts from the auto reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. An update event is issued when the counter underflows or overflows and a new period starts. It triggers an interrupt or DMR request that is used for adjusting timer parameters synchronously with its period which is useful for real-time control. This update event triggers the transfer from preload to shadow registers for multiple parameters, in particular for the clock prescaler, auto reload value, compare registers and PWM mode. A 16-bit programmable repetition counter allows you to decouple the interrupt issuing rate from the counting period and have, for instance, one interrupt every single, second, third and up to 65,536 PWM period. This is particularly useful when dealing with high PWM frequencies. Regarding the STM32C0 microcontroller, the repetition counter is only implemented in timer 1, 16 and 17. Some of the STM32 timers feature up and down counting modes, the advanced control timers 1 and the general purpose timers 3. The counting direction can be programmed by software or automatically managed by the timer in center-aligned PWM mode. In this mode, the counting direction changes automatically on counter overflow and underflow. For a given PWM switching frequency, this mode reduces the acoustic noise by doubling the effective current ripple frequency, thus providing the optimum trade-off between the power stages switching losses and noise. The counting direction can also be automatically handled when the timer is in encoder mode. Quadrature encoders are typically used for high-accuracy rotor position sensing in electrical motors or for digital potentiometers. From the two outputs of a quadrature encoder sensor, also called an incremental encoder, the timer extracts a clock on each and every active edge and adjusts the counting direction depending on the relative phase shift between the two incoming signals. The timer counters thus directly holds the angular position of the motor of the potentiometer. The simplest use case for a timer is to provide an internal timebase. This is commonly used by software routines, either to provide periodic interrupts or single shot timeout protection. The timer can also provide periodic triggers to other on-chip peripherals such as the ADC and other timers through the interconnect matrix. The update event from the timer, typically on counter overflow, is the usual means to have a software timebase interrupt or to trigger a periodic event. It's also possible to generate internal timings using any other timer, using compare events or using the trigger outputs on any other timer. Multiple timing events can be generated with a single timer using multiple compare channels. This slide describes the input capture features. Channels 1-4 can be individually configured as input capture with a number of signal conditioning options. An input can be mapped on two capture channels, typically to differentiate rising edge from falling edge capture, see the figure on the top right. TRC input can be chosen as the capture trigger. It's connected to one of the ITR inputs, timer to timer interconnect. The edge sensitivity is programmable and can be rising edge, falling edge or both edges. An event pre-scaler allows capture of one event every two, four or eight events. This decreases the CPU burden when processing high-frequency signals and allows the measurement to be more accurate since it's performed over multiple input signal periods. Spurious transition events due to noise or bounces can be removed using a programmable digital filter. The figure shows how a signal is filtered out when the filter acceptance is set to four. In the upper case, a clean rising edge capture is triggered four sampling periods after the rising edge as one can notice looking at the internal counter value. In the lower case, a glitch causes the filter counter to be reset and a capture to happen after four successive samples at high level have been counted. Once the capture trigger is issued, the timer's counter is transferred into the capture register and an interrupt or DMA request can be issued. If a new capture occurs before the previous one has been read, the capture register is overwritten and an over-capture flag is set for the software to manage this condition if needed. This slide presents some of the more advanced capture-related functions. The clear-run capture mode causes a counter reset immediately after the capture has been triggered. This allows a direct measurement of the period while a traditional free-running counter would require additional computation to obtain the period following the trigger. In PWM input mode, the timer is able to capture both the period and the duty cycle of an incoming PWM signal. The input signal is internally routed to two capture channels. The signal's rising edge is captured on input capture 2 to provide a period value with a clear-run capture mode. The falling edge is captured by the capture 1 channel, which provides the pulse-length duration. The duty cycle then simply corresponds to the ratio between input capture 1 and input capture 2. Lastly, the timer includes an XOR function to combine the three input channels with XOR logic. This is typically used to handle the three 120-degree phase shifted signals coming from the whole sensors in electrical motors. This allows a clear-run capture event happening on each and every edge of the three signals and have a capture value directly usable for speed regulation. This slide presents the output compare features. A compare event is generated when the counter matches the value of the compare register. This event can trigger an interrupt or DMA request and can be reflected on the corresponding output pin by an output set, output reset or output toggle. The compare register can be preloaded. The preload must be disabled if multiple compare values must be written during accounting period. In the timing diagram, preload is disabled. On the contrary, the use of preload mode must be preferred for applications with real-time constraints since this gives a high time margin for the software to update the compare register with the next value. The transfer from the preload to the active value is triggered by an update event when the counter overflows or underflows. The output compare mode can also be preloaded so as to allow glitch less transition from a PWM mode to a forced on or off state, for instance. One pulse mode is used to generate a pulse of a programmable length in response to an external event. The pulse can start as soon as the input trigger is detected or after a programmable delay. The compare1 register or CCR1 value defines the pulse start time while the autoreload register or ARR value defines the end of pulse. The effective pulse width is then defined as the difference between the ARR and CCR1 register values. See the upper timing diagram. The waveform can be programmed to have a single pulse generated by the trigger or to have a continuous pulse train started by a single trigger. One pulse mode also offers a retrigable option. The timing diagram at the bottom of this slide highlights this option. A new trigger arriving before the end of the pulse will cause the counter to be reset and the pulse width to be extended accordingly. Note that only timers 1 and 3 support the retrigable one pulse mode in the STM32 C0 microcontroller. This slide presents some of the PWM modes. The standard edge-aligned PWM mode is programmed with the autoreload register defining the period and the compare register defining the duty cycle, the counter being in up-only or down-only counting mode. A single timer can generate up to 6 PWM signals with independent duty cycles and identical frequency. When multiple PWM waveforms are generated by the same timer, all falling edges occur at the same time, hence the term edge-aligned. On the contrary, the rising and falling edges of center-aligned PWMs are not synchronized with the counter rollover, so that switching time varies with the duty cycle value. This is achieved by programming the counter in up-down mode. This mode spreads the switching noise when multiple PWMs are generated with the same timer. This is a key feature for three-phase PWM generation for electric motor drives, since it allows you to double the frequency of the current ripple for a given switching frequency. For instance, a 10 kHz PWM will generate a notable 20 kHz current ripple. This minimizes the switching losses due to the PWM frequency while guaranteeing silent PWM operation. A variant of the center-aligned mode is the asymmetric PWM mode, where two compare registers define the turning on and off of the PWM signal. This provides higher resolution for pulse width setting, since turn-on and turn-off times are individually defined. It also allows the generation of phase-shifted PWM signals necessary to drive DC-DC converters based on the full-bridge phase-shifted topology. In the bottom-right timing diagram, the timer provides two PWM signals with identical frequency, 50% duty cycle, and a phase shift varying from 0 to 180°. This slide presents the combined PWM modes. This mode allows a logic combination of two PWM signals to be generated by adjacent channels, the output compare 1 and 2, or the output compare 3 and 4. The PWMs can be ordered and ended to create complex waveforms. Typically, this allows to have two periodic pulses generated with any pulse width and any phase relationship value. Combined three-phase PWM mode allows one-to-three center-aligned PWM signals to be generated with a single programmable signal entered in the middle of the pulses. This mode specifically targets three-phase motor control applications. In this case, channel 5 of the timer can be combined with any of the three channels, one, two, and three, to insert a low-state in the middle of a centered pattern PWM signal. This mode greatly simplifies the implementation of low-cost current sensing techniques for three-phase motor control using a technique usually referred to as zero vector insertion. This slide presents some more specific PWM modes where either the frequency or the duty cycle can be driven by external signals. The timer can provide variable frequency signals using an external reset signal connected either on the ETR or on the channel 1 or 2 inputs. The purpose of this mode is to provide a signal with a fixed on or off time and a continuously adjusted frequency controlled by the hardware. The timer provides control for the on or off time using the compare register while the auto reload register guarantees that the PWM will not stop if the external reset is missing, thus providing a safe control in boundary conditions. This technique is used for a variety of purposes such as transition mode power factor controller or PFC for mains supply duplications and current controlled digital LED lighting. Another mode for the timer is to have the duty cycle controlled by hardware with either an on-chip comparator or enough chip signal. The PWM operates at the fixed frequency, the maximum duty cycle is set by the compare register and the actual value controlled cycle by cycle. This is used for applications requiring current controlled PWMs typically for driving DC motors or solenoids. In this case, a comparator monitors the peak current value into the load. As soon as the current exceeds a programmed threshold, the comparator resets the PWM output which is then automatically restarted at the next PWM period thus providing a controlled peak current value. This slide presents the timer synchronization features. The trigger controller can cascade multiple timers in a master slave configuration. A timer can control one or more timers as the master timer or can be controlled by another timer as a slave. The clock and trigger controller acts as a link between the timers. In master mode, it can redirect outside the timer multiple internal control signals to a non-chip TRGO trigger output. In slave mode, it gathers multiple inputs on the TRGI coming from the external trigger pin or from one of the four internal trigger inputs, ITR1 to ITR4, connected to the other TRGO outputs. Additionally, the input capture one and two pins can also be used as an internal trigger typically to reset the counter. Slave and master modes can be programmed independently. A given timer can thus simultaneously be operating in slave and master modes in a cascaded configuration accepting input triggers or providing output triggers. Master synchronization and slave synchronization are independently instantiated in the timer units. See the table at the end of this presentation summarizing the capabilities of all STM32 C0 timers. This slide lists the various operating modes and the signals exchanged between timers. In master mode, 16 options are given for selecting the trigger to be sent on the TRGO output. The output can be a single synchronization pulse issued upon counter reset, counter enable which corresponds to the counter start, the update event or the compare one match event. Alternatively, the TRGO output can also transmit one of the six waveforms generated including PWM signals to the other timer modules, the compare on channel 1 to 6 and compare pulses on all channels. In slave mode, the timer operating mode is controlled by the TRGI input. In triggered mode, the counter start is externally controlled. This mode is used for simultaneously starting multiple timers. In reset mode, the counter is reset by rising edge on the TRGI input typically for variable frequency PWM operation. A combined mode including reset and trigger can be used for re-triggerable one pulse mode generation. In gated mode, shown in the timing diagram, the counter is active only while the level on the input signal is high. A combined mode including reset and gated can be used to detect out-of-range PWM signal, i.e. duty cycle exceeding a maximum expected value. The external clock mode too can be used in addition to another slave mode except external clock mode 1 and encoder mode. In this case, the ETR signal is used as external clock input and another input can be selected as trigger input. Lastly, the slave mode selection includes clock-related modes such as quadrature encoder decoding or external clocking modes mentioned earlier in this presentation. This slide gives two examples of synchronized operation. The first example shows how two timers can be simultaneously started. A mechanism allows the master timer to start slightly delayed to compensate for the master slave link delay and have all timers synchronized with cycle accuracy. By combining the channels of timers 1 and 3 as shown, it's possible to have up to 8 synchronized PWM channels. The second example shows how to create a 32-bit timer by cascading two 16-bit timers. Here, the update event generated on counter rollover as the input clock for the following slave timer so that timer 3's counter holds the least significant 16 bits, timer 1's counter holds the upper bits, bit 16 to 31. This slide summarizes the timer's four main electrical motor control features. The timer includes specific PWM modes for controlling power switches. In addition to center-aligned and combined three-phase PWMs previously described, the timer features dead time insertion for complementary PWM generation and six-step mode for driving brushless DC motors. It includes power stage protection circuitry with a dual-level emergency stop mechanism to disable the PWM outputs by hardware in case of a fault. It's able to handle the most common sensors found in motor control systems. Quadrature encoders and hole sensors are used for fine and coarse position feedback while tachometer generators are used for cost-effective speed feedback and just require a clear and capture mode. Lastly, the timer includes synchronized ADC triggering options necessary to properly manage voltage and current sensing and avoid any acquisition issues due to switching noise in power stages. This slide presents the dead time insertion function. A hardware dead time generator provides two non-overlapping complementary PWMs from a reference PWM signal. The STM32 timers include up to three dead time generators for OC1, OC2 and OC3 channels. The dead time duration is programmed with an 8-bit value. This value can be locked by the user to prevent this critical value from being corrupted during runtime. This is done by setting a right once-lock bit which switches the dead time register into read-only mode until the next microcontroller reset. Dead time insertion is necessary when driving half bridges where a pair of transistors are connected in series between two power rails. In this case, a delay must be inserted before the switch on of one slide to allow the other side to switch off taking into account physical switching characteristics. Half bridges are usually found in DC-DC converters for DC or stepper motor drive using the full bridge topology shown here or for three phase inverters with three PWM pairs. This slide shows how the six-step drive, also called block commutation, is managed with the STM32 timer. It consists of chaining two timers, one handling the three-hole sensor signals while the other manages the PWM generation synchronized with the rotor angular position generating six successive steps. The first timer operates in clear-on-capture mode triggered by the three inputs. A compare register here compare two is responsible for adding a programmable delay between the raw angular position and the commutation time. Refer to CCR2 in the left timing diagram. The captor register 1 holds the timing interval between successive hole sensor edges and is necessary for the speed regulation loop. The compare two match event is propagated to the slave timer through the TRGO output. These events serve as commutation events and trigger changes for PWM generation. For each of the six steps of the sequence, the states of the six outputs are defined to be either forced active or inactive or generating a PWM signal. The transition from one step to the other is preloaded by software in the commutation-interrupt routine and automatically transferred by hardware to reprogram the output operating mode when the next commutation arrives. The figure at right shows the six PWM signals for two consecutive complete six-step sequences together with the current in one of the motor phases. This slide introduces the break function. A break event triggers a hardware protection mechanism that automatically disables the PWM outputs and forces them to a user-configurable state either low impedance with high or low level or high impedance. The logic circuitry works asynchronously without any clock. This guarantees the functionality even in case of a system clock failure and avoids any clock-related propagation time that would tend to delay the protection. This feature is available on all timers having complementary PWM outputs which are capable of performing power conversion tasks timers 1, 16 and 17. Timer 1 has two separated break channels while timers 16 and 17 support a unique break channel. Supporting two break channels provides a dual level protection scheme where for instance a low priority protection with all switches off can be overridden by a higher priority protection with low side switches active. Furthermore, a dead time delay can be inserted immediately before entering the fault mode for safely disabling the power stage. This prevents potential shoot-through conditions. Let's consider for instance that the fault occurs when the high side PWM is on while the safe state is programmed to have a high side switched off and low side switched on. At the time the fault occurs the system will first disable the high side PWM and insert a dead time before switching on the low side. This slide describes the break function related to the BRK input. Multiple break sources can be combined for triggering a break event. A system break request results from serious errors detected in the microcontroller, CPU lockup, run parity error and loss of clock. The lock signals are right once enabled bits located in the CIS-CFG peripheral. They are reset by default, fault error is masked. Once set, fault detection is enabled it cannot be reset unless the whole microcontroller is reset for functional safety. An application break request results from a board failure. Break inputs can also be selected with the alternate function controller on the microcontroller pinout. External sources can be conditioned before entering the break detection unit in order to select the proper polarity and discarding of spurious glitches by means of a digital filter. Software is also capable of requesting a break, typically when diagnosing a non-recoverable error condition. When one of these break requests occurs an interrupt or DMA request is asserted in addition to set the PWM outputs in a safe state. This slide describes the break function related to the BRK2 input. Unlike the BRK input, the BRK2 event cannot be caused by CPU lockup, RAM parity error and loss of clock. The STM32C0 implements a bidirectional break feature. The break IO pad is used to report board level failure but can also be used as an output to signal an MCU internal failure. The bidirectional mode is available for both the break and break 2 inputs and requires the IO to be configured in open drain mode with active low polarity. A global break information detected inside the STM32C0 can therefore be output to other CPUs or gate drivers. Internal break sources and multiple external open drain comparator outputs are all together to trigger a unique break event when multiple internal and external break sources must be merged. This slide explains how to arm and disarm the break circuitry. The bidirectional mode is active when the BKXBID bit is set. X means BK or BK2 break signal. Since the break IO pad is bidirectional, a low level on the break input triggers a break which enforces a low level on the same pad. Therefore, a disarming mechanism is required to exit the break condition. The main output enable or MOE bit is relevant when a channel is configured as an output. It's cleared asynchronously by hardware as soon as one of the break inputs is active to disable OC and OCN outputs. The following sequence should be used to rearm the protection after a break event. The BKDSRM or BK2DSRM bit must be set to release the output control. The software must wait until the system break condition disappears if any and clear the SBIF status flag or clear it systematically before re-arming. The software must pull the BKDSRM or BK2DSRM bit until it's cleared by hardware when the application break condition disappears. From this point, the break circuitry is armed and active and the MOE bit can be set to re-enable the PWM outputs. This slide presents the ADC triggering options related to the timers. The ADCs can be triggered with Timer 1 and Timer 3 outputs as indicated in the table. This can be done using compare events. The ADC conversion will start on a given compare match. This applies to Timer 1 channel 4. The TRGO event can also be used. This gives extra flexibility since the TRGO can be any of the compare events or timer internal control signals such as register update, counter reset or trigger input. On the other hand, this prevents the TRGO from being used for synchronization purposes. For this reason, Timer 1 also has an additional TRGO 2 output fully devoted to ADC triggering. TRGO 2 offers 16 possibilities including the 6 compare events and the possibility to have a dual trigger per PWM period by combining the compare 4 and 6 events as shown in the figure or compare 5 and 6 events. This also leaves the TRGO free for multiple timer synchronization schemes. This slide presents an example of PWM synchronized ADC trigger. For 3 phase motor control, it's mandatory to have ADC readings synchronized with the PWM generated for controlling the power stage. This allows extraction of the average value out of the current waveform ripple and makes sure the ADC reading is done at an adequate distance from the ringing due to the power switches. Shown here on the left is a 3 phase motor inverter. The 6 switches are controlled by 3 complementary PWM pairs with dead time inserted while the current in the motor windings is measured using shunt resistors placed in the 3 half bridges bottom side. The right side shows the timer's counter compare 1 and compare 2 values and corresponding PWM outputs for the low side switches controlled by CH1N and CH2N. The 2 bottom waveforms represent the current in the motor phase and the image of this current obtained on the shunt resistors. With this low cost topology the voltage can only be measured when the low side switches are on which explains the square wave shaped signal obtained on the ADC input. In this case, the ADC trigger is generated on the counter rollover. This allows the reading to be done precisely in the middle of the period and get the average value of a signal with significant ripple. Additionally, using a PWM synchronized ADC trigger also guarantees that the ADC conversion will be done away from the ringing noise present on the shunt voltages. This slide lists the interrupts and DMR request sources. Most events are able to generate either an interrupt or a DMR request and even the two simultaneously. The update is issued when the counter overflows or underflows. It's mainly used to refresh the timer's runtime settings at the beginning of the PWM period and maximize the interval before the next register update. The repetition counter allows you to skip some PWM periods and decrease the number of interrupts or DMR requests at high PWM frequency. Each of the six captor compare events have their own interrupt. Only channels 1 to 4 can trigger a DMR transfer. A trigger event on the TRGI input regardless of the trigger source can also trigger an interrupt or DMR request. Lastly, additional sources of interrupts and DMR requests are the commutation and break events on timers 1, 16 and 17 only. The timer includes a DMA burst mode to have multiple registers reprogrammed with a single DMA stream. This allows the modification of several runtime parameters simultaneously, for instance, duty cycle and frequency of several channels or dynamically change the timer configuration by writing the configuration registers. The example shows how a table containing three compare values can be transferred into the compare registers with a single DMA burst when a new PWM period starts. The DMA must be programmed in memory to peripheral mode pointing to a unique location in the timer. When the update event occurs, the timer sends a number of DMA requests corresponding to the programmed burst length. Each value is then automatically redirected from the virtual register into the targeted active register. On the next update event, three new compare values are transferred again. In this example, this mechanism saves two DMA streams that would normally be necessary for such an update scheme. This table indicates the state of the general purpose timers or GPT according to the current microcontroller power mode. In run and sleep modes, the general purpose timers are active. In sleep mode, GPT interrupts can be used as wake-up events. In stop mode, the general purpose timers are frozen. The peripheral register content is kept. No reconfiguration of the GPT is needed when exiting these modes. In standby and shutdown modes, the general purpose timers are powered down and must therefore be reinitialized upon exit of these modes. The timer's state in debug mode can be configured with one configuration bit per timer. If the debug bit is reset, the timer clock is maintained during a breakpoint. If the debug bit is set, the timer's counter is stopped as soon as the core is halted. Additionally, the outputs of the timers having complementary outputs are disabled and forced into an active state. This feature is extremely useful for applications where the timers are controlling power switches or electrical motors. It prevents the power stages from being damaged by excessive current or the motors from being left in an uncontrolled state when hitting a breakpoint. This slide explains how to set the timer's PWM frequency. This parameter is defined using the auto-reload value, or ARR, programmed in the TimxAR register and the clock prescaler in the TimxPSC register. The PWM frequency is given by the timer operating frequency fTim divided by ARR plus 1 times the clock prescaler plus 1. Practically, finding both register values is an iterative process where one must start from PSC equals 0, i.e. no clock division. This guarantees that the PWM will have the finest possible resolution. In this case, the ARR value is simply the ratio between the timer clock frequency and the PWM frequency, the whole minus 1. If this equation yields an ARR value above the timer's ARR range, either a 16-bit or 32-bit value depending on the selected timer, the computation must be redone with a higher prescaler value with the following sequence. An ARR value equal to timer clock frequency divided by 2 over the PWM frequency, the whole minus 1. Then, an ARR value equal to timer clock frequency divided by 3 over the PWM frequency, the whole minus 1, and so on, up to the point where the ARR value fits within the programmable range. This slide explains how to program a duty cycle for a given PWM frequency. This parameter is defined using the autoreload value, or ARR, programmed in the Timx ARR register and the compare value programmed in the Timx CCRX register. The duty cycle doesn't depend on the PWM frequency and is given by the compare value over the autoreload value plus 1. Another useful indication is the PWM resolution. This gives the number of possible duty cycle values and indicates how fine the control on the PWM signal will be. The resolution expressed in number of duty cycle steps is simply equal to the ratio between the timer clock frequency and the PWM frequency when the clock prescalar PSC is null. When the clock prescalar is not null, the resolution is the ratio between the timer clock frequency and the ARR plus 1 value. Another way of expressing it is in bits, as for giving a DAC converter output resolution. In this case, the resolution is the base 2 logarithm of the ratio between the timer clock frequency and the PWM frequency when the clock prescalar PSC is null. When the clock prescalar is not null, the resolution is base 2 logarithm of the ratio between the timer clock frequency and the ARR plus 1 value. This slide shows a simple practical example of PWM usage for dimming a low power LED. This can be done directly using a PWM output as long as the current doesn't exceed the rated output current. The first step is to program the frequency to be set to 1 kHz. When doing the ARR value computation with no prescalar and a timer operating frequency of 128 MHz, the result is 127,999 which is above the 16-bit range that can be used with timer 1. The timer prescalar must be set to 1 to have the timer operating at 64 MHz and this results in a valued value of 63,999 for the ARR register. The second step consists of computing the compare register value to have a 20% duty cycle. This yields a value of 12,799. Lastly, the dimming resolution can be computed from formulas presented in the previous slides. With a timer running at 64 MHz, a 1 kHz PWM provides 64,000 dimming steps which corresponds to an equivalent resolution of 15.9 bits. This slide explains a common support case where the whole timer is configured, the counter is started, the PWM mode is enabled as well as the corresponding outputs but still there's no activity on the pins. Usually this is because the MOE bit or the CCXE bit wasn't set. The CCXE bit in the TimxCCER register defines a configuration of a CCX channel as input or output. The CC1E bit must be set to get a PWM signal on the CH1 channel. For timers equipped with dead time generators, timers 1, 16 and 17, a main output enable or MOE bit in the TimxBDTR registers controls all outputs and acts as a circuit breaker in case of full detection on the break input. The MOE bit must be set to have the outputs enabled. This is valid even when the timer is used without dead time insertion and the timer is used for general purpose applications. This slide lists the timer instances present in STM32-C0 microcontrollers. Timer 1 is a full-featured timer, controlled capable, including all PWM options and six compare channels for being able to generate simultaneously three-phase PWM signals and half-to-independent ADC triggers. Timers 16, 17 are general purpose timers. They have complementary outputs and break functions. Timer 3 is a general purpose timer, including advanced PWM modes, up-down counting capability and four channels. Timer 14 is a light timer with support for standard PWM only with one channel and up-counting mode only. They complement the other timers whenever additional independent time bases are necessary. This slide indicates which features are implemented for each timer present in STM32-C0. Programmable dead time is available when the timer has complementary outputs, which is the case for Timer 1, channels 1, 2, 3 and timers 16 and 17. Timers 1, 16 and 17 support a break input. Retriggerable 1 pulse mode is not supported by timers 14, 16 and 17. Only timers 1 and 3 have the encoder interface. XR function that combines channels is only available in timer 1 and 3. Timer 14 is unable to assert a DMA request. The timer is linked with several on-chip peripherals. It serves as a trigger source for the ADC converter. The interconnect matrix enables timer-to-timer direct connection using the master and slave interfaces and direct connection between timers and other peripherals. The reset and clock control unit called RCC provides the internal clock reference for all timers. Three application nodes complement the timer sections in the reference manual. The AN-2592 gives a practical implementation of a 32-bit timer made of two synchronized 16-bit timers and is useful for better understanding the overall timer synchronization mechanism. It comes with a software example. AN-4013 provides a more detailed overview of all timer features and available firmware examples. AN-4507 presents an implementation of PWM resolution enhancement by means of dithering techniques. It comes with a software example. AN-4776 starts with a few reminders on timer operating principles and contains a collection of examples for standard timer use cases. It comes with a software example. Thank you for attending this presentation.