 Welcome myself, Gridhar Jain, Assistant Professor in Electronics and Telecommunication Engineering, Walchen Institute of Technology, Sholapur. Now, today I am going to deliver a lecture on CMOS logic. Now, learning outcomes of the session are at the end of the session, students will be able to draw construction of CMOS inverter and describe its working. Second outcome is students will be able to design logic gates using CMOS logic. Then, this is the symbol of N channel E MOSFET. Now, this symbol of N channel E MOSFET is simplified as shown in right hand side. So, this is symbol of N channel E simplified N channel E MOSFET symbol using VLSI. So, that substrate which is shown by the dotted line. So, that is not used here. So, this symbol for the N channel MOSFET is using VLSI and below that you can see the symbol for the P channel E MOSFET using VLSI. So, this is circuit for CMOS inverter. So, drain of two MOSFETs are connected together which will be the output. Source of P MOSFET is connected to the VDD and the source of N MOSFET connected to the ground as shown in figure. And the gate of P MOS and N MOS connected together where input is applied. So, this is circuit of CMOS inverter. Now, construction of the CMOS inverter is shown in the below diagram. Now, here we start with a P substrate. Now, for this P substrate on to this P substrate. So, N plus and N plus two heavily doped N regions are obtained by diffusion. One of them is drain and other is source. So, right hand side is source and this is drain. So, this is drain between insulating layer of SiO2, polysilicon and gate. So, this is N channel E MOSFET fabricated. Now, for fabrication of the P channel E MOSFET we start with N substrate. But here already we have started with P substrate. So, what is done? A N well is obtained by diffusion on to this P substrate. So, that is N well and on to this N well two heavily doped P regions are obtained by diffusion. One of them is right hand side is drain and left hand side is source for P channel E MOSFET. Then in between these two insulating layer of SiO2 then polysilicon gate. Now, drain of two MOSFETs are connected together where we can take the output. Gate of two MOSFETs connected together where we can apply the input. The source of the P MOSFET goes to plus VDD source of N MOS goes to ground. Means the connections are made during the fabrication according to the circuit of CMOS inverter. So, this is the fabrication or construction diagram of the CMOS inverter. Now, using CMOS logic or using CMOS we can implement the various gates. Now, here let us take the example of two input NAND gate. So, NAND gate is given by Y equal to AB bar by De Morgan's theorem. AB bar is equal to A bar plus B bar and this is the circuit diagram for the two input NAND gate. Now, you can verify whether the circuit works as a two input NAND gate or not. Now, the two P MOSFETs are connected in parallel and the source of these two P MOS goes to plus VDD. Drain of two P MOS that goes to the output. Then from output two N MOS are connected in series as shown. Now, input A is applied to the gate of this P MOS and this N MOS. Similarly, input B applied to the gate of this P MOS and this N MOS as shown in figure. So, this is A and B are the inputs and Y is the output. Now, if both input are zero then upper two P MOS are conducting. If these two P MOS are conducting then output Y is getting connected to the VDD and therefore, output is logic one. Now, if input is zero one means A is zero and B is one then this P MOS will conduct this will not conduct. Therefore, output is again getting connected to the VDD means output is logic one. If input is one zero or zero one A is zero and B is one then next is A is equal to one and B is equal to zero. So, this P MOS will conduct and if input is A and B are one one then upper two P MOS will not conduct and the lower two N MOS will conduct. Therefore, output is getting connected to the ground. So, in this way the circuit works as a two input NAND gate means output. So, Y is equal to AB bar means if both inputs are one then and then output is zero. If both inputs are one then and then output is zero under all other condition the output is one. Now, pause this video and think on the following question. What will be the circuit for two input NAND gate? Now, circuit for two input NAND gate. So, already we have designed two input NAND gate. So, here two P MOS are connected in series for the upper one and below from output to the ground two N MOS are connected in parallel. So, this is input A input B VDD and VSS. So, Y is equal to A plus B bar by De Morgan's theorem this is equal to A bar into B bar and this is the circuit. For two input NAND gate. Now, actually for the CMOS logic from output to the VDD whatever is the circuit that we call as a pull-up network. Which is designed using only P MOS and from output to the ground whatever is the circuit that we call as a pull-down network. So, pull-down network is designed using only N MOS. Pull-up network will connect the output to the VDD and pull-down network will connect the output to the ground. And pull-up network and pull-down network are dual shock each other. Means in the pull-up network two P MOS are connected in series. So, in a pull-down network two N MOS are connected in parallel. So, instead of P MOS N MOS instead of series parallel. So, they are dual shock each other. So, this is the general block schematic of CMOS logic. So, pull-up network or a circuit using only P MOS and the pull-down network or circuit using only N MOS. Then pull-up network goes to VDD, pull-down network goes to ground and in between pull-up network and pull-down network output is taken. And you apply the common input to gate of MOSFETs in the pull-up network and the pull-down network. So, this is block schematic for the CMOS logic. So, in this way using CMOS logic we can implement any gate or any Boolean expression can be implemented. Now, let us implement two input AND gate using CMOS logic. Already we have implemented the two input NAND gate. So, what I have done? I have drawn two input NAND gate as it is. So, output of two input NAND gate is Y dash is equal to AB bar. And already we know the inverter CMOS inverter. So, output of NAND gate is passed through a CMOS inverter means it is inverted. Therefore, the output of CMOS inverter is nothing but Y is equal to AB. So, in this way this is two input AND gate. Similarly, two input OR gate can be designed by using the two input NOR gate followed by CMOS inverter. So, these are references. Thank you for watching the video.