 , మ్రియ్రవాయంది, వినానియ్రియ్ంది. భ్తాని. మ్యరింది, ఎవి వాయాయాయాయా. టాతువిమోలికాను. మామురికా, సోది సికోపికి. is the first lab I will be focusing on the very basics of design compilers and I will move design compiler I will tell you how to get help in the design compiler how to get help on commands and variables we will look at the library setup in detail we will take a look at the portal inside the library how to report the information in the library I have a design example which have multiple RTS files in very lot it also contains some memories that will be very useful for the family how to handle these kind of matters so let us start with the very basics so this is the structure this is the structure in which we should arrange our file this is the recommended structure obviously you can follow your structure also but it should have some logical basis this structure is something like this in the RTA directory you have all the RTA files there is a read me which tells what are the changes this is again this example design is from synopsis so we use this in our lab then the folder models contains the library and we look into all these libraries in detail then the scripts which contains the DC scripts for your design which would use processes then work is the folder in which we would start working part and working decision and then output is the one in which we would store the output on the design compiler so what is the output of the design compiler is the method the most logical output from the design compiler is the method you could always also write out the constraint type whatever you apply so we will redirect all the outputs to this there is one more folder input which has the one more is busy so now i would for this session i would not source any any script file i would actually write out each and every command so that it's very clear how do we go about doing that so next let's go to work i'll just clean up some of these stuff just to start afresh so now in this session the design compiler is already set up so you could see what the official points to the DCL points to the place where it's an offset design compiler so the command is a decision i'll just invoke it now whatever we enter into DCL we can actually redirect to a log by using the T command so now whatever we type inside DCL the log will be stored in DC dot log DC by default also dot log but it's not that easy to read so you should always make sure to read it the command contains the log plus a lot of extra things so to get a simpler log out of DCL this is the best way now when DC starts it will usually list down the various licenses and various features so these are various licenses and various feature names so what we will be using is either DCUltra and DCExpert so the compile command belongs to the feature DCexpert compileUltra command belongs to the feature DCUltra sdl compiler is the one that reads in your weblog files and analyzes them again DFT compiler is used for scan design there is a suit of design some pre-made IPs from synopsis like adders, multipliers etc library compiler is the feature that will parse your library files power compiler is the main suggestion to use the power forget about DFT compiler for now and so can adders you need to worry about code so it looks like compileUltra license is removed so we would be using compileUltra if you have compileUltra please use it if you don't then use compile so compileUltra is much more advanced than evolved form of compile so I would recommend using it whenever it's available this is the version so if you are using if you are working for trial synthesis for your lab and on you don't need to worry about the version when you work in an industry you should be very sure which version you should be using because some of the versions still contain some part synopsis my editor I think that the feature we know because we see the above version team and they showed that all the designs of which avoid any pit points now in decision is there is a tickle command mode I am not going for UI mode you are always free to experiment but I find it takes this not more powerful than the UI mode the reporting is not more intuitive so I would focus on the tickle interface as it's very popular in the industry but please please please do explore the UI mode for design reason whatever I mean I can only say that you are not missing anything by going with UI mode by not going with UI mode so all these all the features are contained in the tickle mode UI is just it will just show you some block diagrams of some suffix which will be very helpful otherwise the tickle interface is quite sufficient so when you type help here you would get a list of all the commands so this is a list of commands that is available to you so now if you let's say want to see what are the commands that can work on libraries you could do something like this so this will tell you the list of commands that can be lifted so I would let's say I want to know what are the reporting commands so I can say report start it tells me these are the reporting commands that are available to you so you see there are a lot of commands we will go over the most popular one and always for anything you want to do now it's each command has two types of filter available so let's say I use a command called command called defined design list now defined design list so the tab works very well so it will automatically be command for you so defined design list should do a minus help on the command so minus help tells us that what are the options available so what it means is that defined design list a small summary it is a design design list the option available is minus path and minus path directly so this tells us that this tells us that these options are available so the battery name it is a logical name and minus path will be pointed to a specific directory path on your menu directory so you could for an extensive help you could do something like this you can say man is a manual platform manual man defined design list now this is a much more descriptive help on a particular command so what it tells us is that this defined design list command maps a design library so you need them so design library is a logical name unit directory is a physical path so every command is a return filter so this is the syntax it tells us what the arguments are and it gives a description it also lists down some example and it tells you what all commands are related to this command it is clear from this command defined design list that it is related to analyze and elaborate now let us look at the the libraries first so we will go out of this okay now let us see the libraries first so libraries are scrolled into the directory model let see what is there now there are two let us first focus on the standard command list so this is the standard command list S A E D this is from Synopsis and now it has if you notice that it has C C is .5 and C .db file so the .db file is a text relabel format each of these corresponds to one particular operating condition so ff 1c 1 6 v n 40 means this belongs to a fast corner fast fast fast means fast term of fast term of 1.16 volts is the voltage minus 43 n is for negative minus 43 so this is the fast case fast corner or the best case corner this is the slow corner ss means slow 0.95 volts so again you see that there are two extremes here lowest voltage to highest voltage this is a typical corner so the the typical corner will be the operating voltage and operating compressor at which at chip it is supposed to operate and the other design corners are the margins for which we should make sure that our design is work so typically the voltage is 1.05 it can go so the range of the chip for which we are which we will qualify the chip will be from 1.16 to 0.95 volts so what is the worst corner worst corner is when the device is are slow that means NMOS and PMOS is slow that says when the voltage is lower mostly in most of the cases that will be minus 10 percent of VDD VDD here is 1.05 volts so there is there is some margins 0.95 is the lower side the device will be slower at high temperature temperature is 125 here the typical temperature is 25 right so TT means typical so these are three corners one is this is the best case corner this is the worst case corner typical corner as I stress lower time before that synthesis has to be done at the worst case corner at this corner if you compare any cell so both these are please will be exactly same in terms of the number of cells the cells of salary and all that the only thing that changes is the timing number than the power number so you could actually see compare both of these that is pick up one cell each and you would notice that the slow corner has more delays than the fast one we will see so synthesis will use the slow corner the worst case corner and we will see what is the use of the fast one and a typical corner we will see later it will come in the next slide right but for for this lab you will keep using the worst case corner that is the slow corner but DB dot DB are retained from decision again these are the binary versions so design compiler it is can read dot dot with but it is preferable to give it a dot DB processing becomes much more faster that is why we prepare these web files we read in and write out the DB files before even starting the system this is a very simple command for right click you could read it in right click that will do the job for you so I have already written out the DB so that we tend to use the DB there is one more file there is one more library which is for the library we will have a live on a DB as very similar to the standard there now let us see what is inside the list we have seen some examples in the in the lecture slide but let us we will look at it if you will much more included now so this is the library name this is the library name the first few lines tell the tell the section define some variables important here is technology CMOS delay model stable lookup what is stable lookup stable lookup is non-linear model is represented by a table lookup stream it also has the time units library defines all the units then it will define some threshold value so these are the threshold value used for calculating rise rise time for time 28 so we can we know from here that the limits for calculating the transition times and the rise and fall delay are from 0.2 VDD to 0.5 similarly these threshold here PCT PCT means percentage these threshold here define that how do we calculate delay from input to output the delay is calculated by taking the 50 percent of VDD of output minus 50 percent of VDD of input from these thresholds define that there will be some default pin caps some default loads and so on I will not go through everything this this defines the nominal voltage so the worst case library has a voltage of 0.95 that is 0.125 process 0.99 this pin does not matter for this because there is a great library for each there will be some by load reports now this this part defines the by load there is also something called voltage map that so VDD is set to 0.95 here so these are the by load models these are different by load models that are available in this library also there would be a by load selection yeah there is a by load selection group which tells us that how the by load is selected so this is automatic linear based by load selection so this is the by load selection area and so now this is the phase that operating condition is defined process voltage temperature entry type and now comes the comes the look of table the look of templates now let us see let us see one cell so this is the cell and 2x1 so this is a cell the area is given the leakage power is given let us not focus on the pg pins for a while that will come later this is I can only tell you that this pg pin is used for low power synthesis so and this is outside the purview of this code so this is used in the in the low power pin now what it defines here is the pin the pin is defined direction is encode whereas there are capacitors available there are some power numbers here similarly A2 is again a second pin it is an input pin it tells what is the fan out load if you remember that how the fan out calculation is done it tells the fan out load and then there is a pin called y which is the output pin direction output and function this is important this tells what kind of data it is an AND gate because it is A2 and A1 now so there are power numbers and there is a timing number so this is the look of table so this is the cell right sense as that with respect to pin A1 when A1 changes I mean sense is positive unit meaning that A1 will rise output will rise when A1 will call output will rise this is called positive unit negative unit means when input rises and output falls there is an invert relationship it is called negative unit so this cell rise there are two indexes here it uses this table so we can see what this table is you can look at the top so this is the look of table it is using variable one is resource next transition variable two output gap and if you see index one index two values they are both different values but they are dummy values so whenever the table is used the indexes are assigned the proper value so this is transition value these are deficit and the values with this this table will tell what is the delay so for example this is the delay part when the transition is fixed and the gap is this this is the way you can understand this look of table how it is arranged so there are different cells there are a lot of cells here each for each the important thing to know is how to see the area numbers how to see the function and so DC will use the function to map the design it will use the timing and area parameters to optimize the design it will use the power number to do some power calculation and power optimization but we will see that later but let us focus on area and timing for this these two last last session so these are let us look at one of the sequential cells let us look at a scan flaw so this is a flaw sdfs now the function here is represented slightly differently as we saw on the slide it is is represented by ff i2 i2 n is locked on cld the next state is this so next state depends on the pin called scan able so if the scan level is low the d will represent the data pin is represented by d if the scan level is high the data pin is scan input let us look at the non scan the non scan the flaws are usually dfs represented by the name dfs can ones are called sdfs this is a very global kind of naming convention so here it is clogged on clk next state is d here is represented by rstd and here the pins are listed go down this is the pin d so now d now an input pin of a combination element does not have any timing parameters it just has the fan outflow that is it and some capacitance however a deep in will have the timing parameters which are nothing but set up a hole so this is the setup and this is the this is the hole so this is the setup when d is rising when d is falling related pin to clg right so the setup rising tells us that the timing is with respect to the clock rising so this is a positive s triggered so these timings are setup rising hole rising you could go through it at a at your own pace and see that don't worry about the negative values it's not it's very common to have negative whole value you could read about it online by the whole value the negative sometimes but it's common to other now let's go to the pin q this is pin clk now dc knows from this clock through that this is a clock pin of the clock again clock does not have any timing parameters it just has power parameters this is a reset b pin now reset b now a reset b which is asynchronous will have a recovery removal timing similar to setup and hole recovery and removal so this is the reset pin and then we go to the output pin where the function is iq which is again we saw at the top that how the function is represented for this and then it will have the the timing numbers the timing numbers are with respect to the clock rising edge so cell rise output will have now two things one is the delay part that is the transition model and so this is the this is the delay part and this is the transition tone cell rise rise transition cell call call function and then there is a timing with respect to the reset pin so now what does a library have let's summarize library has a list of cell for each cell the function is defined the input output pins are defined timing is defined the output pins will have the delay and transition number timing number the input pins for combination will have nothing no timing number or sequential they will have set a full time right now let's go to dc again and go to dc again now how do we start the first thing we do we know where our libraries are we need to specify we need to tell dc how do how does dc call to the library so for the first thing now i talked about commands there are two things there are a lot of things for variables but there are a lot of variables which control the functionality of the compiler how do you get a list of variables you just see a print bar so this is the list of variables and the default value dc for example we could see what is the search path so the search this is the search path this is the default search path this is the first path points to the current directory and the some directories inside tools in opposite so the first thing what i would i like to do is set the search path i usually set the search path to where my rth is and to where the libraries are now what i did is i set the search path to i appended some things to it i appended current directory in a positive way i appended models and the rth this is the first thing i did i set the search path i tell you how i how it is used now since i have included models and rtl if i read the rtl file now i don't have to give the complete path since we this is included inside search path so dc will search for it inside the directory listed in the search path and it will automatically find it second thing i do is that i have set the link library now this link library is we set the link library to star star means already loaded memory designs in memory this is you can read about link library by reading the man page but this means that link library is the list of library that will be used to link the design at all points of time that means even before synthesis after synthesis always so link library should have a list of all the library and all the designs in the memory the star represents the designs in the memory this tells us what is what are the other other libraries available so what we have available is the worst case library for standard cell and some library for memory here i do not have a worst case library for memory so i am using the typical it is okay to have this for trials but whenever you are working on real projects please make sure that all the cells memory standard cells or analog map should have the worst case library available for synthesis now i set the link library to know what is the link library set to i can do an echo echo dollar link library or i could even do a print var on this so this tells me that link library is set to this then what i do is next i set the target library now target library is a set of libraries which can be used by bc to map design please you have you it is very important to understand the difference between target and link is a superset it contains all the libraries target contains only those libraries that bc should use for mapping now what does bc use for mapping it uses the standard cell library it does not use memory libraries for mapping a memory is a hand instantiate itself that means if you want to use a memory you should instantiate it in your design if you do it directly in your design there is no way bc can map a complex logic to memory that is why a target library will contain should contain mostly the standard cell memory right now we have set all the library now what we could do is now till this point only the libraries are set the libraries are not ready yet when the libraries will be read when we read in the design so till now it is only bc is only preparing stuff for you it is the you have only set the lab with some variables but nothing has happened yet no reading has been done now we we define some a designer part the command we were saying earlier so i defined a designer which tells bc that in the current directory in the physical directory word is your work territory now every time bc reads an rtl file it will create some intermediate files those will go into this now i actually do this in fact as when we read the first library rtl file we will see what happens now let us read the first rtl file so i am reading just a part of this one file from the complete design i am not reading the complete design we will start slowly we will build this up we will read the complete design later now what i do is i just read in one rtl file this is the command analyze minus format we will log so you could either use analyze the library or read file i am using analyze the library it is much more intuitive so analyze minus format while log and i tell minus library work now here i am not the library work with the physical directory which is also called work and i read in this file now please note i haven't given the full path for instruction decoder now as soon as i give this dc will launch the press to a compiler it is the feature it is searching for instruction decoder in the list of directories given the search path it found it the compilation is completed so this is only a syntax check now at this point dc loads the library it reads the library is given in the link path now i can do some command i can use some command to see what the libraries are loaded let us let us do let us do some reporting now we will elaborate this first and see what happens now assuming that this instruction decoder is my top level design i will elaborate it you typically will only like to elaborate from the top so let us say you read in 10 file you would give in the elaborate you will give the design name the module name of the top post block here since it is only one rtl file i will just give the name of the so i will open this i will show you what the rtl is this is the rtl this is the module this is some kind of instruction decoder the commands on the top also tell what is the what is what does this block do this is some instruction decoder it has a cloth it has a reset it has some inputs some outputs it is it is simply it has some instruction bus and it will give out the enable signals this is an instruction for many cpu so so this is the rtl here i see that there is okay one always drop there will be a list of registers here and so the module name is called instruction decoder so i will just give the elaborate command now what happens now the earlier the analyze command it just takes the syntax of the rtl file it did not do anything else elaborate command will now run a lot of rules here it will now try and map the design with the gtech components that is what elaborate as please go to go back and read about elaborate that is what elaborate is trying to do it will try and map where rtl design the gtech components to the technology independent library let us know what will happen so it will do all kind of equivalency what it tells is that this was an always block it tells us that it is infinitely divisive in process in routine instruction decoder line some give the line number in this file routine is the module name file name is given and now it tells us that it found so many registers so we saw one always block it is reporting with respect to that we would it tells us we get for the register it tells whether it is bus or not the width is more than one the bus is less otherwise it is more it tells us whether it has a synchronous t set a synchronous set set we set or synchronous set or synchronous t set now let us go back and look at the rtl again now it will append underscore edge to each one of the names so let us look at the instruction this let us just look at this instead is a register some there are some buyers which work on this based on the value then it is assigned to some some buyers and then the register itself is based so we see this that there is a this always block we see that it has a synchronous t set back because it is not in specific period if you notice then the if command is the first one if what happens on reset so there is a pragma also synopsis think set reset reset you could add a moment this and see what happens usually it should work fine because this the coding style is good so this should be made as a synchronous set block synchronous reset block and then there is some idea so now so for each of the register that you work on it is good to see for each of the rtl file it is good to see the elaboration report at least for the first time if it gives you lot of so if your register is not appearing here there is something wrong maybe it appears as a latch which you did not intend to do it may maybe you targeted it to be a flip flop but it became a combination logic because of coding mistake so lot of info is in the elaborate time now at this point the design is mathogy text is it possible to see yes it is possible what we should do we could use a write command you can say write minus f command you can say very low and minus output is let us say i say it is a short so if it wrote something let us see what it wrote so this is this write command is the one that is used to write on the net now please note please remember that the synthesis is not being done we haven't issued any compiler compiler come on now let's see what kind of set is that we get what we get here is a new so we looked at the sequence set gen block this is the generate sequential element so if you could see that you could compile it with the block diagram even in the electrified so and then there will be a host of so there are lot of plots and then there are some gtech components gtech mod gtech odd and so on right so this is a gtech netlist how is it used it is gtech netlist useful there is no optimization that is taking place as of now because there is no synthesis that has been done if they use a gtech netlist is that let us say you want to deliver your code to some third party and you do not want to clear out your design you could always give them a gtech and if they are using the same tools in office design compiler they can use this to plug it in their design they can use your your code in the gtech form and use it in the design use it for synthesis so this way your code is productive they cannot read it and they can also go ahead and so this is one of the uses of gtech now let us lose the now i won't go into compile into this in this lecture we will focus on the compile command let us focus on some of the reporting so till now we see that how do we set the libraries using link part target using these these commands link search part link library target library defined now let us see that what what is it with design design designer so it created a directory called word inside word what is there inside word there are few binary files which belong so we read a module called instruction decoder so these are the intermediate files that synopsis generates design compiler generates it is not used by us but it is used by the tool do not worry about that but it is a good practice to create a word directory and link it to the logical directory word whenever you are working otherwise what you do is you dump a lot of files in the local directory which you do not want you want this particular area to contain your log files only so it is a good thing to create a separate directory and point design compiler to that one for writing out these intermediate files now so we we saw how to set we link library target library before define designer we saw how to read a single RTL file and what does elaborate command tell right now I will show you a couple of reporting commands that are very useful for library so first command is list underscore library list underscore list that tells us we see that what are the options that you can either want a particular library to be listed or you can use this command it will give you all the library that are there what else what is loaded library name is this this is defined and this is the part so standard cell is loaded memory is loaded gtec is loaded gtec is part of the tool it is not something that any technology library does provide you this is this is included in the design compiler tool and standard essentially standard standard is the list of symbols that are used to show you the block diagram when you use the GUI mode right now there is one more command called report and list now this tells us what what is the library what are libraries are loaded now we can do a reporting so list will give you a list of things report commands can be used to report on those things so I want to report on the library on the semester library let us look at the options we have there are so many options available here so what does an library contain it contains cells functions timing power knowledge data a lot of data it contains a lot of data this report command in so one thing is you can either open up in a text editor and see or design compiler also gives you a summary before so I what I will do is I will just do a so a square brace here is that these options are option you could you could and this is library name is without this square brace that means this argument is composite so I just give one one argument I just say report in the school name and I will do as report on this library what it is giving it gives me that this is a technology library and it has power down pins it is created by the school it created it is created on this day library version time unit it gives it gives us all the unit information it gives the operating conditions forget about intercom to voltage for now it tells us what is the voltage value some default values whatever we saw in the library it's all here in this report and it's easier to read a bit compared to each VTX file it gives a list of viral models it also tells that for a particular length for a particular fan out what is the length it will use for a particular only form so it gives a list of viral model these are all the viral model it tells us also about the viral model selection group so on then it tells us now here not there there was hardly any text and the the variable name there was no comment on it where DCMEN also tell you the comment so what does this mean delay threshold performance so input threshold percentage rise output threshold percentage rise and so on I have already explained this now it also gives a list it it gives some legends that now it starts listing the components that is it tells and before listing the components before listing the cells it tells what kind of cell it is either a black box or a test shell or a function there are a lot of legends it has level shifter map only in our DC it needs to know apart from knowing what whether it is the combination cell or a sequential cell apart from knowing all the stuff it also needs to know some other be this this collection of stuff is called attributes each particular cell has an attribute for example let us look at few examples now for example take a simple iron cell now it does not have any attribute it is a simple combination cell but look at an antenna cell this antenna cell is a b that means it is a black box the legend tells us that b means it is a black box b means to do not touch and b means to do not do what does b mean this means that antenna is some kind of special cell b black box means DC does not know the functionality of it why because there is no function attribute different you could go back to the library you can open the text file list file and see for yourself whether it is an antenna there will not be any function attribute the antenna cells are typically they are very special cells this do not have any functionality but which are used to correct some problems in the layout now standard cell library contains all kinds of stuff it contains all the combination special cells special cells antenna should it be used in simple thing no it is a cell that is that might be used by the layout engineer to resolve some problems which are very specific to layer it has no functionality but it still is a part of the standard library because the same library is used by all it is used by the synthesis guy it is used by the timing analysis guy it is used by the back end user so the library is common and these attributes are a way to tell you the tool that this cell should be used or not used so just because first thing it said to black box second thing it said said to you which means do not use you mean that do not ever use this cell do not ever input this thing so DC will not use this cell to do anything so even if let us say function was defined when it was not having a black box but if you set it do not touch sorry if you set it do not use then DC will not input that cell about do not touch means that if this cell is already present in this in the design if this cell could be present in the back end in the port layout because the layout is in the my side you will see if this is present then do not touch it many people they like to instantiate some in their app you see the examples in design also and they want DC not to remove them they want to tell DC that I have placed this cell and please do not touch it do not remove it that is it is edited by do not touch do not touch DC that do not play around do not modify anything related to this cell do not use cells do not ever use this cell so now there are for example there is a cell called AO box one right the functionality is known it is not seen but we are telling that do not touch it do not use it what does AO mean AO means AO means it is an always-on cell it is an always-on cell fine always-on is an attribute use for power only but so for each cell there are some attributes defined right so here for example ISO cell cells as it is an operation cell so all all special cells which have some special functionality which are might be used for voltage domain problem might be used for following DRC problems in layout all these cells should be do not use and do not touch in the in the lab if the cell is not let us say that attribute are missed something you could always give commands and DC to accomplish that but usually it is a good factor that it comes from the value so s i guess means sequential sense because all the national are attribute as s so there are so this is a s this is a redemption kind of a thing so there are a lot of lot of special kind of cells this is a scan cell scan type of a thing and so on so the port layer will give everything i think there is also a summary let us see what all now report list did not give any any tiny information it fight upon it will just throw out list of pilot models the variable setting and the list of cells and the rapidly you could also see the timing later it will be big report you could see minus minus timing example so it will also list out the timing data so here it started dumping out the lookup tables and to see it will started dumping out the so this is just again a different sort of a view for the ladle so it is just dumping out the data from the document side so so so report list and list list is a very useful commands so no about no more about library instead of going and opening and etc these reporting commands are much more useful now so we read in the article we read in 15 so DC will we laboratory that so DC will set by default it will set the current design to be whatever design in laboratory so by default current design is set to whatever we laboratory we think we laboratory instruction decoder DC set this to instruction decoder now if you want you can just give a compile command complete and see what happens let us let us see so what I do I just give a compile command I have not defined anything I have not defined any timing constraints I have not defined any area constraints I have not defined any environment constraints but still let us see what happens if I give compiler now what what it does is that compile I draw since it is the first time we are running compile it will load up the character library and it will do some analysis so it will say analyzing this and so it takes some amount of time the the bigger the library is the longer it takes so what I will do is so meanwhile it will I will I will go over the command and see now we we elaborated one article now what happened what what if you want to read the complete design whatever all the article so you could do it in this way you could say analyze my fabric work and then in the curly basis you can specify all the article this is a list of all the article files the backslash is for escaping the new line so so that is much more readable so what I will do is let us look at the the compile commands in more detail in the next lecture so for this lecture please focus on you could go back to your decision we open up the decision play with these commands search path link library target library read and write on write write a small character article code using the HS lines of article coding you can try and write in write out write a small instruction for example or use the efficient code from the lecture side and read that in design compiler look at the elaborate report so the focus of this lab was to make you concentrate on the library and the elaborate report so please focus on the elaborate report we can different kind of article file see what the elaborate report contains and focus on the compile command of this design we will we will talk about the design functions with normal functions how to