 Hello everyone, I am Dr. Asha Thalange and today we are going to discuss state diagram and state table for sequence detector using Mealy model for overlapping type. At the end of this session you will be able to draw the state diagram and state table for the overlapping type sequence detector using Mealy machine model. These are the contents we will be covering in this session. Now before moving ahead recall how many states are required to draw the state diagram for a sequence detector using a Mealy model? Well, the number of states required is same as the number of bits in the sequence to be detected. For example, consider a sequence detector to detect the sequence 101. So here the number of bits is 3. So the number of states required to design the sequence detector is 3. Let us now draw the state diagram for a sequence detector using a Mealy model. Now consider an example to detect a sequence 101 for Mealy model and overlapping type. As discussed the number of states required to draw the state diagram is 4 here as the number of bits in the sequence is 4. So let us consider these 4 states S0 to S3. Initially in the reset mode the state machine goes into the initial state that is the S0 state. Now initially let us assume that the incoming bit stream is same as the sequence. So let us consider the state S0 and now the first bit received let it be 1. So here it is the first bit of the sequence. So there is a state transition taking place from S0 to S1. Now here in the Mealy model the output is expressed on the state transition line as shown. So here the output is still 0. Now consider the first bit is received now in the state S1 it is waiting for the second bit. Now here if the second bit received is 0 it will move to the next state. So here the received bit is 1, 0. Now since the sequence is not yet completed the output is still 0. Now again consider the state S2. Now the received bit till now is say 1, 0. Now if the next bit received is 0 it will move next to the next state. So here there is a state transition again taking place. So here again still since the sequence is not completed here the output is still 0. Now up till now the first 3 bits have been received. Now in state S3 if the next bit received is 1 it means it is the end of the sequence. So here as soon as in the state S3 if 1 is received the output becomes 1 as the sequence got ended. Now since it is a overlapping method here among the sequence apart from the first sequence in all the bits we can treat the last bit to be the first bit for the next sequence. So here this one can be treated as the first bit for the next sequence arriving. So in this case when in S3 if the bit 1 is received it means it is the end of the first sequence. So output is made 1 similarly this can be acting as the first bit for the next sequence. So if the first bit is received then it has to wait for the second bit. So we know that for second bit we have to wait in state S1. So here after receiving 1 in bit S3 it will now move to the state S1 to wait for the next bit that is 0. Now let us assume again the state S0. So here in the state S0 if the initial bit received is 1 we know that it will move to the next state. But here if the initial bit received is 0 it means no sequence is started. So here it will remain in the same state and also the output is made 0. So in S0 state if the incoming bit is 0 it will remain in the same state. Now let us assume that the first bit now received again is 0 sorry. Now let us assume that the next bit that is received is now 1 and it will move to the state S1. So here the first bit of the sequence is received. Now if the 0 is received it will move to the next state. What else if the second bit received is also again 1? It means again there is a break in a sequence and now this one is treated as the first bit for the next sequence. So here again this bit 1 received is treated as the first bit. So here it will wait in the same state to receive the second bit that is 0. So here in S1 if the incoming bit is 1 it will remain again in the same state. Again the output is made 0. Now let us say that the next bit received is 0. It means we have received 1, we have received 0 now it is in the state S2 to receive the third bit. Now if the third bit received is 0 it will move to state S3. Now what else if the third bit received is again 1? It means instead of 1, 0, 0 if the third bit received is 1 it means we have received 1, 0 and 1. So it means again there is a break in a sequence. So here now the third bit received 1 is acting as a first bit again and now it will wait again for the second bit to be received. So here it will move to state S1 to wait for the second bit and now this bit received 1 is acting as the first bit of the sequence fine. So let us now assume that 1 is received again in S1, 0 is received and now in S2 again 0 is received. So the received bit is 1, 0 and 0 it comes to the state S3. Now in this state now if 1 is received it is again moving back to state S1 and there is a complete of a sequence and the output is made 1. Now what else if in state S3 if a 0 is received? It means this is the fourth bit position. So received bit is say 1, 0, 0 and the fourth bit is also if it is received as 0 it means again there is a break in a sequence. So here once the fourth bit received is also if 0 it means again we have to start from the first bit of the sequence. So here there is a state transition to the initial state. So in S3 now if the incoming bit is 0 it will move back again to the initial state and wait for the first bit 1 again to receive. So this is how here the state diagram for the sequence 1, 0, 0, 1 is obtained for the Mealy model. Now once the state diagram is obtained let us convert this state diagram to a state table. Now we know that in the state diagram there are four states. So let us write in this present state there will be four state S0, S1, S2 and S3. Now based on the present state and the input value here we know that both the next state and output depends. So output depends on present state as well as input whereas next state also depends on the present state and input. Now consider the state S0. Now if the present state is S0 and input is 0 so the next state is also S0 and output is made 0. So similarly here the next state is also S0 and output is 0. Now consider the same present state S0. Now if the input is 1 here the next state is S1 as well as output is 0. So here next state is S1 and output is 0. Now consider again the present state as S1. Now in the state S1 if the input is 0, the next state is S2 and the output is 0. So similarly the next state is S2 and output is 0. So again in the same present state S1 if the input is 1 the next state is also S1 and output is 0. So here next state is S1 and output is 0. the same process is applied for all the states. So, consider S2 again. So, S2 if input is 0, next state is S3 and output is 0. So, here S3 and output 0. Similarly, in S2 if the input is 1, next state is S1 and output is 0. So, here next state is S1, output is 0. Same is the case for the last state S3. So, here in S3 if input is 0, here the next state is S0 and output is 0. So, S0 and output 0 and finally in S3 when the bit received is 1, then the output is also 1 and the next state is S1. So, here S1 and 1. So, finally the output becomes 1 when in state S3 final bit 1 is received. So, this is how the state diagram is converted to the state table. Now, using the method explained, try to draw the state diagram and state table to detect the sequence 111 using Millet model for this overlapping time. So, this is the state diagram and the state table obtained for the sequence 111. So, as shown here the number of bits is 3. So, the number of states required is also 3 and here this bit here is the middle bit 1 is acting as a overlapping bit. So, from here the bit starts for the next sequence. So, here totally there are 2 bits of overlapping. So, this is how the state diagram and state table is obtained. So, these are the references used. Thank you.