 Welcome to the presentation of the STM32-L4 Plus Direct Memory Access Controller, or DMA. It covers the main features of the DMA controller module, enhanced by the new DMA MUX module. The DMA controller embedded in STM32-L4 Plus is similar to the one implemented in the STM32-L4, but with an additional DMA MUX. The main feature of the DMA is to offload the CPU for data transfers from any memory mapped source towards any memory mapped destination. For more information about the memory mapping and specifically addressable space for each DMA controller, refer to the L4 Plus AHB bus interconnect. L4 Plus DMA features two DMA controllers. For each DMA controller, it is possible to do programmable block transfers with seven concurrent channels, each of which are independently configurable. Programmable channel-based priority and data transfers via the AHB Masterport connected to the bus matrix. There is also a DMA request multiplexer or DMA MUX with programmable selection of the source of any DMA request, from a peripheral in DMA mode or from a trigger, and event triggered and synchronized DMA request generation. There are 89 peripheral requests and four DMA MUX generated requests. There are 26 triggers and synchronization inputs, and among these 26, there are four DMA MUX generated events. There are 14 DMA channels and requests. Each channel of the DMA controller is independently configurable. A channel can be assigned to a DMA hardware request from a peripheral in peripheral to memory or memory to peripheral data transfers. Alternatively, a channel is assigned to a software request in memory to memory data transfers. A channel is programmed with a priority level, and a channel is programmed for a number of data transfers at a block level. The software can control a channel via the separated interrupts and or flags upon programmable events, such as a block transfer complete and or a half block transfer complete and or a transfer error. A channel is programmed for a number of data transfers at a block level with independent source and destination data size, independent source and destination start address, independent source and destination address increment, either contiguously incremented or at a fixed address, and a programmable amount of data to be transferred within a block. In memory to memory mode, a block transfer starts as soon as the channel is enabled. There is no hardware request. Whereas in peripheral to memory and memory to peripheral modes, a block transfer starts as soon as both the channel is enabled and the peripheral sends a DMA hardware request. A DMA hardware request identifies a single DMA data transfer. Each DMA hardware request is paced and granted by the DMA when each data is successfully transferred to the destination. In any mode, channels arbitration is reassessed between every data transfer. DMA MUX is a programmable multiplexer router of DMA requests. The mapping of DNA requests from any peripheral to DMA channels is programmable via independent DMA MUX channels. Additionally, up to four DMA requests may be internally generated by the DMA MUX following an input trigger signal. Any generated DMA request is independently programmable in terms of the trigger selection, the edge detection, and the number of generated DMA requests upon each trigger event. The trigger source may be EXTI0 to EXTI15 or LPTIM out, DSI tearing effect, DSI end of refresh, DMA2D end of transfer, LTDC line interrupt, or any of the four generated DMA MUX events. In synchronization mode, any DMA MUX output DMA request can be synchronized with respect to a programmed and selected synchronization input. The synchronization edge detection and the number of transmitted DMA requests upon the synchronizer event are also programmable. As well as managing DMA requests, DMA MUX can also generate programmable DMA MUX events, which may be looped back as trigger inputs. For example, this would apply to transfers chaining between different DMA channels. In normal or unsynchronized mode, SE equals 0, DMA MUX is routing one selected input DMA request to one of its output DMA requests. On top of that, DMA MUX may be configured for generating an event, EGE equals 1. An event is generated at every NBREQ plus 1 DMA requests. Here NBREQ equals 3. In synchronization mode, SE equals 1, DMA MUX is configured to synchronize a DMA or block transfer request upon the reception of each hardware synchronization event. The block data size is programmable via the program number of DMA input requests equal to NBREQ plus 1 to be transferred between two occurrences of the synchronization input. On top of that, DMA MUX can be enabled for generating an event every NBREQ plus 1 DMA requests. If there is a new synchronization occurrence before the block transfer has been completed, as paced and granted by the DMA, there is a DMA MUX synchronization overrun flag and a raised interrupt. Each DMA channel can notify software with an interrupt being caused by any of the four possible events. Half block transfer completion, block transfer completion, transfer error, or any of the three above events, also known as global. DMA MUX can generate one interrupt caused from an overrun by any of the configured channels. Root cause may be either a trigger overrun before the internally generated number of DMA requests have been issued and completed, and or a synchronization overrun before the number of DMA requests, external or internal requests, have been issued and completed. This table summarizes the state of DMA versus the power state machine.