 Thank you. Thanks, Daniel. So, I am going to talk about Private Circuits, a modular approach. This is in joint work with Ivali Shah and Amin Sahai. So, ideally, you want to protect your computation against external and trustworthy entities, right? However, this is not always the case. Many studies have shown the existence of surveillance attacks, which actually extract sensitive information from various devices. This sensitive information could include things like your credit card details as a number and so on. And this class of attacks in the literature has been coined as side channel attacks. There are various types of side channel attacks to read in the literature. And in this talk, I am going to focus on side channel attacks, where the adversary obtains some partial information about the computation. So, how do we actually protect our devices against these side channel attacks? This question is not new. There is an entire area in cryptography that studies these sort of questions. And this is the area of leakage-resilient cryptography. So, the goal in this area is to come up with cryptographic schemes that resist side channel attacks. And there are several sort of primitive studied in this area. And in this talk, I am going to focus on one such problem, which is to design leakage-resilient circuit compilers, which was originally introduced by Isha Saha and Wagner. So, let me explain what this is. So, first let me explain what are circuit compilers. Circuit compilers allow you to compile a circuit C into a compiled circuit C hat. And this is accompanied with the corresponding encoding and decoding algorithms. So, the encoding algorithm allows you to encode an input X into encoded input X hat. So, the computation of C hat on X hat essentially emulates the computation of C on X. And to recover C of X from C hat of X hat, we are going to use the decode algorithm. And here crucially, we use the fact that the encode algorithm is probabilistic. Okay, some remarks about this definition. So, we are only interested in the setting when C and C hat contain NAND gates. And the case when C contains NAND gates is without loss of generality because it can convert any Boolean basis into NAND gates with constant overhead. And when C hat, when you want to work with C hat for other basis, then you can actually extend our results to this setting as well. And we consider, we only consider the setting when the circuit compilation algorithm is deterministic. And the reason to study this is because we can use the circuit, the compiled circuit in multiple times. And there are no hidden draft doors. So, modeling adversaries is also very clean. And we allow C hat to contain random bit gates. So, by random bit gates I mean is that this is a gate where if you invoke it, you will get a random bit as an output. Okay, so now let me explain what is leakage resilient circuit compilers. So, the security experiment associated with this notion is as follows. So, we have this computation C hat on X hat. So, we have the values assigned to these wires. So, the adversary is allowed to submit a leak function. And this leak function operates on all the wire values in this computation. And it outputs something, some short information. And intuitively we want that the adversary doesn't get any information about the input. So, we don't care about hiding the circuit. We allow the adversary to know the circuit, but we really want to hide the input from the adversary. So, now the question is what sort of leakage functions can the adversary submit to the submit to the challenger? So, there are two categories you can consider here. So, one is global leakage, another one is local leakage. In the case of global leakage, the leak is a function of the entire computation. So, for instance, leak could potentially compute parity of all the bits in the computation. So, in local leakage, the adversary has some partial view of the computation. So, you can think of the computation as divided into blocks and maybe he gets some subset of these blocks of computation. So, there are many works that study both these categories. So, in the case of global leakage, there are many works. And some of these works resist attacks against leakage functions that are in low complexity classes. For instance, there are works that study leakage resilient circuit compilers, secure against AC0 and so on. In the case of local leakage, there are two popular settings. One is wire probing attacks and another one is split state leakage resilient circuit compilers. And in this talk, I am going to focus on wire probing attacks. So, what are wire probing attacks? So, in this case, leak is just a projection function. So, the output of leak is a subset of wire values in this computation. So, how is this subset chosen? Is this chosen by the adversary or is this chosen from some random process? The answers to these questions lead to different settings. So, let me first focus on the worst case setting. So, in this setting, the adversary specifies a threshold T and he is allowed to get any T wire values in the computation. And there are several works that study this setting following ISW. And in particular, many of these works have been studied by the chess community. And you can actually, if you look at ISW, one of the motivations they provide for this problem is in some sense devising MPC on silicon. It is, you can think of it as applying MPC techniques to design secure hardware. And in the recent years, there is growing interest in designing leakage resilient compilers with good randomness complexity. So, let me define what randomness complexity here means. So, the randomness complexity of a circuit compiler is nothing but the number of random bit gates. And a natural question to ask here is how many random bit gates are needed for a leakage resilient circuit compiler. And this is naturally motivated because the randomness is a scarce resource. So, you do not want your compiler to have too many random bit gates. So, a few years back, Isha et al. studied this problem and they showed a positive result which uses just slightly more than T cube random bit gates. Recall that T is the threshold associated with the compiler. So, natural question to ask here is whether T power 3 plus epsilon is tight. And in this work, we answered this question and the answer is no. And in particular, we show the following result. There exists a leakage resilient circuit compilers for SSI circuits and threshold T that resists T wire probing attacks. The size of the compiled circuit is s times polynomial in the circuit, polynomial in T. And finally, the randomness complexity used in this compiler is only T power 1 plus epsilon. So, this is for worst-case probing attacks. So, let me move to a different setting which is random wire probing attacks. So, in this setting, recall that in the worst case setting, the adversary could choose any T wires in the circuit. But in this case, the adversary gets every wire value with some probability P. And in the ideal world, we want to show a simulator that can simulate this leakage given only the circuit C. And we also allow for a small simulation RRE. And this model is related to the noisy leakage model that was studied in many prior works. So, let me review the prior works in this area. And the regime I am interested in is the case when P is constant and E is negligible. When I say negligible, it is negligible in the circuit size. And there are two prominent works in this regime. So, the first one is by iThai. This iThai showed the first construction in this regime. However, the construction is highly complex. At least I do not understand the construction well. And following iThai, there was a work of ADF which actually among many other results showed a simplification of iThai's result. But this result still uses some heavy machinery. For instance, they use AG codes, expanders and so on. I have to point out that even iThai's results use some expander-based tools in the construction. So, in this work, we show a somewhat simple construction of leakage resilient circuit compilers in the same regime as studied in the prior two works. And in fact, we can actually show a concrete constant. It does not look that exciting now, but we hope that our approach can be used to improve this constant. And underlying our result is a simple composition-based approach that only uses elementary tools, as you will see soon. And as I had mentioned earlier, we were only interested in the setting where C hat contains NAND gates, but you can actually replace the NAND gates with large gates. And in this case, you can actually tolerate probability arbitrary close to one. So, we also study another model called leakage tolerance. So, in the model of leakage tolerance, the input and decoding algorithm are identity functions. So, the rest of the talk I will be mainly focusing on leakage resilience, but I will give the results we obtain in the leakage tolerance model as well. And the reason why we study leakage tolerance is because it implies leakage resilience. So, the security notions are slightly tricky to define compared to leakage resilience. And the reason is that in this case, the adversary gets some fraction of the input and output. And so, we need to factor this when we formalize the definitions for the worst case in the random probing case. So, as before, the worst case will be parameterized by T. And we require that the simulator can simulate the leakage even given T bits of input and output. So, correspondingly, we can also define the probabilistic setting, the definition of the probabilistic setting. So, here note that we also have this additional parameter P prime. And this P prime determines the probability of leakage of the input and the output. And we correspondingly obtain similar results as leakage resilience. So, we can show a construction that has the same randomness complexity as before. In fact, we even can show a lower bound that says that we require at least T random bit gates. So, in that sense, this is tight. And for the probabilistic case, we can actually show upper bounds and lower bounds. So, this P which is the same as what I had written earlier. So, you can show that any leakage tolerance compiler can tolerate, there exists leakage tolerance compiler that can tolerate any probability that is less than this. And correspondingly, we can also show that if you want to tolerate probability greater than 0.8, then there does not exist any leakage tolerance compiler. So, let me explain the techniques used in this work. So, the goal for this talk would be to just stick to leakage resilience circuit compiler, tolerating random probing attacks. So, this is what I am going to deal with for the rest of the talk. And the starting point to constructing this is T auto fan secure MPC protocol. With this I mean this MPC protocol tolerates T adversaries and N is the number of parties. So, I am going to view this MPC protocol slightly differently. Instead of viewing this as a protocol, I am going to view this as a compiled circuit. So, MPC protocol of a circuit C will be viewed as a compiled circuit C hat. So, a party P2 will be viewed as a block of gates in this compiled circuit. And similarly, the communication channels between the parties will be viewed as the wires between these different blocks here. So, it is just a different way of viewing MPC. You can correspondingly also define an intuitive security notion. So, a party being corrupted here corresponds to leaking the entire block of P2 in this case. Just this view point leads us to the first candidate of leakage resilient circuit compiler. So, you can think of the compiled circuit C hat as just being an MPC protocol for C prime. So, what is C prime? It takes as input shares of X reconstructs, compute C of X and then share C of X. That is it. So, this is the candidate leakage resilient circuit compiler. So, and what is the encoding and decoding is the trivial algorithms. The encoding just secret shares the input and the decoding reconstructs the output. So, why is this secure? So, note that if utmost T wires are leaked in this circuit, then the leakage can be simulated. And why is this the case? Because any T wires being leaked is the same as any T parties being corrupted in the corresponding MPC protocol. And the MPC protocol guarantees that as long as utmost T parties are corrupted, things are secure. This is the intuition. So, now we need to calculate what is the probability that more than T wires are leaked, right? And once more than T wires are leaked, then we cannot do anything. This is why we need to incorporate this as a simulation error E. And by a simple turn of calculation, you can actually show that the simulation error E is upper bounded by this much. So, this looks complicated. So, we will just stick to the setting where these things are constant P, C and T are constants. In this case, the error will also be constant. This is great, but we really do not want leakage resilient circuit compiler that only tolerates constant simulation error, right? So, how do we go from constant to negligible? So, to do this, we are going to start with a base gadget. So, what is this base gadget? It is another name for a leakage resilient circuit compiler that has that is associated with constant probability P and constant error E0. Note that in the previous slide, we just constructed such a base gadget. So, we are going to use this base gadget to achieve our result. So, how do you reduce the error? So, the idea is as follows. Again, start with the T out of N secure MPC protocol. And now replace every gate in this protocol with a base gadget. So, we have a NAND gate here, replace this with a base gadget. And somehow we stitch all the gadgets that are associated with these different gates. And whatever you get here will be the next gadget. And I am going to call this gadget, resulting gadget as G1. So, now why is the resulting circuit compiler secure? And the reason is that as long as utmost T base gadgets fail, then you can simulate the leakage. And the reason is the same as before. As long as utmost T base gadgets fail, that corresponds to corrupting utmost T parties in the MPC protocol. And then you can successfully simulate. So, now again we need to calculate what is the simulation error in this setting. So, in order to do that we need to calculate what is the probability that more than T base gadgets fail. And the expression is the same as before except that you replace P with E0 here. And E0 got replaced with E1 here. So, by suitably setting the parameters you can show that E1 is actually smaller than E0. So, you have achieved some progress. So, now we showed that there are reduces, but we should also be mindful of how the size of the resulting compiler increases. And in fact you can, this is easy to observe the size of the final compiler. Here will be the size of the base gadget times the size of the MPC protocol. So, now we reduce the error a little bit, but it is still a constant. So, how do we keep going forward? So, we just repeat this process. So, in the case step we are going to take a T out of N secure MPC protocol. And we are going to replace the NAND gate with the gadget obtained from K minus 1 step. So, if you keep doing this you realize that the size is no longer small because in each step you are increasing the size of the gadget. And after K steps this will be exponential in K. Even when you only stick to constant size circuits. While this might seem worrisome at this point let us look at how the error reduces. In fact you can show that the error actually reduces quite well. It is 1 over 2 power 2 power K. So, it is actually doubly exponential in K. So, this is good for us. So, just to summarize what we have here is that when the circuit is of constant size, then the error is something like at most 1 by 2 power 2 power K. And the size is exponential in K. The size is still exponential. So, we need to make sure it is polynomial in the circuit size. And to ensure that we will just set K to be logarithmic in the circuit size. So, at this stage the error will be negligible in the circuit size. And the size of the gadget will be polynomial in the circuit size. So, note that all this while I have been saying circuit of constant size, circuit of constant size. So, what kind of circuits are we considering? So, for now let us just consider NAND gates. So, what we have so far is leakage resilient circuit compilers for NAND gates with negligible simulation error and constant probability. This is the result we want except that it is only for NAND gates. So, how to go from NAND to arbitrary circuits? So, what we do here is we start with this arbitrary circuit which is comprising of NAND gates. And we will replace every NAND gate here with this gadget. So, this gadget is associated with constant probability and negligible simulation error. And then we figure out how to these different gadgets together. So, this is the resulting compiler. So, one thing I did not explain is how to actually do this teaching, how to argue security when these different gadgets are interacting with each other and so on. So, there are some compositional issues that come up in this case. If you are interested to know more I can explain offline. So, this was about random probing attacks. So, for worst case leakage we do something similar. In fact, the same approach works even for the worst case leakage setting and the analysis is significantly simpler. And to show the randomness complexity result what we do is we have this base gadget. We observe that this base gadget has what we call constant randomness locality. You do not need to know what randomness locality for this talk. And we observe that in every step this randomness locality only increases slightly. So, after k steps the randomness locality is some constant times k. And then note that we set k to be logarithmic and t. And there is a previous work that shows that any leakage resilient circuit compiler that has small randomness locality can be converted into another leakage resilient circuit compiler with small randomness locality. There is randomness complexity. And so we are going to use this result to get small randomness complexity. So, that is the main idea. So, let me conclude. So, we get results in the leakage resilient and the leakage tolerant settings. So, in both of these settings we consider two types of attacks. The worst case wire probing attacks and random wire probing attacks. So, worst case probing wire probing attacks we get optimal randomness complexity result. And for random wire probing attacks we get a construction that is significantly simpler than prior works.