 So, welcome to this lecture on advanced digital system design in the course digital system design with PLDs and FPGAs. The last few lectures we have been discussing some issues in the controller FSM issues. And the last lecture we have looked at the problem of state assignment we have found that it is a an interactable problem to do it systematically. So we have tried some heuristic approach to minimising the area. Then we have looked at the problem of unused states what problems it can create and how to handle it for a fault tolerant finite state machine design okay. So when I say fault tolerant it depends on the application. But nowadays in general it is not a big problem to take care of that because we are not limited by too much by the area. So it is better to take a safe approach we have not completed that maybe the last few slides were kind of remaining. So in this we are going to review that part so at that time I will complete and continue with some more issues in the finite state machine. I am hoping to complete that today and look at the issue of synchronisation briefly. Because we cannot kind of take an extensive analysis and all that in this course we do not have time it takes some quite a few lectures to complete it. But then in a gist you know what is the problem what need to be done at least something which can be done routinely that we will see but there are advanced techniques which you may have to refer to the literature. So let us go into the last week slides last lecture slides. So this is what we have seen we have looked at the problem of state assignment. Suppose a state diagram or a state machine has number of states as s then the number of flip flops are n ok. So which is log s to the base 2 the ceiling of log s to the base 2 ok to make it an integer and now the moment you have n flip flops 2 rise to n possible states are there. The assignment talks about assigning this 2 rise to n to s ok. So for how many possible ways to do the state assignment it is a problem of permutation. Because states are unique and this 2 rise to n possible states are also unique ok. So it is a permutation so it is a permutation of 2 rise to n, s and for even a reasonable size fsm it is a medium level fsm we can say like state is 17 and n is 5 we will end up with a huge number of possible assignments. And suppose our aim is to minimize the logic area of next state logic and output logic then this is an intractable problem. So we look for the heuristic solution to these 2 problems and definitely if you look we are as far as say you take the next state logic optimization wherein we are looking at the next state as a function of the present state and input. So when you minimize we are trying to play with the min terms which is formed of the input condition and the present state. And what we have controlled is the states because we are assigning the states. So that tells that if we look in the next state table and this is what we have controlled you know I have written the assign the state but assume that this is si and this is st we are trying to find and this is sk you know both are sk ok. Now I put kind of numerical values but assume that this state is si this is st this is sk and sk. So if si and st transit to same next state sk under the same input condition then we will end up with say when you form equation for d2, d1 and d0 see d2 has 2 ones and the min terms are like that and you know that it differs since I have assigned this as 0 1 0 0 1 1 it is logically adjacent and when you group it all rest are same and when you play with logic adjacency theorem this q0 literal will go off from the resulting kind of phi literal product them ok. So that is how it happens this can be applied to the more number of states but there is no fun in trying to do that with the 3 states should be in powers of 2 because we can eliminate if there are 4 kind of logically adjacent assignment then we can remove 2 literals then if it is 8 then we can remove 3 literals and so on. But these are as you go higher the chances are less but definitely this like 2 states producing the same next state for same input condition is a possibility. So that is what is shown here and now this throws up and that is what formally stated and I have told that even if like there is a situation suppose these are not same for d2 both are 1 it like if you have exhausted all possibilities and nothing is working out even in this case suppose these are different even d2 is 1 and if you can have logically adjacent kind of assignment at least for the d2 the equation will be kind of area will be minimized because you should know that we are not talking a single kind of logical circuit we are talking about a logic circuit for d2, d1 and d0 which comprises together it comprises the next state logic circuit okay. Now this kind of prompts us how to do the output logic minimization a heuristic which say for a more kind of output we say if there are si, si transit to same sk sorry it produces same output okay because the output is a decode of the present state then this being same if you can make this si and si logically adjacent which is an example shown here 010, 011. So when you work out the minimization for O2 then we see that the Q0 is removed okay so and this can be applied to the powers of 2 like 2, 4, 8 and so on and in the worst case even if it is okay for one output it works okay so that can be done and I am not sure whether the tools do it but then you can write even manually but at least if the tools offer such a thing you can choose some kind of options while synthesizing or write some attributes in the VHDL code to be able to do that by the tool okay. So that is the formal statement then we have looked at this the problem of unused state like you have s states and n flip flops okay and now when you take n the log s to the base tool could be a fraction and then we take a ceiling. So there are some kind of states which is kind of left which is not required here because we are taking a ceiling we are taking the highest integer from this and so we have 2 raise to n-s number of states which is unused. An example is shown here like if number of states are 5 then we will have to use 3 flip flops for binary encoding then there are 2 raise to 3-5, 3 unused state and then we said that suppose this is a state assignment we have used 0, 1, 2, 3 and 4 there are unused state 5, 6 and 7. Now how to handle this unused what to do with this unused state and what we said that by chance if some flip flop change state say here we took an example suppose the state machine was in this state and it by like Q2 has flipped it bit by noise then it gets in here what happens. So at least like we can list out all the possibilities one thing is that we can hope that it get back somewhere okay. Maybe it is 101 it get back to 100 by a flip or whatever you can you know you can think of most probable case you know 1 bit you know flipping and getting back to 100 or if it get back to 001 all the more better or it could get stuck there it could loop through all or some of the states and so on. But the dangerous thing is that suppose it is looping through some states here and it produces some random output which suppose we have not taken care in the design then it could be very pretty disastrous and that is so let us talk about the fault tolerance. And we have seen an example where it can happen suppose we write the next state logic VHDL code like that and we say case present state is and say when s0 when s1 we say up to s4 up to 5th state and for when others we assume that you know let us minimize the next state logic kind of area and we said next state is down care okay this is the down care of the standard logic and then naturally the synthesis tool is going to consider these states you know like 5, 6 and 7 the way it wants you know it will be treated as far as the next state logic is concerned this could be treated as 1 or 0 or 1 like that you know. And the way the synthesis tool take it 0 or 1 decide what happens once it reaches there okay. So we have taken an example the next state suppose the synthesis tool is working on this problem and 0, 1 up to 5 is defined properly and 5 sorry 0 up to 4 and 5, 6, 7 is not defined and assume that 101 we said irrespective of the input condition we have not specified it is a down care. So suppose for D2 it is treated as 1, D1, 0, D0, 1 then what happens is that by mistake like by some kind of error the state machine get into the state the next state as by this table is 101 so it will get stuck there okay. Similarly in the case of take this case you have state 5, 6, 7 we said down care and the synthesis tool treat it as 1, 1, 0 for this and 1, 1, 0 is 1, 1, 1 and 1, 1 is 101 then you can see that it goes to 101 the next state is 110 so it comes here then next state is 11 it comes here next state is 101 so it loops through that. And we have not even looked at what is the output okay output the way you write you know you might say that during this state the output is some state 1 when others you say it is 0. So for all that may be during this 101, 1, 1, 0, 1, 1, 1 all the output may be 0 most of the time it will end up like that and that could be kind of the way the active logic is kind of defined it could be dangerous because there could be some active low signal and which could like you have a maybe reset bar or enable bar or write bar then you will find that that signal is asserted and something happens okay and depending on the application it could be disastrous. So we said the solution so it is not a good idea to leave it as its down care or not specified we have to bring if it gets into a new state we have to bring it back to some valid state you know that is important. Now when I say valid state most of the time at least in the picture I have to show a some state I cannot there is no it is very illogical for me to show the arrows here or here. So I show it at the beginning this need not be true because this is a kind of the power on initialization stage and blindly we cannot bring it here okay so that you should remember a new state should be brought back to a safe state it could be the unit state but need not be okay. So like in the code when you say when others you should say next state is something some safe state need not be in its state you have to look at the application okay do not like the problem with all this is that you by habit you put an arrow like that and forever you will be putting an arrow like the somethings habit builds and people put an arrow happily without ever thinking about it and or just right when others next state is the starting state and you think you are safe it cannot I mean it can be disastrous again depending on the application because there could be this could be a very long drawn control of some huge machinery which is moving say I may be exaggerating but I always whenever I see this picture I see the space division they have a launching rocket you know and normally it gets assembled in one place and to the launching pad it moves you know kind of over a trolley it takes may be half a day or one day to reach there it goes all the way slowly. Now as I said I am exaggerating assume that this is a state machine controlling that movement and by say it has moved 80% and 20% is remaining say half a day is remaining and that state machine gets into this annual state and you just bring it back to the original and that poor trolley which took may be almost a day to reach here goes all the way back there you can imagine much dangerous example like this is definitely an exaggeration but like you can take medical where human safety is involved and I suggest that you be very kind of serious about as engineers very serious about what you are designing okay. Many people do not kind of do not think too much about it but then I suggest that you are working in a team you gather enough information according to the policy of company that may be you are working on a confidential thing which the company does not want everybody to know every detail of it. But at least know the what critical application you are working on and take enough precaution because even for the senior group leaders it is wise to disseminate the required information to the engineers so that they can make a judgment in such scenarios because sometime the designers only know these issues in detail not the team managers sometime so you have to take care of that. So that is what is written here and definitely there could be you might ask why not suppose the state machine was in this state and by noise it has gone there is there a possibility that it can come back to the same state okay. So now that is a tricky question you know that it is at least from without extra information is not possible because this state is something which is kind of memorized till the transition once it transit we are not storing the last state okay we are kind of we are deriving the next state from the current state okay. But we are not like you cannot travel back you know we have no logic to work backwards okay otherwise you should keep a copy of like the next thing do thing is that you keep another register you make a copy. But then the issue comes if by noise you know it gets here how are you sure whether the copy is wrong or this is wrong okay. So it prompts that if you are adding redundancy then you have to have at least 2 copies and you have to take a majority vote like you have the state machine. So you have 3 kind of state transition happening and if something goes wrong you take 2 out of 3 voting and do it. There is another interesting possibility that you can use error correcting code for the state assignment that means that you have to add redundancy to the state it means that in this case suppose we add 2 extra bits parity bits and assume that there is a distance between these valid state okay like if you have learned about error correcting codes the harming code and harming distance and all that at least say 2 bit distance. And if the 1 bit flips then you can decode the maximum likelihood decoding which is the nearest day neighbor decoding and all that. If you have learned some communication you will be clear about it but this could be done but this is at the cost of kind of extra parity bits extra bits and in the case of error doing the decoding and all that you know that extra hardware is required. So which essentially talk about the error probability so you have to really kind of determine what is the probability of error or what is the mean time between failure of the state machine with regard to this unused state. But if it is not a very large number then you have to take a kind of call on implementing this error correcting code and all that definitely you should follow some analysis some reasoning blindly you should not kind of add these redundancies wasting area you know maybe increasing the delay and so on. So that is my kind of call on this fault tolerance but it is always safe when you say when others next state is an unit state at least for this do not blindly write the unit state you know analyze application is there another possibility another probable state where it can be brought back should be thought about. So that is my advice on that so let us move back to the state machine again. So here you see this output logic let us concentrate on this for a while many a times you find that say it may happen that this is quite fast next state logic is fast that means it is able to kind of make the state transition quickly. But this delay is huge compared with this that means that you are slowing down the clock to match this output logic delay because output has to reach at the output. So or it may happen that there is an event and with regard to that event there is a state change and you are producing the output when the state change happens you know that there is a tcq delay from here to here then there is a t output logic delay. So in response to some input it might take a one clock period for the state to change then tcq plus t output logic delay for the output to come. So at least in some cases this output delay may not be kind of tolerable I mean that may be high you know so the output delay is tcq or tco plus t output logic you know that is what is written here. The question is that how can we reduce this output delay if required okay if required it is not that you should try to reduce it if you have implemented you have looked at the various delays and if it is okay with you go ahead there is no problem okay you do not need to reduce it but if there is a requirement to reduce it how to reduce is the question and let us ponder you can think about it okay. Now you are at will to go ahead you know you can when I ask such questions I mean do not fast forward the slide and look at the kind of slide when I ask such a question maybe you should pause and think about it okay. So let us come back to the state machine diagram so we have a problem here when the clock comes it takes tcq time plus t output logic time say so much time for the output to be valid okay and valid output comes after so much time okay. Now the question is that can we reduce it okay now there are two ways kind of if you look at this block diagram very carefully or you say if you kind of contemplate on this block diagram as some would like to put it. So here you know that look at the present state present state is nothing but like upon a clock this next state becomes the present state okay. So what happens like you have an input the next state logic is decoded and is ready here then a clock comes it is transferred here then it goes through the output decoding and the output is available. So let us ask this question why not anyway the next state if it is ready instead of waiting for the clock to come and for that to appear here. Let us take the next state and put this output logic here and take the output okay we cannot take the output because that we are expecting after the clock. So let us put one flip-flop set of registers at the output if there are three output we will put three flip-flops clock by the same thing so that when the clock comes the state change and output also change and we need the state you know now do not think that the state is not required because state is required to kind of decode the next state. So this is very much required but instead of waiting for the next state to appear at the present state and decode we will put the output logic here and then we have to put a set of flip-flops at the output because the state change and the output change okay. So that is one possibility so keep that in mind okay. The next possibility is that is one good possibility the next possibility is that think that there are say five states so we have three flip-flops okay. So Q2, Q1, Q0 assume there are three outputs maybe some right bar enable or latch or something like that can we encode this output in Q2, Q1, Q0 directly okay that means whether we can take Q2 as enable Q1 as right bar, Q0 as latch or something like that okay. Then it is a great thing because they need any logic this is removed and the delay is Tcq okay. Now the earlier approach who also is the delay is Tcq because upon the clock this output comes out of the register okay. So these are the two probable method and now let us look at the diagram so this I have written. So this decoding from the next state looks like this you have initially we used to put the output logic here. Now we put output logic here the output of the next state logic and we put the registers for the output and which is clocked by the same clock because it has to the output change has to synchronize with the state change okay. When this next state for which the output is decoded becomes the present state that output with regard to that next state is available at the output okay. Now there is an issue look at the register to register path because to decide on this clock frequency we need to consider now two path one is this, this red line that is from the state flip flop Q2, Q1, Q0, 2D to D1, D0 and there are 3 into 3 9 possibilities like Q2 to D2, Q2 to D1 and so on okay. So 9 paths are there so we have to say Tcq plus T next state logic plus T setup is a clock period. If you look at the other path where from this state flip flop through the next state logic through the output logic it reaches this output flip flop. So you will have Tcq, T next state logic, T output logic and the setup time okay. So this is like you will be asking okay fine the output delays register I mean reduced but what about this clock period now the clock period might take a bad turn because it could be more but mind you there could be some kind of consolation because next state logic is a combinational circuit. The output logic is a combinational circuit now it is possible to put it together and minimize it okay. Now instead of decoding from the input and the present state the next state and then decoding the output logic we could what I mean is that you can think of this as a single circuit where the output is decoded directly from the input and the present state. So if the tool is able to flatten it you know put as a contiguous kind of circuit and minimize it maybe this next state logic plus output logic delay might be comparable to this original next state logic delay then we have done it nothing is lost and output delay is reduced okay. So that is kind of one way of dealing with the output delay now mind you what with regard to VHDL coding is required is that we used to write initial at the beginning like suppose if you are writing a process we will write case present state is when as 0 what are the outputs which are like 1 and 0 we write. So here instead of saying case present state is because if the output logic was here we say case next state is and then that will generate the output and then you can register it or we can write this register and this logic together in a process because we have seen that a registers with the preceding combinational logic can be written in one kind of process okay. So you can say if reset is 1 then like all the outputs are 0 1 by 1 then it is a else if rising edge of clock then you say case next state is. So this will be taken care okay so that is with regard to coding it is not a very difficult thing to code straight forward so it is a matter of coding it some change in the coding then you get it not much of a detail it is a minor detail okay. So the critical path delay is Tcq plus dnsl tol plus tsetup. Now if you look at both the delays there is no much difference like we have to consider from the previous clock delay okay the output okay to come back equally that means that like in this a clock comes then tcq, t next state logic then tsetup then again tcq and t output logic I mean that is how because we are now decoding the output from the next state. So we have to work from the previous clock period then only it can be compared but if you compare that like you have in the in this case you have tcq plus tnsl plus tsetup plus tcq plus tol okay that is a case that is what is written here. But if you look at this same thing tcq plus tnsl plus tol plus tsetup plus tcq so only the order is different from the previous clock edge you know the total delay same but after clock edge this will give you only just one tcq you know that is like earlier the boundary was here so you like after clock edge you have to get tcq plus tol but here after clock edge only tcq comes because the tol goes before that okay so but our only hope is our consolation is that when is both are minimized together this tnsl plus tol could be greater than this tnsl plus tol because that can get minimized okay. This cannot get minimized because there is a register boundary coming in between there is a next state logic then there is a flip flop here and output logic but here if you look at we have moved output logic before so between one register and the next register you have both together and that can get minimized okay. So from this kind of expression itself for a clever student you can make out what is happening because I have written these terms in that particular order okay so that tells you what is the advantage. So that is about output decoding from the next state so just a summary we have started with the unused state and we said that for fault tolerance that you have to bring the state machine to a safe state this is a good practice for irrespective of any design do bring from the unused state make a transition to a safe state. Then we have looked at the problem of reducing the output delay and we said there are 2 ways one is the decoding the output from the next state logic than the present state but you have to register that output to be kind of coincident and with the state change. And we have seen that from a previous clock edge point of view there is no difference we are playing with we are moving some logic which was after a register to the before the register but in effect you have the output delay is reduced from tcq plus tool to tcq alone. But now the 2 combinational circuit is within between 2 registers and that can be optimized and we are hoping that the clock period may not be affected so much you know that is the crux of it. Now let us look at the next technique where the output is encoded in the present state and if you remember the block diagram if you remember the lecture we have started seriously not the introduction not the course policies and all that when we started this course the first lecture we have learned about the synchronous circuit as a kind of structure of the sequential circuit. This is the kind of the structure of a synchronous counter okay but the counter may not be counting in strict sequence you know that you should remember. So you can imagine now we are back to a counter which is a maybe a crazy count it may go through it may go through all kinds of sequences depending on the input but that count output or the state output itself is used as output and maybe at the outset you might think that no this is not going to happen this is not possible okay mind you it is more probable than you think because the reason is that we have we are not worried about the particular numerical value of the state you said that we when we develop a state diagram we work with symbolic state we say S0, S1, S2 and so on then we assign it to reduce some area and all that. So the same technique can be applied because we have some two output and two flip-flops say we like we have the freedom of choosing the state. So looking at the output pattern requirement if we go back and do the state assignment then it is possible that this might work okay. So that is the moment I say that that should kind of trigger some light in your brain okay. So let us get back to the diagram so here addition to that okay now let us look at it maybe we take an example say take this example okay. So here the output delay no doubt it is a TCQ because as soon as the state changes the next state the present state get next state and the output is same as present state so it is valid. So the output delay is TCQ exactly same as the previous technique and assume that in our case we are four states S0, S1, S2, S3 and there are two outputs assume again. Now this is definitely you will accuse me of cooking it up yes I have kind of cooked it up but these are the kind of possibilities like you have two outputs right bar and enable and if you care to look at it the S0 the outputs are 0, 1, 1, 0, 1, 1, 0, 0 okay. So these are unique patterns 0, 1, 1, 0, 1, 1 and 0, 0. So why not to the state S0 we assign 0, 1 like Q1 get 0, Q0 get 1 and S1, 1, 0 and S2, 1, 1, S3 and 0, 0 that means that straight away the Q1 can be used as right bar and Q0 can be used as enable. So many a times you do not even look at that possibility it may happen nowadays what happens is that you do such a kind of suppose say the pattern was 0, 0, 0, 1, 1, 0, 1, 1 sequentially and we have used enumerated data type then internally the synthesis tool has done a sequential assignment. We have seen that most synthesis tool will do a sequential assignment which is nothing but 0, 0, 0, 1, 1, 0, 1, 1 and it will automatically match you will find that when the equation of the output is derived the right bar will be you will find that is automatically Q1. But here it is not such a kind of nice kind of matching like S0 is not 0, 0, 0, 0, 1. So synthesis tool may not do though it is very simple synthesis tool may not do that trick. But we have looked at the kind of changing the state assignment by some attribute like state encoding attribute, enum encoding and attribute and so on. So if you have used enum encoding and assign this state then you get you know without any output logic to output. So this even compared to the previous technique this is a very kind of possible technique which you should look at it okay. So I have told you the reason why it works okay because we do not care about the state assignment. So we can do that state assignment maybe it may not minimize the next state logic or output logic. Output logic definitely because there is no output logic at all okay. So this is quite neat still you will accuse me of kind of you know manipulating it to look very nice possibility. Yes I agree that now what we have done that there are 2 outputs there are 2 raised to 2 possible patterns okay. And so 4 possible pattern and we have exactly 4 states and these each pattern is not repeating it is unique. So everything works out very nicely for us what if like in this case what would have happened if say in S2 the same 0, 1 appears you know then this there is a repeat. So there no unique output pattern to distinguish the state okay. So that is a possibility like we have like this case you look at this case here the same scenario where the output pattern is different in state S1 the output is 1, 0 S0 it is 0, 1 S2 is 1, 1 but when it comes to S3 it is again 1, 0 okay. So there is no way now to use Q1 as a right bar because these 2 states are kind of identical but we can do one thing we can add an extra flip flop okay. So actually to encode 4 states we need only 2 flip flops but for us to reduce the output delay what we do is that we introduce one more flip flop for the present state no harm okay absolutely no harm. So that is what we are going to do it we introduce like Q2 there were only 2 flip flops we introduce an additional flip flop and where this pattern was repeating we made it different by making this extra bit 0 in one of the state where the output is repeating and in the other state where the same output pattern is there we put it 1. So now you look this is 1, 0, 0 this is 1, 0, 1 rest of the places you can make it 0 or 1 it does not matter. So we have made it 0 there is no particular reason but yeah you can make it 1 also like this is something you should know in kind of there is no great reason for 2, 0 or 1 like as a pure logical exercise. But there may be some repercation with regard to the circuit because if you think of an animal circuit if the gate is 0 it is off gate is 1 it is so like there could be some differences something is made active the current is sinking. So you should think about those scenario but then what I am saying is that we can safely assign the default bits of 0. Now what we do is that we say state 0 is 0, 1, 0, state 1 is 1, 0, 0, state 2 is 1, 1, 0, state 3 is 1, 0, 1 okay. Now like then we use Q2 as a right bar Q1 enable and Q0 we do not use it Q0 is a part of the present state because we have added this to make this output unique like for this repeated pattern to come in this 2 different state we have added extra bit. So but you might ask now you have 3 flip flops and there are 8 possibilities and we have only 4 valid state there is a new state that has to be brought back and that needs some decoding all kinds of thing okay and that may have some repercussion. But if it is going to all 0, 0 it may not add to the circuit so on but you think about it what are the possibilities. So that is a game in encoding output in state bits you do not have to first like you do not have to really worry about like a number of output and number of state bits and how many patterns are repeating like what are the total possibilities which is greater which is less and all that none of this serious analysis not required what we are looking is that what is a repeating pattern okay. So definitely if the number of like you have some 16 states only 2 outputs that there is no way to kind of encode like encode all that you know the state bits using 2 patterns so you need extra bits. If the number of outputs like 2 raised to number of outputs are kind of less than the possible state then you need any way extra bit whether it is repeating or not. But in general you can look for the maximum repeat and try to make a difference because if there are more outputs and less states definitely there is going to be repetition okay. So that you should understand that so let us take another example where this is little more kind of complex. So we have 7 states S0, S1, S2, S3 so S4, S5 and S6 and we have 4 outputs okay. Now once again I have put 4 outputs so possible patterns are 2 raised to 416 which is greater than the number of states so like this should be enough okay to encode but you see there is repetition okay. So you see that in state 1 these 4 outputs are 0, 1, 0, 1 like that and in state 0, 2 and 4 the output pattern is 0, 0, 1, 0 it is repeating okay. So we have 3 repetitions to make a difference we need 2 bit extra bits. So we added that and we have assigned 0, 0, 0 here, 0, 1 here, 1, 0 here 2 kind of distinguish between these 3 and between these 2 we can make 0, 0, 1, 0, 1, rest can be 0, 0. So we now assign in like Q5, Q4, Q3, Q2, Q1, Q0 and these are the kind of the state bits like 6 flip flops frankly we require only 3 flip flops but then in this scheme we end up with 6 flip flops and possible states are 64. But we get now the output directly encoded in the state bit like you have Q5 as address 1, Q4 as address 0, Q3 as write bar and Q2 as enable. So this is a good mechanism to reduce the output delay. So the rule is simply stated identify the state with same output value from this there could be multiple of such from these identify the state where 1 output pattern repeat maximum okay. So there could be like this case there are 2 state where output pattern is repeated there are 3 states where the same output pattern is there pick up the 3 okay. Now check how many extra additional bits are required to make a difference make it and use the original bits where we started like Q5, Q4, Q3, Q2 as output then we are done. So that is encoding output in state bits. So quickly running through it like this is the game we are kind of encoding the output in the process state at the beginning it looks a kind of impossible kind of thing to do but then we remember that the state assignment is something which we have the control flexibility. So why not do the state assignments at that such a match happens and that is very easy when the possible patterns and the number of states matches then you can do straight away there is a repetition then you have to take additional bits and definitely as I said if the number of state bits 2 to the power of number of state number of outputs are kind of less you need anyway additional bits otherwise if it is greater then we have to look at the repetition. You can work out that kind of case and then you can do a proper state assignment to encode the output in state bit which reduces tcq all together it throws the output logic but definitely you should be asking this question. Now we are playing with the state assignment what happens if this increases the next state logic delay yes these kind of question should be asked analyze I do not think the tools do it because the tools many a times choose a kind of fixed kind of state assignment with which this cannot be done. But then you can do a like in a at least in simple cases you can do an analysis and try to do this yourself maybe there are the tools complex very good tools might try to do this you have to check the tool manual. So that is what is maybe the last FSM issue that I am kind of discussing in this lecture. Now we have another issue called synchronization so that maybe we will complete that in the course of the next lecture and then we have to do maybe we will look at the devices called programmable logic devices then we kind of play with the tool before getting into maybe FPGA. We have to learn the test bench to be able to use the tool because I think we have learned enough to write the VHDL code for data path and the state machine. Because you know all about the coding the combinational circuit various syntax what it means how the simulation work how the concurrency simulated just for your understanding. And we have looked in detail about the sequential elements sequential circuit registers how to code using various construct what it means and then we have looked at in particular about the finite state machine as a separate lecture we have handled it so that we have good grip on that. So this is good enough for synthesis but to be able to do a good development then we have to write the test bench. So I am planning to cover the test bench maybe I will in the next few lectures I will try to cover the programmable logic devices. These are being used less and less nowadays not too much application but from an academic point of view maybe it is wise to look at it it is a nice architecture but it does not scale to accommodate kind of complex circuit and it also has some certain problems like lack of memory lack of registers and so on. But for certain application it is good as an academic exercise to look at its architecture is a good point because it tells how that architecture is evolved and the thinking process behind it is good so we will look at it. I do not teach that in my regular course because that is not being used very much so that I kind of avoid but then the course name itself had PLD at the beginning when I gave the syllabus sometime back so I will stick with it I will cover it maybe it will be definitely academically useful though maybe application wise it is not you may not kind of end up using it I do not know what happens after few years if you are kind of this is being recorded in 2013 what happens if you are listening to this lectures in 2015 I do not know whether that PLDs will be useful. But in anyway as I said I will be covering the kind of synchronization in a one lecture also then PLDs then the test benches then we can look at the FPGAs and AK study and play with the tool to wind it up and that will be a kind of good conclusion. So I think today we have looked at basically a new state transiting back to the safe state then we have looked at that was for fault tolerance then we have looked at the techniques to reduce output delay one was decoding the output from the next state and registering it and we have seen that analysis wise there is no kind of difference in terms of the terms involved but there is that within the register boundary the output logic and next state logic is coming together the minimization can happen may be the total critical path delay can come down second thing was that the decoding the output in the present state though it looks kind of a less probable situation we have found that it is quite useful thing to do and we have looked at that technique the algorithm for it. In the next lecture I am going to handle the problem of synchronization very important thing as I said I cannot do all analysis come out with various the expression for the fault tolerance and all that we cannot go in depth I cannot go into the flip-flop this is something do with the flip-flop I cannot go in normally in the course I go into the flip-flop try to analyze bring out this issue why it happens a deep understanding from the that point of view but then if you accept that problem we will see at least how to handle it the most simple and most used techniques we will look at it without that I feel the course would not be complete so we will look at it and so I hope things are coming to the end of the course please or otherwise otherwise when we kind of tying everything together at the end you will be at loss so because when we have reached the FPGA then we will be kind of putting everything together we will be putting the digital system basics we will be putting the VHDL the FPGAs the tool maybe some board exercise everything together so unless you have a good grip it will be difficult to follow please go back and revise learn it well and I wish you all the best and thank you.