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Published on Sep 27, 2012
Keynote at the FPL2012 conference http://www.fpl2012.org Slides: http://fpl2012.org/Presentations/Keyn... Over the past decades parallel processor speedup has been an elusive quantity for a broad class of applications. Yet with the end of performance scaling for single processors the need has never been greater. The problem is not technology but programming models. One answer to this speedup problem is to create an idealized data flow machine that exactly correspond to the application and stream data through the resulting machine. This approach can be emulated with FPGAs, providing more than an order of magnitude speedup even as executed as an emulation of the data flow machine.