 Hi, please introduce yourself. I'm Steven Dundt, I'm the operational manager of IMAIC ICLINK, so I'm responsible for the technical operation of chip services. Anything from design to supply chain of A6, application-specific ICLINK. So what's the latest technology you're showing here? We are able to provide customers with 3nm technology, which is the latest technology from TSMC. We're a broker for TSMC, Value Chain Alliance partner. How do you make it work so small? Well, TSMC makes it work so small. Well, but they are a partner of IMAIC. IMAIC is a research organization based in Leuven, Belgium, and some other parts of Belgium in the world, where we do research on new transistors concepts, new materials, new ways to make it work. So we're actually helping the foundries to make it work. I personally don't know too much about it, because I'm using the technology to make chips, to make functionality, and we abstract the smallness of everything to do that, obviously. What are you showing here? We're on our booth now at Embedded World, and it's hard to show things that are really interesting, but this thing is a mask of a mask set of a TSMC chip. Several chips, you can see several chips on the mask. In this technology, I think there's 36 masks that are used to create chips on wafers, like the one that we have here. This is one that comes out of our research fab. It doesn't have a product chip on there. It's test structures. So there's a mask before the wafer? So there's several masks that are used in a process where it's layer upon layer upon layer upon layer that is creating the transistors and the interconnect between all those transistors. And somehow the mask is square and the wafer is round? In which part of the mask? What is on the mask is repeated on the wafer. You can see that pattern here as well. So light is shown through the mask on the wafer where this photo is on the wafer and the mask is stepped, as we call it, over the wafer. So the same pattern is coming back many times. So there's many, many chips on one wafer. Why do you have a 6x5 here? Well, what you see here is the reticle of the wafer and for this chip, we were able to put it several times in there so that we can get more chips from a wafer. It's optimizing the area, the silicon area and the cost-hands. A very good mask on the 3 nanometer tech cost millions and millions and millions of euros. It's a set of masks in the 3 nanometer. It's in the order of 50, 60 masks, something like that. And well, yeah, it's cost... That's a lot of money. Many millions. And somehow this mask has zero defects or something. Like, you need to be very reliable when you make chips. Mask writing is a very important part of chip making. So yeah, there should not be any defects on the mask because otherwise every defect will translate into a wrong chip. How do your colleagues and yourself have the capacity to design something so complicated that just... As I said, we're abstracting. It's by using abstraction. It's by not looking at transistors anymore but at logic gates and not looking at logic gates anymore but at building blocks. That's the only way we as humans can grasp the millions and millions and millions of transistors that there are on one chip. Is it a game of software and the software just takes care of it? Or do you have to...? We wish. There's a lot of software and the software takes care of a lot, of course. You cannot place every single transistor in a multi-billion transistor chip, of course. There's a lot of software help. There's a lot of pre-built made blocks. But the human in that process is very important. We have to know what we're doing. We have to know the goals. We call it PPA optimization, power performance in area. And that's a human thing. There are tools that are integrating AI as well in this process. They're pretty new but still the human is still the factor, right? I won't be able to zoom in on 3nm. This is not 3nm. The way they're designed... When you look with a human eye, it kind of looks random, right? But you have to think of heat dissipation around the chip, like put things in the right place so they don't... There's many things to take care of. There's like the power mesh on the chip, for example. All the transistors in the chip or all the gates in the chip have to have the right voltage everywhere in the middle and at the edges to be able to work within the right timing. And if that's not the case, your chip will not work. Or it will not work intermittently, which is even worse. And when you do the right design, the yield is going to be great and better and better as they get used to it over there in the fab. The yield is mostly related to the process itself and the layout of the chip. They work together. So you have to make a layout that yields very well. And there the tools help as well. At the end, just before you're taping out, as we call it, go to production, then we do a check, which is a design rule check, which helps you to show that your design is producible with a good yield. How do you define your role at IMEC? Are you very much working towards it with the EDA industry? What is your... Well, obviously we are using EDA tools and IMEC is working together with EDA companies also on the creation of new knowledge in the field. We are users of EDA and we work with the whole ecosystem of designers, foundries, packaging houses, all sorts as we call them, failure analysis companies, etc. So what kind of discussions you have here at the Invented World? What people come to ask you about? It's nice to see a lot of people after Corona when we talk about future possible projects, new people or new customers that are coming with ideas to create new chips, partners that we haven't seen in a while, the design partners, EDA companies. Is there a lot of themes like the Edge and IoT and low power microcontrollers and everything and you have a role to play in all these different things? We help those companies make their chips for us. It doesn't really matter which application it is but obviously we see some applications being more sought after than others. There are these things that are hot, like AI for example. All right. Yeah, that's one new thing they did, because when you have three nanometers, there's so much space on your chip and they just put the AI and stuff on the big part of the chip now to take advantage of all these space, right? Maybe. I don't think it's more like that. The silicon real estate is defining your cost. How big the chip greatly defines your cost. So putting something on there just because you have the area, I haven't seen it happen really. All right, cool. Thanks a lot. Okay. Thanks.