 So, welcome to this lecture of digital system design with PLDs and FPGAs. We will have a quick run through the last lectures part. In the last lecture we have seen the timing analysis of the controller, how to go about designing the control algorithm using a state diagram and so on. So, a quick run through the slide then we will start today's part. And we have looked at the maximum clock frequency, we have to analyse 2 paths, one is a register to register path and the register to output path. And we choose the maximum as the minimum clock period and as I said that this output can go to some other register through a combinational circuit, then one has to account the whole path from this register to that register. But in the absence of that knowledge I have shown up till this point, but you have to keep that in mind. And similarly exactly like the synchronous counter case, the whole time violation is this is the inequality the tcq plus tlogic should be greater than the whole time. Otherwise there will be whole time violation and if there is a violation then you have to increase the delay of the logic. So, that because as I said everything is we are analysing with the same edge. So, it has got nothing to do with the clock frequency, but in the first case we are our analysis is from one clock edge to the next clock edge. So, if there is an issue, if this is not satisfied you can increase the clock period or reduce the clock frequency you can solve it. So, whenever there is a slack is negative, the margin is negative you can decrease the clock frequency or increase the clock period. But when there is a whole time violation you have to see how to increase the combination delay in the path or do something else which we will see maybe some other techniques may be as we go along. And we have looked at the controller design and many a times when we design a controller we have a text kind of specification and from there we will have to derive some sort of sequences then some waveform. But then there may be quite a lot of possibilities we have to work out and always humans are good at using graphical tools. So, we use a graphical tool like flowchart called state diagram which captures the various steps in sequence or states and depending on the input it is transition in each step or state what are the outputs. So, that is basically what we are going to do. So, in a state diagram states are represented by oval or circle transitions by arrows and output is associated in a block with this oval essentially we will be able to once you draw that we will be able to come out with the two table of the next side logic and output logic after the state assignment. So, we have seen some kind of unconditional transition going from one state to other state on the next clock edge and here we have a transition depending on an input that means if the machine is in this state or step when input is 1 it goes here input is 0 it is a branching condition and very other useful condition is that waiting for some signal to become active. So, here as long as this enable is not active you remain there the machine remain in the present state as 0 and when that becomes active it goes to the next state both are conditional transitions. So, let us we have looked at the outputs we normally specify the output associated with the state and again in textbook cases sometime there is a habit of writing the output you know like input slash output and all that. This works for very kind of simple cases where there is only few inputs and few outputs but when there are lot of output that cannot be done. So, it is better to write separately so this is what is done here. So, in this state these are the output signal so this is a direct decode of the state and in this state the read bar has become 0 and the latch has become 1 and in the case of mille output we write the output is a function of the input in this case the input is same input is used for the transition condition. But as I said earlier it need not be it can be another signal which is not an input to the state machine per se. So, that captures the kind of the state diagram basics and we have looked at a multiplier kind of state diagram controller for multiplier data path and as I said normally like in software you come to a state where everything is inactive then wait for some signal then you come to another state initialize everything. Then come to a main computation state and iterate it through many clock cycles and when the computation is done you go back and wait for the next operation and we have also seen that from the input and transition you can write the next state table and from the state and the output each output we can write the output table. So, from this we have seen how to write the next state table and the moment you write that you can form equation for D1 D0 minimized and so on. But in our case we write this diagram in some hardware description language and the tool does everything you know tool does the state assignment tool does all these minimization and all that and output table in our case is a function of the present state. So, 4 outputs we write as a function of the present state and then you can form equation for each output minimize it implement it again in our case we will write the state diagram in describe the state diagram. Then the tool will take over and do all the kind of minimization and implement it and that is it and I also said that this is this next state table and output table is kind of equivalent to the state diagram because all the information for this is there. So, the moment you draw the state diagram the game is over the design is done rust is a kind of automatic process which the tools can do very well. So, with that I think we will move to a case study to basically this case study is to kind of illustrate the controller design than the data path design we will we have seen at least the data path of the CPU. We will take the data path design in another case study when we kind of little more proceed further at this point the case study I will give more importance to the controller and as I said it is a simple case study but it is realistic to it is it can be used in real life it is not that you know something very simple I cook up and most often most textbook shows something like a traffic like controller is a kind of favorite example for most people because everybody experience that case and one knows all the specification and the clearly from the kind of day to day life experience but this whatever I am going to discuss also for an engineer is a familiar scenario very simple scenario. So, let us go to that case study. So, the case study I have taken is a data acquisition system. So, in a normal like you want to capture some analog signal and take the digital samples and do some kind of say digital signal processing on that is our system okay. So, normally you have an ADC maybe a single channel multi channel we do not care much about the number of channels but we assume that it is a quite a fast kind of ADC which captures high frequency analog signal okay. So, now normally the ADC is interfaced to a microprocessor or microcontroller some kind of microcontroller or microprocessor and what is done is that the processor you know give the tell the ADC to start the conversion then when it is done it is read through this example I have worked out is little bit old maybe the present day interfaces are not parallel interface like I2C or SPI interface but I am showing a parallel data interface from an ADC in this case but this can be translated to the whatever is the latest interfaces available. But we are assuming that this particular processor is used for you know it is an embedded system and the processor is kind of working on many things and now if ADC acquire sample and interrupt the processor every now and then like suppose it is an 12 bit ADC every time one sample is acquired or few samples are acquired if processor is kind of interrupted then everything slows down. So, our idea is that we design a controller or design a system where our controller will give the tell the ADC to do the start of conversion and when the ADC say it is done end of conversion is done we will store the sample somewhere in a temporary it will be stored in some place and when that storage is full we will interrupt the microprocessor and or the controller will interrupt the host CPU and the host CPU comes and in a burst okay read the whatever was in the storage. So, that basically to kind of free the processor from kind of per sample overheads okay because if there is a real time moist running on the processor these interrupts can be costly because there is a task switching to make this active and read and then continue with the other task. So, all that is avoided so that is a basic scenario what we are going to do. So, I will put a picture so this is the and it is always better to write a picture better to draw a picture which brings in clarity okay. So, we have an ADC as I said I am showing a bit old ADC with a kind of parallel interface and not a command through SPI or I2C. So, here you have an analog clock analog input and there is a start of conversion to the ADC and when ADC is completing the you know the conversion it gives an end of conversion. Then the idea is that we put this data into a temporary storage and this is a host interface. Host will give a start signal to start all operation and then we start this business you know continuously keep on converting and putting it to the storage and when the storage is becoming full we interrupt the system will interrupt the host and host will read the data the output of the storage read the data using this host read signal. So, that is a basic idea so we have to have a data path you know data path is very simple we need a temporary storage. So, we need to read the data from here put it to a temporary storage and the output of the temporary storage goes to the host and all these condo signal you know the start of conversion looking at the end of conversion giving an interrupt and so on should be done by the controller or look at the start signal and so on ok. So, the question is what is the best kind of temporary storage and definitely it has to be a memory ok that is very clear but you see that this memory a normal static RAM if you put it has one address bus and one data bus ok but this ADC side has to write and the host has to read ok. So, a single port may not suffice in this case like if you have only one address bus and one data bus that has to be switched between both sides you know you need some kind of multiplexing and it can become complex. So, normally one would think that ok why not use a dual port RAM so in a dual port RAM you have two data buses and two address bus. So, we can use one kind of bus here to write and one kind of bus here the second port to read ok. But if you think for a while a RAM will allow a random access ok that means this input side can write to any location and the output side can read from any location and it allows kind of other way like from this side you can write and this side you can read. But in our case if you look at it the data flows only in one direction it does not flow in other direction and we do not care about the random access and all that like we are getting the analog samples you put it in a sequence the first sample comes here, second sample here, third sample here and so on and the host need to read in the same sequence. There is no point in reading the fifth sample, seventh sample, second sample and so on. There is no random access it is a one way flow. So, DPRAM is a costly solution most of the features are not required. So, if you again if you know the various memory technologies the best solution for us that if you is a one way flow and it is a first in first out kind of read like you write first and you whatever is written first is read first. So, what is required is a FIFO here ok that is ideal solution because FIFO you write in one side read from the other side and there is no addressing like addressing is implicit in a FIFO because there is a write address register on read address register or you can say a write pointer and a read pointer at the beginning both point to the first location. So, you start writing then it write pointer increments you start reading read pointer increments and definitely the read should not overtake the write and the write should not kind of come below like it should not overwrite. So, there are some control signal like empty full and all that FIFO gives to kind of synchronized that means when it is empty you do not read when it is full you do not write and so on ok. But that is FIFO so the FIFO is the best solution in this case. So, let us try to put it and you know that the controller gets a clock and a reset the controller has to give this start of conversion. And when the end of conversion comes the controller should know that and the start signal from the horse should come to the controller to start the whole operation. And this FIFO need a write signal that has to be given by the controller and the FIFO this data can be connected to the data input of the FIFO. This data can be connected to the data output of FIFO and the read signal of the horse will come to the FIFO read. And how to give this interrupt signal ok now the FIFO has various signals like full half full and three fourth full and all that ok. Now like if you have a full signal and if you connect that to interrupt it may be dangerous in the sense that when it becomes full you give the interrupt and the CPU has some OIS it does all the task switching at least it has to before going to the interrupt service routine even if it is simple system. It takes quite a few clock cycles by the time it comes to read it it must have over a term because we are continuously doing this operation suppose the host is not stopping it it will all right. So, it is very safe to use a three fourth full signal as interrupt. So, by the time the host comes here then the data is not you know the temporary storage is not yet full and nothing gets lost in the process. So, that is a basic kind of block diagram. So, let us look at it you know that is this is what I declare I mean I have told the DP RAM you can put but the random access we do not require it is a one way data flow DP RAM allows two way data flow. And it is quite costly because of multiple ports and it is too complex for the application the ideal solution is a FIFO it is very simple to use the addressing is implicit and it is enough for the application. So, I have put whatever I have told ok. So, you have a controller which need a clock and a reset the start signal comes from the host start. So, when the host say start whole operation will start the start of conversion is given by the controller the FIFO write signal is given by the controller because controller knows when is the end of conversion coming here the end of conversion is coming to the controller. Then it will give the FIFO write that this data is connected to the data input this output data is connected to the host interface the host read is connected to the FIFO read and three fourth full is given to the interrupt. So, that when it is three fourth full the host can come and read the signal ok. Now, we will make some assumptions. So, one thing is that like when the interrupt come and the host comes and try to read it by the time may be that we have the controller has written or the ADC has written quite a bit of data more than the three fourth. So, the question is that like we are not giving any other handshake signal like empty or full to the host make it keep it simple. So, the one question is that how much when an interrupt comes how much the host should read ok. So, we are not sure like but we are sure that when the three fourth come the 75% is full. So, let us assume when an interrupt comes the host will come and read less than or equal to 75% but fixed like it will read 75% or it read 70% does not matter ok. So, it will read somewhere around less than 75% all the every time the fixed amount ok. And anyway that there will be something remaining which gets pushed when the new data comes again it gets filled and it comes and read the 75% ok. And may be the last time you know the when the host stop it and may be there is some data remaining there we do not know how to empty it unless there is you know other handshake signal. So, may be that is ok like you say stop you remove the start then the interrupt comes or interrupt does not come some data may remain there it is ok like we will lose some data there the last cycle once it is known this can be taken care there is no issue. So that is the first assumption we make when an interrupt comes the host read something fixed amount less than or equal to the 75%. Second assumption we make is that we will not impose any constraint on this start of conversion pulse that means that we say some kind of narrow pulse is given to the ADC that will work you know that is one assumption we make. And but when you write to a memory write to a FIFO we need a definite width pulse width ok some minimum pulse width is required for write we will try to meet that ok. So, these are the assumption we make one is regarding when the interrupt comes how much to read the timing of the SOC pulse and the timing of the FIFO write signal ok. There is no much constraint on this as some narrow pulse will do but here you need a definite pulse width for FIFO to write ok. So, that is assumption we make now so that is written here like host processor will read something less than or equal to 75% the SOC is a narrow pulse and frame write FIFO write signal timing has to be met correctly minimum it has to be maintained ok. Now what is the next step you know like we have put a block diagram so the question is that what is the next step and can we go to the kind of control algorithm the state diagram no I think the very important thing is that we have to draw the timing diagram. So, the input and output relation from this description and referring to the various systems we use maybe you have to refer to the ADC data sheet to get the ADC timing we have to read the FIFO data sheet or FIFO we have to know like if you are designing the FIFO yourself you should know what are the timing parameters of the FIFO. Then we draw a timing diagram showing the input output timing waveforms so that is the next step. So, let us write the timing diagram so I have shown the timing diagram in the slide. So, here you know you have at the beginning the start is low or inactive so all the signals are inactive SOC is 0 end of conversion is kind of 0 and the FIFO write is high because it is an active low signal normally the right signals are active low it is kind of inherited from the TTL kind of logic because where you know the active high signal does not source much current and active low signal is the one which is sourcing the current so most of the time the write is inactive. So, to reduce the kind of current this was made inactive but with the CMOS that is not a big deal but anyway this is kind of inherited from the previous technology. So, if you look at that the timing diagram when the start goes high then the controller detects it and give a narrow start of conversion. The moment the start of conversion is given and this shows the continuity we do not know how long it take the end of conversion to come. So, this shows some kind of continuity maybe it is continuing and then the end of conversion comes the moment the end of conversion comes the controller has to give a write signal of certain width to the FIFO and the FIFO gets written and we terminate the controller terminates FIFO write and after that again look at the start signal and if it is 1 then give the start of conversion and repeat the whole process. So, this is the kind of iteration we do this whole process starting here it is continued if the start signal is high at this point. So, that is the basic kind of waveform and from where we derive the control algorithm okay but the next question to ask is that how do we generate very precise timing for this FIFO write okay. So, here this start of conversion is a simple thing what we do is that we come to a state at the beginning SOC was 0 when the start signal come we can come to a state make SOC 1 and transit to another state and make SOC 0. So, for 1 clock period duration when that state machine is in that state this SOC will be 1 and you get a narrow pulse okay it depends on the clock frequency which we use for the controller. But this pulse can be of 1 clock period duration if you want 2 clock period duration make SOC 1 for 2 states then you get 2 clock period duration. But we assume that there is no great constraint 1 state duration is good enough for this case but the question is that how to generate a pulse of certain size okay. So, taking Q from what I have described one ways like when the end of conversion comes go to 1 state make it low. Now if you know the clock period of the controller suppose it is say the it is 5 nanosecond and you need 25 nanosecond width for the FIFO write then one thing to do is that first come to a state where the FIFO write is low transit to next state where FIFO write is low and go on doing that for the 5 clock period or 5 states then you will get a clean pulse. But then this is quite kind of cumbersome suppose we kind of updated this design with a faster FIFO then the state machine has changed the controller has to change maybe only 3 states are required instead of 5. So the question is that can we move this kind of timing from the implicit state which we add and move it elsewhere okay. A subsystem we add that will keep track of the kind of width of the timing pulse then it will be ideal because if there is a change in the width of the pulse we can modify that subsystem easily maybe there is some flexibility to do that. So that is what I have shown here so one way of doing it is that controller is going through many states which match with the width of the write timing it might occupy too many states and modification is difficult like you get a slower or a faster FIFO then you have to modify the state diagram and redesign the controller. So why not we use a counter we keep a counter okay so what we do is that we keep a counter and when the end of conversion comes it goes to a state and make the FIFO write low and start the counter okay. Now wait for the counter to reach a particular count and that we can decode using a decoder and that signal is given to the controller and when that signal comes we go to the state machine go to a particular state a new state and terminate this FIFO write is made one. So this is more elegant because the counter maybe like we use a 8 bit counter so it can choose various kind of count can be decoded okay. So you have a flexibility of choosing many counts many values and only the decoder need to change okay if you at the beginning itself depending on some the range of the access time of the FIFO you choose a counter width to accommodate kind of all kinds of possible ranges in future then only the decoder need to change it is very simple decoder is many a times an AND gate with inverters so it is very simple to redesign. So that is what we are going to do that. So now I will show the modified diagram with the subsystem so everything else remains same now we have a counter which is outside this our data path and which is clock by maybe the same clock or a derived clock from here normally there is no reason to use any other clock than the controller maybe I will touch upon it why it is so. But yeah there is no need to use a lower clock than a controller clock because unless it is available in the system okay if there is a lower clock than the controller is available you can use it. Otherwise suppose this is 10 megahertz if you plan to use 1 megahertz anyway you need a clock divider which is nothing but a counter so that division can itself happen here okay not a big deal. So and there is no point in using a higher clock than this because this clock is lower which will not be able to catch again we will discuss that business later. And you see the counter as a reset which goes from the output of the controller so normally this counter is kept reset by the controller and we can use an enable for the counter also since we have not kind of learned how to bring in enable and all that I just keep a very simple scheme that is kept reset and when the controller need this reset is removed that reset is made 0 then it starts counting and this is a decoder equal to time when you say equal to some fixed value it is a decoder and equal to a variable it is a comparator. So when you see equal to some numerical value do not think that it is a comparator because you know the comparator is an exclusive over gate comparing but when you say equal to 3 equal to 10 it is nothing but like if you say 4 lines are here say equal to 10 means that it is decoding 1010 pattern. So you can imagine that 1 then there is an inverter then 1 inverter going to an AND gate that output is going to the controller. So the idea is that the controller gives the start of conversion it is waiting for end of conversion when it comes it does 2 things it makes this fiftorite low the counter reset is made low it was 1 it was kept reset and the counter starts counting and when it reaches that this particular kind of pattern and that pattern is chosen so that it matches the fiftorite width and this gives a signal to the controller this goes high this was 0 and then it terminates this fiftorite and wait for the start again. So that is the basic business so we added a subsystem now so what next step we have to do is that we have to kind of update the timing diagram ok that is very important all these are kind of most people kind of hate this kind of very systematic approach they think that is very pedantic to draw but if you do not draw you can make mistake and in a complex design where multiple teams are working on kind of on a project then if small things can make a difference you integrate everything then you find some silly mistakes cropping up many times in complex design the verification is done by somebody else and it goes to full cycle it goes to the verification then come back with a minor correction and lot of time is wasted if you do not plan things properly. So anything complex you plan it properly take time to plan take time to go systematically then there is less kind of debugging less kind of errors cropping up but only thing is that you may not see many things concrete other than the paperwork like till towards the end of the end part of the project which can keep some people tensed up in jithri but one need not worry anything complex the most activity will happen when towards the end of the project then once you do everything plan properly bring things together towards the end it becomes very quick neat and easy integrating than you know kind of going through eternal cycles of debug and iteration and things like that not that you do not have to debug but then if you plan properly there will be less trouble waiting for you at the end. So let us move on let us see the updated timing diagram so this is the let us turn to the slide so everything remains same you have when the start comes the start of conversion is given by the controller wait for end of conversion and essentially this is the conversion time from the start of conversion to end of conversion and then the controller does two things the FIFO write is made low and the reset is made low and the counter starts counting and the controller wait for this write time signal okay the write with time signal when it goes from the decoder the reset is put back so that the counter is reset and inactive and the FIFO write is made inactive by making it one then again check for the start and if it start is one start the start of conversion and whole thing repeats okay. So we have come to a kind of good point to derive the control algorithm and looking at this waveform you can derive the control algorithm it is very easy now let us derive the control algorithm by looking at the timing diagram. So like let the state machine come to a starting state okay and all the signal all the output signals are inactive SOC is 0 this is an input signal FIFO write is 1 reset is 1 and this these two signals are the input to the sorry output of the like sorry input to the state machine so which is what is looked for transition. So and even the start end of conversion and this write time is input SOC FIFO write and the C counter reset is or the outputs may be I could have put different color but then anyway you understand that now so we are in a starting state with this inactive condition SOC FIFO write and counter reset is inactive and at the start state we are waiting for the start signal so that means the start signal is low remain in the state the same state the starting state and if the start signal is 1 transit to the next state upon the clock period clock active clock edge transit to the next state and make SOC 1 okay. Now we said we need a narrow pulse so way to generate is that next clock period transit to third state and make SOC 0 so you get out of the controller you get a pulse SOC 1 clock period duration pulse as SOC pulse then the ADC start you know converting then the state machine is in the third state where the SOC was made 0 at the same state it wait for the end of conversion to become high that means remain there like a wait and go remain there as long as end of conversion is low when the end of conversion comes high go to another state okay and make this FIFO write low and the counter reset low. Now the counter starts counting so at this state what you can do is that it remains as long as this signal is low so it is waiting for right time signal to go high so if it is low remain there and when it comes high go to the next state and make it 1 and FIFO write is 1. But you know that that next state can be the starting state itself because if you look at in this state the start of conversion is 0 FIFO write is kind of 1 reset is 1 so which is equivalent which is same as starting state so we can go back to the starting state. So that is the control algorithm so looking at the waveform one can derive the control algorithm you can write it in words once again starting state make the output inactive wait for the start signal when the start signal come transit to a new state make the SOC 1 transit to another state make SOC 0 wait for end of conversion when the end of conversion comes transit to another state make the FIFO write low the counter reset low wait for the you know right time when it comes high go to the starting state and the whole thing is repeated. So that is the control algorithm you can write it down upon reset come to an init state wait for start initialize output inactive upon the start go to next state make SOC 1 then do not wait for anything transit to next state make SOC 0 so that SOC 0 here 1 here 0 here so you get 1 clock period pulse here and wait for end of conversion to become 1 and then upon end of conversion transit to next state start the counter make it 0 make FIFO write active and wait for this right time signal to go 1 when it becomes 1 go to the starting state. So very simple very clear and you might wonder that in a complex case writing this is it worth I would say writing is worth because many a times writing allows you to think as you write as you draw waveform you tend to ask questions some questions come to my come to the mind and you will be able to address that but if you most people what they do is that either they do not draw the waveform and start writing the code ok from the head and that is prone to mistake but anything you write it down the mind works if you are thinking and the logical something logical is missing it comes to the mind and then it can kind of you can sort it out ok even sometime discussing telling the same thing whatever is known to another person sometime the process of telling brings these question to the mind or sometime inner question from the whoever is listening maybe they have not understood things properly but a doubt a clarification can trigger some answers to your mind. So it is very important that you work on the paper discuss sometimes speak aloud so that these things come to the mind ok of course this is not my kind of topic it is something to do with the cognition but then that is related to education that is why I am pointing it out because people shy away from these kind of simple steps and waste lot of time and it is very costly many a times whatever maybe you have a public limited company kind of designing a chip but that is the money of the shareholders and if you make a mistake if you do not meet the deadline lot of money is wasted it is do not think that it is your company's money your money it is the people's money so that you have to be responsible as an engineer many a times you do not feel responsible sometime a doctor is treating a patient and one thing that is the doctor is a medical doctor is a kind of more as more responsibility than an engineer. But I think engineers should you know kind of understand that we are responsible for the problem we are solving how efficiently we are solving how cost effectively we are solving very rarely that in a system which is designed by an engineer fails in the field and the engineer is you know kind of drawn to litigation many a times it does not happen but it happens in the medical profession so one has to keep this as a work ethic to kind of address these issues. So let us move to the state diagram now to implement the control algorithm we have implemented like we have written down so let us look at the whatever we have discussed how to draw the state diagram. So let us move on to the slide so see at the power on you come to a starting state okay S0 then at that state we make the signals inactive this is the starting state signals are inactive SOC is 0, fufo right is 1, counter is reset 1 okay so that is the output of that state more outputs and then here we are waiting for the start signal. If start signal is low remain there if start signal is 1 go to next state we know that we have to make SOC 1 rest all is remain same SOC is made 1 now we transit to next state because we want a pulse on SOC and SOC is made 0 rest all things are same and here the ADC is converting start converting so we wait for the end of conversion. So if end of conversion is low we remain there upon the end of conversion we go to the next state and what we have to do is that we have to give the fufo right signal we have to start the counter and that is what we do fufo right signal is active the counter is active the counter is counting so we are waiting for the decoder output to come. So the right time is low then remain there right time is high go back because then everything is remain same and wait for the start signal okay. So you should like symbol come to start you know starting state make SOC 0 wait for start signal to become active when it becomes active come to next state make SOC 1 go to next state SOC 0 wait for end of conversion when it comes start the counter fufo right is active wait for the decoder output and when it comes come to the starting state and you know repeat if the start is low. So one thing is that you see we are kind of looking at the start signal only at this state. So it is a very good thing you know it is the logic becomes simple because if you are looking at the start signal every state the next state logic will become complex but it has a beautiful advantage saying that we start at the whole you know start of conversion process even if the start goes low in between we do not care whatever was started is completed. So sometime making keeping things simple will result in very elegant solution like that is evident in the timing diagram like here since we are only looking at the start at the beginning even if it goes in between we are not stopping anything we are completing it and then stopping the whole game okay. So keeping simplicity sometime can result in really elegant solution which sometime people will boast saying that even if halfway the start is become inactive our system make sure that it is completed and solved. But we know that it is a very simple decision which has resulted in some elegance and here then we have 4 states so we have we can do binary encoding we number of flip flops are 2 then we can do the state assignment because to develop the next state table and output table we need to know what kind of flip flops we are using for the transition and how many flip flops and so on. So what is the states of the flip flop so we will assign S0, 0, 0, S1, 0, 1, S2, 1, 0, S3, 1, 1 and we will use D flip flop you know that if you use a JK flip flop we can use that maybe we can see that later but we assume the D flip flops are used so that the transition is same as whatever you want to transit same thing you give it to the D then you get the proper transition. So now we are able to write the next state table and the output table from the state diagram I hope the state diagram you remember so we move on. So do not forget this is the finite state machine you have 2 flip flops here giving the present state and the input comes and depending on the input and present state we are you know from the state diagram we are deciding this and in each state we are using output logic you know creating output by output logic in our case it is all are more output so there is no kind of this line is not necessary. So let us develop the next state table so next state table you have a present state as input the real input as inputs ok to the next state table. So we write the next state as a function of the present state and input so at the beginning 0, 0 if start is 0 these are do not care remain there if start is 1 go to the next state 0, 1 in the 0, 1 respective of the condition transit to third state 1, 0 and in 1, 0 we are waiting for end of conversion as long as it is low remain there 1, 0 if it is 1 you know 1, 0 is transiting to 1, 1 and in the 1, 1 state we are waiting for the right time decoder and if it is kind of 0 remain there it is 1 go to the starting state. So that is a symbol and we can form the min terms of D1 and D0 minimize it get the equation. So D1 and D2 are the function of the present state and the inputs the design is done and similarly the output table we can develop you have the present state output 3 output and in the first state the SOC 0, Resta 1 the next state SOC is 1, Resta 1 in the third state we make SOC 0 and then the end of conversion start of conversion has happened and in the last state we are making the reset and the Pfeforite active that is all and the output can be you know the equations can be form minimized and so on. So here the outputs are function of the present state that is what is shown. So the whole process of designing have shown so let us recapture that the whole process in steps so that you know clearly what is happening. So the design methodology we have used we have started with the specification which was written like a set of spec then we drew a block schematic of the block diagram and signal and we kind of argued for some block like temporary storage what is the temporary storage and so on. So basically there is a data path which is the Pfefo and the controller so in a complex design the data path is quite can be complex and then third step was that we have drawn a system timing diagram. Then some question cropped up whether how to meet some timing diagram so we have timing requirement and we need to put a counter so we had some subsystem to meet the timing then we have updated the timing diagram okay. Then we have described of course we have to do the data path design we have assumed the Pfefo design is done okay we have not attacked that but ultimately have to design the Pfefo too in this case or use a Pfefo as a block from somewhere or you have to literally design the Pfefo. So data path has to be designed and in a complex case we have to go through a hierarchy top down design then we have developed the controller algorithm from the timing diagram then we you know kind of the draw drew the state diagram and after that we have optimised okay in our case we did not do much of an optimisation but there was an optimisation like if you remember from the last state we said we could go to another state and make things inactive then we realised that instead of going to a fifth state you can go back to the in each state because those are equivalent okay. So in a complex case this may not be obvious you have a lot of states and there could be some states somewhere in the state diagram which are kind of equivalent and that can be brought together okay. So that is state diagram optimisation you can remove the redundancies and we will see how these are done by the tools but what are the kind of algorithm to use to detect the redundancy and so on. So there is a step in state diagram optimisation then we have to do the state assignment after optimising it you have to assign the state assignment we have to do the selection of flip flops what type of flip flops are used then we have to develop the next state table depending on the flip flops form the equation minimise it output table equation minimise then ultimately we have to choose some device technology and implement it so implement it then things won't go work at the beginning you have to debug it if something you feel that something is working at the beginning there is something wrong with you wrong with the whole thing something has to go wrong okay it is better things go wrong because at least in the learning process you can debug and learn things it is not that you need not plan but then it is better you know something goes wrong so that you can learn things well and ultimately you have to document it this is what you know I don't know why I am talking about documentation but then be it in academia or industry one need to document everything properly so that the people who are coming afterwards can follow it through so these are the steps which is now you realise that some of these things are done by the tools okay so let us look at it if you look at it all these things has to be done by the designer this is where the maximum creativity is required you know you have to come out with an architecture data path then identify subsystem draw the timing diagram come out with the data path design come out with the control algorithm draw the state diagram then you can describe that in hardware description language all these can be done by the tool say up to here the tool can do it and you need to give some directive to the tool and test and debug you can use some equipments to do the test and debug and documentation maybe the tool can help you with some report for documentation so steps 1 to 8 is done by the designer 9 to 13 is done you know done by the tool and the directives and the next steps is done by some tools or equipments and the designer. So I have taken you through a whole you know case study starting with a specification we have seen how to automate offload the processor by a design a data acquisition system basically we have described the system came out with the block diagram the ADC the host controller and the temporary storage we have chosen FIFO and then we have interconnected that then we have put the timing diagram then we have identified the subsystem updated the timing diagram and we have derived a control algorithm drawn the state diagram and we have developed the next state table and output table you wrote down the whole process all the steps in the design process the initial part up to the state diagram data path design and the controller design is done by the designer where the maximum creativity that is where you have to spend time then you should know the tools you know to know it well and we will learn about the tools and then proceed test and debug and document it. So we have been learning how to design the data path and the controller there are lot of timing issues various issues in the controller to discuss and the data path design. But for the time being I will stop the digital design part and we will in the next lecture onwards we will have the basics of the VHDL so that you are able to describe the combinational circuit and sequential circuit of some complexity using the hardware description language then we will come back to this issue so that the design and the VHDL can go hand in hand. So next quite a few lectures we will go through the VHDL part so please revise whatever I have done till now for whatever reason I am sure that you will be you know seeing this video course but there is no point if you mechanically go through the lecture after the lecture like leisurely without working yourself. So please revise work yourself learn it well so that at the end of when once you go through the complete course you are a master in the subject. So I wish you all the best and thank you.