 Hello and welcome to this presentation of the STM32H7 System Overview. This block diagram summarizes the key features of the new STM32H745 single core line, which integrates the Cortex-M7 core with single and double precision floating point units running up to 480 MHz, with 32 kilobytes of cache, up to 2 megabytes of dual bank flash memory with ECC and read while write capability, 1 megabyte of SRAM with scattered architecture, 192 kilobytes of TCM or tightly coupled memory RAM, including 64 kilobytes of ITCM or instruction TCM RAM and 128 kilobytes of DTCM or data TCM RAM for time critical routines and data, 512 kilobytes, 288 kilobytes and 64 kilobytes of user SRAM and 4 kilobytes of SRAM in the backup domain to keep data in the lowest power modes. This line also includes up to 35 communication peripherals in addition to the new LCD TFT controller interface with dual layer support taking advantage of the chromart accelerator. This graphics accelerator creates content twice as fast as the core alone. The STM32H7X3 single core line also embeds 11 enhanced analog functions including low power 14-bit ADCs running at up to 2 mega samples per second, 12-bit DACs and op-amps as well as 22 timers, which include a high resolution timer running at 480 MHz. The STM32H7X3 single core line is pin-to-pin compatible with the STM32F7 series for common packages and compatible with most of the common packages of the STM32F4 series. In addition to the single core line, the STM32H7 series offers two new dual core lines, STM32H745 and STM32H747 which are based on high performance ARM Cortex-M7 and Cortex-M4 32-bit risk cores. Running at up to 240 MHz, the ARM Cortex-M4 processor features a dedicated hardware adaptive real-time accelerator or ART accelerator allowing zero weight state code execution from flash memory. STM32H743 and STM32H747 devices operate in the minus 42 plus 85 degrees Celsius temperature range and STM32H745 devices can operate in the minus 42 plus 125 degrees Celsius extended temperature range. All lines operate from a 1.62 to 3.6 volt power supply. The STM32H7 series features a total of 1 megabyte of RAM, 192 kilobytes of TCM RAM including 64 kilobytes of ITCM RAM and 128 kilobytes of DTCM RAM for time critical routines, 864 kilobytes of user SRAM and 4 kilobytes of SRAM in the backup domain. The flash memory interface manages the CPU AXI accesses to the flash memory. It implements the erase and program flash memory operations and the read and write protection mechanisms. The flash memory is organized as follows. Two main memory blocks divided into sectors and an information block containing the system memory location from which the device boots in system memory boot mode and the option bytes to configure read and write protection, BOR level, watchdog software hardware and reset when the device is in standby or stop mode. The embedded system SRAM is divided into up to 5 blocks. AXI or Advanced Extensible Interface SRAM D1 domain is mapped at address 0x2400000 and accessible by all system masters except BDMA through D1 domain AXI bus matrix. AHB, AMBA high performance bus SRAM D2 domain is split into 3 areas accessible by all the system masters, accessible by all the system masters except BDMA through the D2 domains AHB matrix. AHB SRAM 1 mapped at address 0x300000. AHB SRAM 2 mapped at address 0x300000. AHB SRAM 3 mapped at address 0x300400. AHB SRAM D3 domain with AHB SRAM mapped at address 0x3800000 and accessible by most of the system masters through the D3 domains AHB matrix. The system AHB SRAM can be accessed as bytes, half words or 16 bit units or words or 32 bit units while the system AXI SRAM can be accessed as bytes, half words, words or double words or 64 bit units. These memories can be addressed at maximum system clock frequency without wait state. The AHB SRAMs of the D2 domain are also alias to maintain the Cortex-M4 Harvard architecture. AHB SRAM 1 also mapped at address 0x100000 and accessible by all the system masters through the D2 domains AHB matrix. AHB SRAM 2 also mapped at address 0x100000 and accessible by all the system masters through the D2 domains AHB matrix. AHB SRAM 3 also mapped at address 0x100400 and accessible by all the system masters through the D2 domains AHB matrix. The TCM or tightly coupled memory SRAMs are dedicated to the Cortex-M7 CPU. DTCM RAM on the TCM interface is mapped at the address 0x200000000. ITCM RAM on the TCM interface is mapped at the address 0x200000. ITCM RAM on the TCM interface is mapped at the address 0x0000000. ITCM RAM and DTCM RAM are accessible by the Cortex-M7 CPU and by the MDMA or master direct memory access through the AHB slave bus of the Cortex-M7 CPU. At startup, the boot memory space is selected by the boot pin and boot add-ex option bytes, allowing programming of any boot memory address from 0x0000000 to 0x3FFFF, which includes all flash memory address space, all RAM address space, ITCM, DTCM, RAMs and SRAMs, and the system memory boot loader. The values on the boot pin are latched on the fourth rising edge of sysclock after reset release. It is up to the user to set the boot pin after reset. If the programmed boot memory address is out of the memory mapped area or in a reserved area, the default boot fetch address is programmed as follows. Cortex-M7 boot address 0, flash memory at 0x0000000. Cortex-M7 boot address 1, system boot loader at 0x1FF00000. Cortex-M4 boot address 0, flash memory at 0x08100000. And Cortex-M4 boot address 1, SRAM 1 at 0x1000000. When flash level 2 protection is enabled, only boots from the flash memory or system boot loader will be available. If the already programmed boot address in the BCM7 adds 0, BCM7 adds 1, BCM4 adds 0, or BCM4 adds 1, option bytes is out of the memory range or RAM address, the default fetch will be forced from the flash memory at address 0x0800000 for the Cortex-M7 core and the flash memory at address 0x0810000 for the Cortex-M4 core. In the STM32H7X5 or X7 lines, the two cores can boot individually or at the same time according to the option bytes as shown in this table. This allows implementation of safe booting and ensures proper initialization on power up. The enabled CPU is defined as the master. It is responsible for system initialization. The other CPU performs specific initialization operations.