 Greetings, risk five friends and subscribers to my channel. So I posted the video of this Kaikad schematic put together and I got a couple of feedback items from commenters who are vastly appreciated by me. So let's go right into some of the corrections that I need to make. So the first one is down here over by shift right. This bit was supposed to be 30 and not 20 a couple of commenters pointed that out. I honestly I probably would have caught that when I made the PCB because I definitely would have noticed that this signal does not go between 31 and 29, but it's a good thing that we catch it early. So there's that. Let's see another error that some commenters made is this and what I did here was I connected the enable to the input shift output enable signal and I totally forgot my own advice that inputs to gates should always have a defined logic level and unfortunately if you disable this buffer well none of these signals have a defined logic level. So I'm just going to change that by grounding this and that means that this buffer is always going to be enabled, which is great. Unfortunately I made exactly the same mistake on the ALU which is unfortunate because the printed circuit boards were just made and sent back to me. They're on the ship from China or actually on the plane since I'm using DHL. But anyway hopefully I can just maybe lift up those pins and then put a couple of bodge wires in there. So that should fix that issue. If we're simply not doing a shift operation then it's entirely possible for none of these buffers to be active and that means that none of these output signals have a defined logic level, which means that none of these signals are going to have a defined logic level. Now one way I can solve this problem where the inputs or rather the outputs, one of these output buses has no defined logic state is to make sure that one of these pairs shift left, no shift or shift right is always active at any time regardless of whether the shifter is supposed to be active or not because really we just want to make sure that the very final stage doesn't output anything, in other words it tri-states that destination bus. So there is a simple way that we can fix this. So here is the key. We know that these signals are always going to have defined logic conditions. We do need to make sure though that that's the case because for example for instructions which have no source register we will need to make sure that we have no source register or have no second source. We need to make sure that this is going to be set to something like zero. This buffer is always active so that means that these control lines always have defined logic levels. So the only thing that really is preventing these buffers from becoming active is the shift right and shift left signals. You can see that we've gated those signals with the shift output enable signal. In other words this line could be one and also this line could be one. And if that's the case then shift right is not going to be active and shift left is not going to be active and if these lines are in a particular condition then that means that no shift is also not going to be active and that leads to an illegal bus condition where one of these internal buses is just tri-stated. So what we're going to do is simply not gate this. We're going to remove these completely and we are simply going to connect this to there. And now we can just remove these. And in addition we're going to take the shift left and we're going to wire that up to this and now we can just call this shift left because that's what it is now. And we don't need any of that crap. So in this way shift left is connected to what? It's actually going to be connected to the 30th bit of the, no actually shift left, what is shift left connected to? Well it's connected to F2. F2 again is always going to have some defined logic state which means that shift left is going to be defined which means that shift right and shift left are complementary of each other. So either we're going to shift right or we're going to shift left and the way of course that we disable shift left or shift right is with the RS2 sub 0 or RS2 sub 1 or whatever. So in other words if RS2 sub 0 is active, in other words is a 1, that means we are always going to either shift right or shift left if the shifter is not enabled. And if RS2 sub 0 happens to be 0, well then we're just going to do a no shift operation. It doesn't actually matter what we do as long as only one of these pairs of buffers is active at any one time. And again it doesn't matter what we do as long as we disable these output buffers at the right time. So here we have this shift output enable. Okay, here's a problem though. Yeah, this is definitely a problem because now let's suppose the default condition is going to be shift left just for argument's sake. Well that means that unfortunately these buffers are going to be activated. So that's really not very good. So we definitely do have a problem here. What I could do is I could simply take RS2 sub 4 and combine it with shift output enable. So I'm going to do that, I'm going to do that offline because I just need to do a little bit of thinking about exactly which gate I need. I think it's just going to end up being an OR gate. So I'm going to need one OR gate that ORs RS2 sub 4 with this output enable, shift output enable and that will basically be the final output enable for this. And unfortunately because I feed RS2 sub 4 the not signal to shift left and the RS2 sub 4 to the other shift, which is no shift, I need to be sure that that's going to work as well. So anyway, that is my solution to the invalid bus state problem. Another issue, these are actually not supposed to be not connected. So I'm just going to remove these Xs right away and I'm going to define these signals. So I'll define those signals later on and let's see, okay, an objection was raised. So this AND gate, first of all, I can change its value to an LBC. So an objection was raised that this AND gate, the output goes to something like 32 inputs. And the question is, well, can the fan out of this AND gate take B32 or higher? The answer is actually yes. So we're not dealing with TTL, you know, which is where that comment may have been triggered from because I had this as an LS. This is all CMOS. So with CMOS, first of all, in terms of static DC characteristics, the output of this AND gate here, I actually have the datasheet that we can look at. So here is the 74 LVCO8. And if we look at the output current, we can see that it's plus or minus 50 milliamps. So that's the capability. If we look at the input, do we have an input leakage current? We do. So, you know, we're down in the microamp region. That's what input leakage current basically means. Nominally, there is no current. You can see that here. It's basically plus or minus 100 nanoamps. But in fact, there is some leakage current. So the input characteristics of LVC are such that the DC fan out doesn't actually matter. We can also take a look at the AC characteristics. Now for this, I have to go to the Texas Instruments guide to low voltage logic. And what we're looking for is the load capacitance. Now if I pull up the datasheet for the 541, and we look at the input capacitance per line, it's 5 picofarads. Now if we're going to be driving something like 30 inputs, that's a total of 150 picofarads, and 32 would be 160. So now this graph is specifically for the 74 LVC 16245, which is a 16-bit buffer. And we're looking at VCC is about three volts. And let's just assume that it's all 16 outputs switching. That's like the absolute worst case. Now if we look at 160 picofarads, that's right around 6 nanoseconds. So the propagation delay of that AND gate is going to be 6 nanoseconds. Obviously if we get the load capacitance down to 50, which is an equivalent of 10 inputs, we could go sub 4 nanoseconds. So do I really want to save those two nanoseconds? If again we look at the datasheet for the 541, we can see that the propagation delay for VCC between 3 and 3.6 is something like 3 nanoseconds. So we would be saving a little less than one gate's worth of propagation delay. It could be worth it, in which case I would have to split this AND gate up. Since I'm only using one AND gate out of this, I could just duplicate this and duplicate the inputs, and then route the outputs to just a few, like 8 outputs. That would certainly get the propagation delay down. I might end up doing that. I might not. Again, I'm just not sure whether I will or not considering that the overall propagation delay of this thing. So if we have 5 stages of buffers, that's already 5 times 3, which is 15 nanoseconds. Plus we've got this additional buffer is probably going to be an additional 3 nanoseconds. We're up to 18, plus these gates. So we're probably at 20 or 25 already. And shaving off 2 nanoseconds, which is just a 10% difference, is just on the edge of significance. So I'm not sure it's worth the extra work. Let's see. Were there any other comments? I think that was about it. So one interesting thing is we can look at that designer's guide. It's got a lot of interesting things in it. So this is the LVC designer's guide from Texas Instruments. And let's just skip right to some of the interesting graphs. OK, so these are the voltage levels of 3.3 volt logic versus 5 volt TTL. You can see that the voltage output and input thresholds are identical, which means that you can take a 3.3 volt chip and drive a 5 volt chip with it. The thing that you can't do is take a 5 volt chip and drive a 3 volt chip with it, because even though the output thresholds are the same, this 5 volts output could go all the way up to, well, 5 volts. Especially if you're feeding an LVC, which has no effectively infinite input resistance, the output is going to be very close to 5 volts. And that means that you're going to overdrive the 3.3 volt chip. So that's not good. That's case one in this diagram. And interestingly they say that there is a special thing called a CBTD device, which incorporates a diode to create a 0.7 volt drop, and then a crossbar technology switch, which provides an additional drop of 1 volt, which takes your 5 volts and drops it down to 3.3. So that's kind of interesting. AC performance, so we've got just some propagation delay things, and you can see that as you increase the voltage, you decrease the propagation delay, simply because you're driving the transistors harder. Let's see. This we already looked at, this is actually very important because we want to know what the load, what the propagation delay does in terms of the number of outputs, the number of inputs that you're feeding. Power considerations, I don't really care about power, to be honest. This, what is this show? There's some hysteresis in here, 100 millivolts. So it's kind of sort of a Schmidt trigger, kind of you get that automatically. You can see this protective diode over here, that's why you never want to drive the input of these chips below ground. And you can see by the current that once you exceed something like 0.5 volts or so, which would be the forward voltage of that diode, the current rapidly climbs, and then of course you burn the chip. So that's not great. Input current loading, look at this, it's like in the Pico amp range. So yeah, you don't have to worry about your DC characteristics. But in fact, you know, there's, and this is leakage current. So that's interesting. My current change, so I think that means that if you're switching, there's a maximum of 500 microamps additional on the power line. This is an interesting circuit, we've discussed this before, it's called bus hold. So the idea is that when you drive an IO pin of a buffer with a logic level, and then you release that line so it becomes tristated, this circuit over here effectively keeps that logic level. So that means that the input always has a well-defined logic level. The only problem, I don't really like this feature because it requires actually a lot of current in order to flip the state of this bus hold input cell. You can see that you require something like, let's see, something like 200 microamps on each input. So you know, then if you're going to multiply by something like 30, you're already in the six milliamp range, which could be significant, you know, considering that that's about a quarter of an output, a typical output of like 24 milliamps. So I don't necessarily like the bus hold feature, but on the other hand, if I need to define the states of these inputs even when the shifter is not activated, then I may very well have to do that in the next revision. So here are just some output characteristics, not very interesting. Here we're talking about termination. And interestingly, they say that as a general rule, if the trace length is less than four inches, no additional components are necessary to achieve proper termination. So I do have termination on my backplane. I don't have any termination inside each card. And I think that's going to be sufficient. We have some signal integrity and stuff, just more stuff. Again, I don't think that the rest of this is very important. This is just marketing stuff, you know, basically are saying, oh, TI, we have better chips. And there's another interesting marketing. Yeah, this is some more marketing comparing Texas instruments to Fairchild to IDT. And if we go down to, I think it's really close to the very end. Oh, this is interesting propagation delay skew. So if you've got all the inputs changing simultaneously, what's the spread on the outputs? And you can see that TI claims that their skew in one direction is 150 picoseconds. And in another, it's very close to 150 picoseconds. That's for an 8-bit buffer. And for a 16-bit buffer, of course, the spread is a little higher. Yeah, and this is output-to-output skew. Yeah, output-to-output skew, then what was I looking at? Propagation delay skew, right. Okay, so the propagation delays are very close to each other. You know, for a three nanosecond propagation delay, 150 picoseconds, difference is actually pretty good. This is the output skew where if you change all the inputs simultaneously, what's the spread on the outputs? And, you know, it's something close to 200 picoseconds. Yeah, okay, so, and here's the conclusion. So basically, they have this table of TI versus Fairchild, Motorola, and IDT. And they have all of these measurements. And they say a plus sign indicates a desirable characteristic. A zero is average and a negative sign is unfavorable. You honestly think that they would have a measurement where TI shows up as unfavorable. There is an additional modification that I need to make to this circuit. It's just a minor one. If we take a look at the Texas Instruments data sheet for the LVC 541, we see this note that says to ensure the high impedance state during power up or power down, the output enable should be tied to VCC through a pull-up resistor. And the minimum value of the resistor is determined by the current sinking capability of the driver. So that means that we have this buffer over here. Now, of course, we don't actually need to put a resistor and tie it to a particular power rail because this is already powered. This is already set to a power rail. But these all have logic signals that do need to be tied to one of the power rails during power up. So that means that, for example, RS2 sub zero here would need to have a resistor connected to plus 5 in order to turn off this buffer to ensure that the buffer is turned off during power up. So that's another thing that I'm going to have to do. Basically, I'm just going to take a resistor here in just a second. So basically, I'm going to take a resistor and I'm going to do something like this. And then I'm going to grab VCC and do something like this. And now the question is, what is the value of this resistor? And basically, it says, well, it depends on how much current this thing can drive. Well, what happens if I just say 10k? Well, first of all, this would have to be capable of sinking. What is this 3.3 volts? So this would have to be something like 330 microamps, which of course it can do. So that's fine. And this basically takes nothing. So I think a 10k value would be just fine. So I will have to do that for all of these input lines to make sure that during power up, they have a well-defined state. I think that's really what it comes down to. So that's another modification. So I've got that ORGATE modification and these resistor modifications. And I think that should be about the end of the modifications. That's pretty much all I wanted to talk about. So this was just a little feedback video. Again, thank you very much to all the commenters. I really appreciate it. And I will see you on the next video. Bye.