 Yesterday we were looking for isolation and the last we did was the trench oxide isolations and we have now an active area which is separated by deep trench which is filled up with oxide. Now we did this last time, now I will start with today, if we are not doing trench oxide and we are doing a normal low cost process then there is another process step is kneaded which is called channel stopper. This may not be kneaded in STI but this is normally kneaded in the normal isolation oxide we grow, for example what is kneaded is this step is same as earlier we have a silicon dioxide, nitride, resist and we implant now depending on whatever substrate we have in this case I implanted P plus in a substrate P. This black portion is a P plus implant and this resist will stop the implant elsewhere, wherever resist it will not go through, wherever clear regions are there the implant process will make the surface below P plus then of course we remove the resist and start driving along with anneal actually and we start oxidation along with driving is essentially in oxygen so this oxide will be grown and since the impurities will also be driven in so just below the oxide you will have a P plus layer as you start going impurities will also start going down and they will be always in touch with the oxide so you will have now a P plus layer between below every thick oxide or fox we have created and this is many times essentially in older technologies, the new technology of SIT probably does not need is as much but older one has to be used with this, the reason is obvious, if you have drawn I will just show you this formulation I will clear it why I am saying, repeat I am trying to create a P plus region below thick oxides, now we are not I do not know whether the design course has started layouts, hopefully something they might have shown, so in the layout of a circuit when we come for a mask something this formula will come back to it just see if you draw the figure I will just first explain and then we will come back to this numbers, so I repeat this process is necessary only if this kind of isolation is provided if you have STI then you do not need this implants, now why this word channel stopper and that is something I like to explain, to some extent this question was asked in the exam indirectly in the mid-sem, is it okay, this is standard once you know this you just get thick oxide, this we have done yesterday only thing is now a P plus region is below all foxes, all fox regions, why it is called fox, the larger area of the wafer is essentially a thicker oxide everywhere except the place where transistors are coming, therefore it is called field oxide, so let us quickly we will come back to this sheet again, what is happening of course I do not have colors but let us take this is your drain of the transistor and this is your source of the next transistor essentially I am saying when I make a transistor here there will be drain, source, drain, source and there will be oxide, there will be source drain, source drain, so between drain 1 and S2 there is a thick oxide, you can see this, this thick oxide is sitting between the drain of 1 to the source of 1 okay, so essentially this region is thick oxide everywhere and since metal has to run except the place where transistors are because it should not touch any source drain, it is called runner, if metal is running, interconnect is running, so it may run for example in between like this may go ahead also, this is metal, since below metal there is a thick oxide, below metal there is a thick oxide so it isolates itself from the transistor regions okay, however there is an issue here okay, the issue starts you have understood what I said, I have 2 transistors separated by thick oxide and in thick oxide wherever I have thick oxide I run the metal, so I run the metal on a thick oxide but it created some problems, if I have a metal line here okay and this was my source drains okay, then I figure out whenever metal receives highest voltage VDD the signal has the highest value then this is please remember this is oxide, this is substrate concentration, so this is metal oxide semiconductor okay, metal oxide semiconductor, so there is a capacitor formed there okay with thicker oxide, if this oxide quality is not good enough, the doping is not large enough then if you look at the expression for threshold it is 2 phi f plus phi ms minus kiosk by kiosk which is kiosk for this may be dash I should put for field oxide plus the doping of substrate okay, however if this 2 values are such that it does not become large enough positive value okay, how much large it should have at least cross VDD okay, the threshold of the, so this is called field transistor, this transistor is called field transistor which is built in nothing can be done on that, so the threshold of a field transistor is less than VDD which can happen depending on the oxide charges, depending on the doping you start with then the inversion below this will start the metal will invert the field oxide as well, so if they assuming right now there was no P plus this drain through a channel, field channel will connect to the source of the next transistor okay, so it is shorting the 2 channels okay, it is shorting the 2 channels and why it can happen if the VTF for this thick oxide is not large enough larger than the VDD then this process and typically VDD is not the only signal, what is the maximum signal one line receives if the power supply is VDD, I repeat, I have a signal going on a metal line 0 to 1 I shift, how much is the maximum voltage a line will see, it will actually see a transient depending on the inductance of the wire of this metal line, LDI by DT will be the large amount of voltage will create and 2 VDD is the possibility depending on of course Zeta as the we called and it can even sometimes if there is a capacity effect it can even boost further bootstraps, so the safest VTF is 3 times the VDD but the minimum you should try is twice the VDD is that correct, the minimum VTF voltage required for safe operation is 2 VDD, now if I want to increase VT, how do I do increase the VT in this function, Phi M S increase but it is log term, so it does not increase the value of Phi M S is 0.6, 0.65, 0.68 it will go at much as 0.04 volts maximum change, the only thing I can change is the bulk charges that the doping Q and AXD, okay. So if I have to increase any but I do not want the rest of the places that doping should go, I only want the field threshold be higher, so wherever field was there I put a P plus implant everywhere which will increase the field threshold of this so called parasitic transistor larger than 2 VDD, is that what clear? Yes, except for the transistor the field oxide is going to come everywhere, so wherever field oxide is going to come below that it should be higher way P plus, okay. You can see here there are 3 regions, all 3 regions there is a P plus, oxide is going to come here, here, here, wherever there is a field oxide below that there should be a channel stop and that is why I call channel stopper, what this channel stopper means? This channel does not get connected to this channel and it stops, okay because of this transistor does not turn on, okay. This is essentially is called channel stopper implant, this is as I say why I say in SIT we do not do so much because SIT is very deep relatively to the source drain, so it is unlikely that the channel will go all the way down and get it connected, okay not impossible but difficult. So one says SIT is a good isolation, you do not need channel stoppers as much as you need for normal this kind of isolation which was the old technique and everyone till 90 nanometer everyone using this only, okay. Below 90 only we went for SIT, so this how do I get the VTF extra? You know what are bulk charges, whatever is QNAXD plus whatever dose you are going to put through implant, anyway dose is per unit area, this charge is also per unit area, is that correct? Q into dose is QB dash or a Q implant, so I know this because I am fixing through implant how much I want, this of course without if I do not put it I said this is a VTF and if I put that it is a new VTF dash, the subtraction is without P plus and with P plus this is Q implant by COX, is that correct? And this is minus because it is a negative charge will come, so it is essentially plus value will appear, so this value is essentially the additional threshold which you want to add to the field transistor threshold which you would have got otherwise there is no channel stopper and this means the dose can be now decided by how much additional VTF you want from the earlier one to add that much dose implant here, so it will be 2 VTD if you want adjust VTF whatever initial was see that it increases to 2 VTF and that 2 VTD and actually find the dose, so implant dose is decided by the choice of VTF you make this, you want 3 VTD you may have to put higher implants, much more dose you need but at least 2 VTD should be safer, I repeat in circuits particular digital circuits the transients actually are more worrisome than the because DC we hardly care 1 and 0 if it is there who cares only when it makes transition the issue starts, so think of situation that in transition circuit should still be in the case of analog also there is a issue but may be some other day, may be next semester course if some of you take where I will teach make signal design then you see what is the why even there the analog part also has a transient issue particularly if I am doing A to D converters, okay so now I start so far we have done it, now I will follow whatever process steps given in the book and my acknowledgement to Jim for allowing me to copy without his knowledge, okay. Of course similar slides are available from MIT a course was normally given by Miss Judith Hoyt and Mrs Judith Hoyt she is also a professor all of them now work on nano sensors including Anand Chandrakas and others so these people have their old courses you can also go ahead access to their these are open courses so it is not no passwords, okay so I just because this is given in a book so I thought that I should inform that this is standard thing which is available in books itself or in the net itself. So the process step which we are going through now is called 16 mass CMOS process and of course this is a very old slide even in his book of 2009 he has given the same slide so I will change, okay. You can see from here this is one transistor shown here this is your starting material then this is your isolation B this is yellow is your isolations you can see here is also a deep trench oxide is there but this is not for isolation what is it? It is a DRAM it is a DRAM capacitor, okay trench then there is a well doping C green one we will do that now followed by channel surface preparation then we have channel doping and channel strains silicon germanium if you add and then you have gate stack and spacers that is the major process step please remember this someone should the other day were asking the spacer is not only for one reason actually spacer is a good thing and spacer is a bad thing so too much spacer thicknesses may worry you too much less as spacer may even worry is more than that so spacer decision no and spacer variations because on a wafer this is very difficult to maintain side walls so the major reliability issue in all the side walls is a spacer how do you create so there are normal processes may one step we do but now we need 4 steps to actually create accurate spacers okay maybe after this whole course last day I will show you what is the spacer technology which itself is a game now okay so then you may contacts by opening silicon and gate and of course as I said this is the DRAM capacitor this may be a resistor this is also there is something called ferroelectric ramps ferrams so there is also a finger kind of mass structure which is created for a ferrams okay and of course there is a thin oxide which is your gate which may be not necessarily silicon dioxide but can be silicon nitride or can be any other high K any other high K okay so this is this if you are really interested in technology some way there is a body which is ITRS as the word says international technology roadmap of semiconductor there is a huge body some 150 people work for it various companies academics and they predict what is the present what they actually first figure out where is the technology now for each kinds of devices DRAM for all kinds and then they predict for the next year so they decide these are the problems and how will they possibly get solved and next year what is expected okay that is called roadmap okay so this 2014 roadmap is already out so now you can go and look at what is 2014 people I have got through and what is expected in 2015 okay what are the bottlenecks even in 14 which they will solve probably if it does not happen next year they say okay we could also that is the present state and 2016 will have the last 15 copy but that keeps doing so this is of course as I say standard this ITRS net is the famous net web page for that go for it only thing give a year 2014 2000 otherwise it will show you 2006 5 any number any area so for every this you ask for slash 2014 2013 12 but 2012 to 14 is not very much changed 13 14 15 they expect now we do not know whether yes or no okay so this is what I want to make this is the ultimate water mass transistor I want to make one N channel device and one P channel device for a CMOS okay for the N mass I only need one of them and of course there is some cases we will make resistors to require poly resistor implants but right now I assume there are no resistors and capacitors are always their mass capacitor then there are junctions so I have a junction capacitor so I do not need additional processing for making capacitors but resistors I may have to okay and also if inductance then I will really be in trouble because I will use a huge area to create the coils okay so we start with yesterday okay this is again a final version of what is typical CMOS will look like this is only two metal layer process the current trend is 7 metals okay so this is metal 1 then there is a metal 2 then there will be isolation metal 3 metal 4 metal 5 metal 6 and metal 7 okay our ultimate M is metal 12 okay but I think I do not know whether we will reach there are the issues of thicknesses the problem is where should we kept VDD or where should your signal should run maximum how much capacitance between the metal layers okay so there are too many issues because if you increase R then whole your speed goes you are looking 6 gigahertz from the transistor and the interconnect is actually making it 2 gigahertz so what is the point in making transistor 6 gigahertz so there are issues so this process number of metal layers and their contacts the making the 1st layer transistor is called front end process and the 2nd onwards or even at least 3rd onwards whatever metal interconnects you create that is called back end process okay and back end process actually decides the circuit okay how is to be connected okay front end processes designs the transistors back ends are these are called interconnects so major research right now is in interconnect not so much in transistors of course in fact is not now known for long so there is not much change has happened from FinFET of 2010 to 2014 okay so this is not a FinFET this is a normal mass transistor there is a P channel device and there is an N channel device this is the gate oxide this is the inversion channel in between N and P where these are okay this please remember since I need one N channel device and one P channel device so I must cannot have same subset so I create a separate regions for each transistors so they are called wells so for a P channel device I should have a N subset so N well for a N channel device I need a P subset so there is a P well okay this is deeper area down at least okay that is called well well means deep enough compared to whatever you are doing at the surface compared to that at least 4 times it should be deeper okay this is essentially adjusting the capacitance and that decides the speed so all these games are related to speed all of us are now trying to see what parasitics we get which reduces my speed so all my effort in technology is to improve speed is that clear so why technology is varying or why everyone has to do something more is to see that the transistor speeds are not limited by interconnects or not limited by some other side parasitics okay so that is something very important. So this is as I say a typical okay this red ones let us say I want to connect metal 2 to metal 1 so you can see I have connected some red portion this is actually tungsten it is called tungsten stub okay tungsten at its own problems so it should be guarded by something so there is a crowd around tungsten stub okay you can see this bleach it can be titanium nitride we will see this process anyway these blacks are metals so metal 1 is to be connected to metal 2 so in this oxide I must first create a hole as the word is via so I must create a via down and then fill it up because I want contact from the both bottom and this now the way it is shown here is not true because once normally wherever gate will appear that contact should not be there should not be any contact above it so it should be always displaced contact so you are here then you move up then you move up and that is why any other required because you will not put one over the other you will keep moving okay. So you can see from here there is a contact to the drain of this transistor this is the source this is also the drain of the P channel device this is P channel device what will this contact if it is a source where it will go in real life this is a P channel device this is N channel device this is the source and drain are identical in this particular process so let us say this is source this is drain of a P channel device this is source and this is drain of N channel device so where this will go and where this will go for a CMOS inverter this will go to VDD and this will go to ground and though I am not shown it but these two connections will be internal I do not need to separate I mean whenever I make this mask for metal I will have connection between two drains okay so I do not have to really connect taking it out okay so then there is a separation has to be done between this and this I want to make a contact please look at I made contact somewhere here this contact I did not push it here I went up open a window put a stop there and went up okay so there is some mask which is to be designed every now and then where and that is why it is called back end process which can be decided after transistor process is ready then we decide for a given circuit what should be back end interconnects okay why it is called back end because at the end of device we are now deciding how to interconnect and therefore it was called back end so back end engineers jobs are not very good they work too much on software like many tools are available cat tools but they are the ones who make money okay this is the source of each channel this is the drain of in channel or maybe source and this is the source this is the gate and one can take this contact up up this can get up this can get up on the surface all contacts can be made in your pads so we can create pad connections so this is the final device we want to make and we are already done so far what isolation we have done anything I had we have only made active areas where transistors are so whatever we have done it we are open these areas so far okay this is our isolation oxides Fox and as I said there may be a P plus below this N plus below this so now we are to need mass because for this P channel device what implant I should do N plus channel stopper should have N plus for N channel device I should have P plus so another mass what I am doing here I should not do here when I am doing here I should not do here so another mass so a channel stopper is not massless you need two mass to do that okay so there is also a catch in the whole system so that is why he has not shown it he is assuming this doping is sufficient to take care but it is not true okay this we are done so I will just repeat yesterday we started with oxide nitride photo resist first step yesterday this is I am just repeating what I have actually drawn and shown you yesterday this is 100 wafer okay silicon nitride was deposited as I say by LPCVD and I do not know how much he is talking of 80 nanometers but it is okay 800 Armstrong's I said I am still comfortable with Armstrong's than with Nano's so just 10 times that 80 nanometer is 800 Armstrong's this is low pressure CVD we will look into this this first oxide is thermally grown then we have a first mask and there was a pattern shown to you in which this was retained and the rest was a star okay once of course this oxide can be removed or can be held this was held because if I am doing channel stopper I need something oh I forgot that day I am sorry maybe quickly one minute I will come back to implants you just if you have drawn you have drawn yesterday something which I forgot in hurry but I think that is very important one thing you have to understand when I am doing an implant and there are number of atoms of silicon there is a possibility that if the ion which is you are passing like a boron which is smaller actually may not interact with anyone okay and just go and go till it somehow finds some dislocation or something where it hits okay this is called channeling is that correct this is called channeling so extra extra range is seen because atoms go in between like a corridor you know it just goes in no interactions okay now this channeling has an issue to if I put a very thin oxide here oxide has is not a crystalline material so what will happen the ions will hit and will when they come out they will not come into straight ones so they will actually get in different angles and therefore more probable to form a Gaussian profile is that clear to you is that why what why this oxide is retained because it de-channelizes the incoming ions is that curve this thin oxide that is de-channelizes the incoming ions where oxide is very thin so most energy it can pass through but crystal de-channel itself okay so this is why the word which I was a figure which I was showing you is that okay what is channeling it is a corridor of atoms periodic you said it is periodic if the gap is 1.62 and strong ion is smaller it can go straight so that such some ions may reach much deeper compared to the others okay so they may actually change the projected range okay so to do this normally thin oxides are retained okay someone asked can you know where I can age I can always age it okay when I was ageing all others I can age that as well okay when you someone also asked that when you age nitride the agent is same for oxide Hf is same for that so the way we do it we do ion ionic ageing or what we called as anisotropic age so I can what we call H stop as soon as oxide starts the H rate goes down okay energies are so adjusted only nitride is etched out okay so there are methods in which oxide can be in case there is no oxide before you will have the second masking you have to do you remove resist put oxide and put again resist so double masking but that is costly okay okay so we are now ready for active area then we did low cost as yesterday we said and then of course we stripped the nitride layer after making low cost and then we start the first process which yesterday after this low cost has been made you remove the resist this photo resist as well as you have removed the nitride so you are now a clean silicon surface okay with isolating islands okay these are active regions the rest is thick oxide everywhere now I use the first mask I have already shown you I need a P well create and channel device okay so I said fine I actually put a resist on this portion using this mask if I am using a PPR what mass I am using career fee I want to return this areas so light should not pass which means dark area this area should be dark on the mass the rest should be clear so this is a clear field mask with a window of dark window which will retain these areas okay so I retain it since this is a resist it is a excellent mask for any impurities so boron is implanted down and it will create a P implant below okay P implant below now the typical dose which is required is 10 to power 13 per centimeter square and the energy is 150 to 200 KV it will typically yield to a final concentration of 10 to power 17 P wells 10 to power 15 if you use NPR that should be clear window window should be clear and the rest should be dark with that decide the dose now this energy is also decided by the depth range you are looking for okay please remember where which one should have higher energy phosphorus or arsenic or boron N or P which has a larger range at same energy boron it will go deeper anyway okay whereas phosphorus so if I implant the same depth then what should I do the implant energy for arsenic or phosphorus will be always higher than boron so this they show you they do not tell but this is done is simply because equivalent value they find out so that same well thickness are available okay so first what is the first thing we did we created a area active area and in that we make a P well okay implant rather right now it is not a well it is only implant there yesterday of course we have seen this SIT STI sorry so this is given in a this I just printed but do not use that we have already seen that then we do a mask to make a n well area okay so what should I do there there is an interesting name we give the first mask was called P well mask the for creating n well we actually have a mass which is called P well minus mask okay P well minus mask so wherever I want implant earlier I do not want implant now and take oxide anyway will block everywhere so I am not worried about thick oxide area so I just take a copy of that is that clear and use the opposite resist she is asking is it okay I just take the opposite of that complimentary mask as they call and just use the other resist so I can open this okay or other same resist okay same resist if I use complimentary mask then I do not need resist to change all you change resist with the same mask also okay either way so now this area is open and this area is blocked now do arsenic or phosphorus implants normally phosphorus implants are done for well why they can go deeper arsenic is a shallow implanter or it has a low diffusivity so it will not go to deep DT products are much smaller so we must put deeper if you want put phosphorus okay so this is also similar dose okay typically 10 to power 13 and look now I just show you the phosphorus implant is done at 300 KV where was boron done 150 to 200 so it is roughly 2 and 2 times or one and a half times the earlier ones we do so that they come almost same depth so and then I start annealing in oxygen to some extent or at least annealing nitrogen for a long typical this if you want depending on what is the time taken and temperature chosen by what method what is the reason I am using some cycles XJ I want DT products so that I get so much XJ I have to Rp square plus 2 DT so I adjust my DT product so that XJ is what I want XJ is what I want okay so typical values are shown here which is around 2 to 3 micron of junctions but any value it can be lesser or larger depending on the technology node one is working at the current technology node may be a less than a micron 8000 Armstrong's but in 11 nanometers it will be even lower okay so we do not know what it is going to do so after p l and well I have been driven in by annealing what is the advantage of this it also anneals all damages activates all impurities and drives them in okay so this is a major step of creating p well and n well one and one go okay so here now a active areas in which you have area for p well area for n well where transistors are going to appear in the p well I will get n channel device and n well I will get p channel device okay now the next problem is we have been doing this often expression okay this expression can be read maybe I can rewrite this expression we also know for any transistor mass transistor v t for p channel device or n channel device is 5 s plus minus 2 5 f minus q ox by c ox minus plus minus q bulk upon c ox where c ox is epsilon ox by t ox where t ox is now gate oxide q v is q n b n d means either any or n d x d max x d max is under root of twice k s epsilon not 2 5 upon q n b so I know everything q ox is of course process dependent 5 s is also the metal which I use which I know anyway 5 s 2 5 f is 2 k t by q l n n a or n d by n i square sorry n i so I can evaluate the Fermi energy or Fermi potential I I know q ox I know c ox and depending on the doping I can decide my threshold okay so depending on this so normally I have a p well whose con how much doping I was telling that 10 to power 17 but this may not be required or this may be smaller or larger depending on node you are looking for v t requirements so I must now put something additionally in the channel area which is essentially required for given v t value is that work clear to you the n well p well doping are not good enough to control the threshold of n channel and p channel devices so I will now use another implant of exact doping of my choice both in p well as well as in n well which will decide my threshold this is called threshold adjust implant what is it called threshold adjust implant is that clear to you but why we still we are not go banking on the p well n wells because they are driven in their profiles are now very flat one so I cannot decide on the channel region how much is accurately uniform doping there so I actually want to know what is v t which is decided by whom by the technology you are told to design and we say this much current vgs minus 50 now you you I have designed all my circuit based on this current or so much gm now you suddenly say no no no vt is 10 percent different or 20 percent different than my whole circuit may perform or may not at all okay so my worries are that I must get correct vt of course still it will not be correct but closer to correctness nothing is absolute in the process everything is statistical okay so after the n wells or p wells are done I now go for threshold adjust implant let us say first I do it for n channel device so what area I should block all p well areas sorry all n well areas where p devices to come should be blocked and please remember this we always show you only this so the other portions are open it does not matter because there will be what there elsewhere thick oxide so it does not really matter if I mask it or I do not mask it is that clear but this window on us open because there is where implant is going to be performed is that clear the rest area is in a field oxide so implant does not go through what is that thickness we have to adjust for the highest energy implant how much is blocking you want maybe 8 lines or 10 9th okay so adjust your thickness of field oxide such that nothing goes through it in the below surface is that clear that is why we other show you how to calculate how much blocking it can give a layer can give okay okay so now I open a p well area and I want to adjust nothing will go below that that implant was done prior to oxidation did you get the point impurity is what you already put there cannot be changed now is that point clear below oxide whatever you have put there is nothing can come out now oh they are they are not in oxide the ions are not ions actually they will discharge through their bonding so they will be randomness in that and they will not contribute and they are away from the surface they will not contribute to VT fixed charges are only when it attacks silicon in the or it is a dangling bond these ions are much fewer than available silicon Si Si bond so in general nothing will pass through this and they will lose the charge and sit in the interstitial site not contributing to anything is that clear because that is an amorphous material silicon dioxide is not crystalline is that correct so there is nothing much will accept the fixed charges which occurs close to the interface they are not inside the interface okay mobile ions move because they are charging them and you are asking them to move otherwise ions will lose the charge as you put in the wafer at the end so they will sit somewhere without contributing to anything okay now I do a threshold adjust for you should protect the PMOS devices boron is okay now you must remember since it is a P well the implant is also P type why because it is an N channel device the threshold is adjusted by P type doping so I do a boron implant somewhere in the well okay somewhere in the well and essentially whatever is Q implant I do divided by C ox is typically the VT I can adjust at that point okay is that clear you are initially P well so I know what is VT with P well doping then I do implant and I know how much is additional VT I have got through which is my implant VT is that layers is called shift I am actually shifting the VT from the P well VT to channel VT so I adjust my VT of the channels okay so firstly I did it for what for a in a P well means I am doing N channel this so I did boron I use complementary mask or complementary resist the same mask either way okay you keep mask same mask then resist change complementary mask resist the same so I open this area and now what I implant arsenic this is very important because now I do not want deeper things to go so I want very shallow implants first actually this I did not tell you every process we go through there is a test wafers are there on every process okay so before we start the next process we actually measure the last process what has happened so I will have a mask capacitors up every time and I am junction device from every time resistors of every time every there is a test area on a mask I keep monitoring test areas before the and I do not use that again same test area in the I will use the fresh so out of says 8 times I want testing so it will be 8 test wafers only one at a time I will take and only that process I will measure and then I will not add to that and the next time use the second month is that clear to you so this testing is done every persistent so I know VT is how much was with the people I have a mask capacitor for that okay on my test so I will monitor that and I figured out and this is not one test area actually on a wafer each chip has at least five test areas and on a wafer you can say 10 by 10 area 20 by 20 so many test chips are available test chips are kept in the corners and the wafer top bottom this center so five so there are too many test areas available to you for testing okay even the final test when we do the whole circuit is available to me on the test like I use a flip flop many times so I will have each kind of flip flop available on the test area so I will actually monitor before circuit is tested because it is too costly to test full circuit so I will test every block so our process step keep adding test areas and if you are fresh something you add additional wafer to do some more test okay only one process step you want to add some more extra step extra process wafers some wafers are kept constant till end so that is why the number of test wafers could be 8 to 20 depends on how many times you want to test okay you can keep adding also additionally in between okay because now last step I have finished I now want fresh from here the next process what changes so I can only add one more wafer wafer with a test area okay so I keep adding test area keep test wafers and also I keep monitoring the combined ones and change ones so I know what has happened from the last step to now okay so this is always tested and only then but this is normally first done by a cat's tool I mean you are doing a supreme or centura's kind of thing and you know roughly what is going to happen okay but I do not trust that result I will actually test physically everything okay all sheet is you said you dove and so much resist I will monitor every area sheet resistances whichever I am creating okay you said hoping I say I will measure photo I will find whether how much was actual doping on there okay so there is a test areas on every chip and every wafer lot numbers and so many wafers are kept adding so testing is during processing is very crucial for success you just do not once do it and hope for the best nothing happens okay then nothing will happen nothing will happen no no circuit will be seen so this is very crucial in our whole process line that we keep monitoring what is happening okay and we keep comparing with what our centura's result and we say okay so I actually modify centura's result now if I monitored something many times and I found this is the value I am not getting so I will actually change the software there I mean values there and then the new values I will get from them and next process I will modify that it is a online modification can go of course once standardized hope for even then test is done that centura's is not used then they know this will work but standardization takes lot of time is that clear so process standardization is a game okay and but money is only and if your process is standardized okay then you have 1200 wafers which are all well okay so similar thing I did one for p-channel devices n-channel devices similarly I did for p-channel devices this is called threshold adjust implant please remember mask this and mask 5 are complementary mask or complementary resist whichever way same mass with different resist or say different mask with same resist you can use it either way okay so there are sometimes called minus mass p plus minus mass of p plus higher p minus care it is called complementary okay you can also see here in the case of Bolan how much was the energy 50 to 85 KV how much was for the arsenic 75 to 100 is that clear so this energy adjustment is for similar depths in both cases is that clear sir I want same both sides so energy I know energy is proportional to the depth range so please this take from me that this energies and and doses are adjusted to make equivalence of both devices many times okay so that they are I do not want vtn should be different from vtp okay there is no harm in actually having they different but if I am making a CMOS circuit I will not like the high and low values be different okay so I want transition should be similar for both p-channel and n-channel when it goes from higher charging and it when it discharged as I want same same process to happen so I will always see to it that vtn are same as vtps but as size I cannot do so I know that mu is double two and half times so I will actually sizing double the p-channel devices or two and half time just to maintain similarity of p device with n device is that clear so this equality of circuit equivalence is always used in technology because they want equal everything from p or n okay so so far we are done we are still to do a transistor we are still only on first implant creation then we okay then this thin oxide was removed because why we kept that thin oxide channeling de-channeling okay now remove that okay and then I grow it the most important process of whole mass transistors is creating a gate oxide of course instead of gate oxide it can be any high k or it could be nitride what is the advantage of nitride over silicon dioxide no no no no no no no no gate oxide my gate replace K. It has almost double that of silicon dioxide okay 7 so dielectric constant is double that of silicon are not 4 3.9 and 7 but roughly double whereas hi-k means really I am on 16 22 28 so So I may go for half neumoxide, zirconium oxide, I may go for lanthanum oxide, I can move gallium oxide, I may try many mixtures, tantalum oxide, I have many possibilities which I can try, okay. So I agree with thin oxide and on that immediately, okay, this of course is an optional step that I have shown you. What kind of oxide it should be? Good oxide is which oxide? Dry oxide, dry oxide is the best oxide, okay. But high k there is no dry oxide, so that is bad or good, whatever it comes, okay. But if you are doing SiO2 based, you always go for gate oxide with dry oxidation. Second reason, if as you take on this case, the thickness of oxide will also come down, okay. From earlier we have 400 Armstrong gate oxide when 5 micron process, then we went as we started going 0.25 we would not force 40 to 70 Armstrong of oxide. And finally what had happened now that they wanted less than 5 Armstrong of gate oxide, then only we look for high k. Because I cannot have one monolayer of silicon dioxide, so silicon or oxygen either. So I cannot create. So then I look for that capacitance value and say okay epsilon I can change, T I can change ratio, okay. That therefore high k appeared. Otherwise nothing better than silicon dioxide. It is the ideal insulator for everything, okay. So then after this gate oxide I deposited using process called low pressure LPCVD, we will look into this process later. And polysilicon is deposited. What is the reaction of poly will be? Poly is normally assumed through, how do you create polysilane? So you have a silane which reacts, it should actually somewhere remove the hydrogen out of it. Yes, then what should I do? I have Si4 and I want hydrogen to go away. How does hydrogen come out? It could dissociate. Key eat. That is cracking the silane means you heat the silane and why it then breaks? Because according to Gibbs free energy, the energy of formation becomes less than energy of, T delta S becomes higher, so it dissociates, okay. Is that fine clear? So as simple as that we follow in making polysilicon depositions, okay. Some people do two masks here and actually dope the poly right there. Is that clear? This poly itself can be doped by two masks. Why one this side mask, the other this side mask? So I can make P plus poly, N plus poly. But many a times this is not advised, okay. Because anyway during the day delineation I am going to implant for source drain. So I will prefer to use that rather than this. But there are processes or books you will see where this tape may be there. So you do not ask me why they have done it. No, they may have done it because they pre-doped the way. And that is very easy because that if I want to dope a poly during this poly deposition I will pass the phosphine gas for making phosphorous dope, arsenic gas for arsenic dope and boron diborin for boron dope. So deposition of boron dope glasses are much easier on boron silicon by just cvd, okay. But I will prefer not to do this as I am saying. But not that every company follows me. So I am not saying that some people do this as well, okay. So I just showed you that he has also said either master unmasked polycylion doping implant is performed. Now this is something as I say do it at a, the only thing we worry that whenever I do implant on poly, I want a very large concentration of poly. Why, why I want to be heavier doped? High, it is a metal replacement, okay. So I should be as conducting as possible. The best of whatever people say 10 to 20 ohm per square is the only sheet resistance one can attain never below 1 or 2 which is metal can give 10 to power minus 3 to minus 5 ohm per square. This cannot give below 10, okay. So all seven done it cannot replace a metal. So we will do some mischief. We will add some metal to it to form a silicide which will have better sheet resistance, okay. Okay, so as I say this process right now assume only poly has been deposited. Some people may dope, some people may not. So far so good. Poly has been deposited on gate oxide but there are no transistors. So now first time we make another mask which is mask 6 to make actual gates. So what is essentially gate? Please remember gate is up to where poly, every poly region was below gate oxide. There was every poly region would have gate oxide below. So I somehow use the sixth mask with lithography as shown here. This is pure resist and I etch poly from everywhere else, okay. But I do not etch thin oxide. Even if I etch I do not mind but for an implant I would prefer to hold that, okay. Is that clear? Dechanalization is necessary. So I will keep this thin oxide. So what since I want a vertically exactly etching kind. So normally all liquid etchants or wet etchants are isotropic in nature. They attack all sites. I want vertically down. So I do anisotropic etching which is essentially what we call as dry etching or ion etching. So I create gate. What is this? The length of this is what it will be for the transistor. And this second dimension which is not shown here in the inside, what will be that? The width of the transistor. Circuit people are only interested in to W by L and that is it. So for then if I achieve this, thank you very much, okay. Of course they will also ask VT. They are only looking for VT. No, they are looking for many things. They look for mobilities. What is mobility here? At the surface. That is very important for them. Musiox. So all of technology is transferring to device performance and since device is going to give me circuit performance, technology is connected to circuit performance which is our ultimate aim. This whole processing is not ultimate aim. This is all done for making a circuit go, okay. So ultimate social thing has happened like this. There was a time when designers used to say I want this and technology used to say well this much I cannot do for you. I cannot give this mobility. I cannot adjust the threshold so much. I cannot give anything of this kind. So then the designers used to crib. You know you are not able to give me what I want. I want 1 million transistors. You say no I cannot give more than 100,000 transistors. The things have changed in 2005 or onwards. Now we have a number of transistors available of uniformity in billions. Find a system which needs that, okay. So the question is now opposite. How much designers can think? Okay, system designers. Then the circuit designers. So first system is not thinking, then device is not thinking. Then why is the crib anything? Oh the process, process? Why are we improving process still is unknown to me. I mean this why Intel wants to go for 7 nanometers is the fun. But they are thinking that they will use their micro process design to much higher depth. But who needs a let us say 10 gigahertz micro process for what? I do not know except for a video game. Other than that you do not need anything actually, okay. Otherwise in real life you do not need 7 nanometer process anyway. Most circuits which you will build or system you will build in 45 nanometer is majority of circuits can go. 80 percent circuits will require no more than 45 nanometer. Some 20 percent may require 16 nanometer or 20 to nanometers or may be 1 percent will require 7 nanometers. So are this invention going on for process is only for the sake of that 1 percent? In my thinking is like this, okay. This may not be agreed by companies. But you can see I am right because most of the companies for foundry lines are closing. Because that is what they keep thinking. So right now my course of course I have the course person I will keep saying technology is the only thing. But in real life it is the system designers which actually should play better role. Because they are the ones who will say okay I want so many functions to be done in so much time frames then only I will require to do something. Nothing is happening. So please when you do the next courses you pay enough attention there because they are the ones who should drive us. Any thing you want I can do now. But their problem comes that oh I do not know what to use with. Ram hai. They say L2 lamp cash will require say 8K. Then they say no I want 64K. Okay 64 K dia. No no 1MB. Okay 1MB dia. You do not know how many exchanges you need on a processor more than 1MB. You do not have an architecture which requires that much exchanges. So just L2 vadaan se faheda kain? Haab iti rham pe aana hi hai aapko ya hard disk pe aana hi hai toh fir usko baana hi na faheda kitna exchange karna ja. Kitna register dal na ja. Just because you have register you keep adding registers. I saw actual architecture people have not come out with anything great so far. Van Newman ne jo bola why we are coming. So something different always happens. Do not blame technology. Technology has reached its peak and nothing is stopping them. Okay maybe I do not know the time. What is this LED business has come? Nainte mein bana hai aapko importance aapke usko. Okay. So now once I delineate the gate. Gate delineation means sizing W by L for the gate is called delineation of the gate. Okay. So I have delineated the gate. Once I delineated I remove the resist. Of course ye actual figure hai. Stanford University ke koi PhD, this is a plumber ke student ki. You can see this is the gate he has shown. This is the SEM picture. Is that okay? Now there are few things more are important in 16 mass process. Now we use another mass 7 actually to do what we call source train extensions and this word is very important. This was required because we said please take it wireless local loop. Always create noise. So now we want that many of the mass transistors have when we did for scaling down to a lower technology nodes, we figured out that the channel length became so high or so small and the voltage did not scale. Okay. There is no voltage scaling going on same as channel length scaling. So the field across the source drain and across the oxide has increased because it is not 1 to 1 scaled. Okay. If it is 1 to 1 scale I do not need anything. I just reduce everything. Fine. It should perform. That is what we earlier did. But now it cannot be scaled down. So we figured out that if your channel length is too small and the length being smaller and voltage is not scaling, the electric field even lateral as well as vertical is very high. Okay. Where is the maximum field in the channel? Maximum potential is at the drain. Okay. So the maximum field occurs at drain. So carriers starting from source get accelerated to its maximum velocity, generally saturated velocity to near the drain. And since they are the most energetic carriers and the oxide is thin enough, the electric field is large. Some of the electrons or carrier, either carrier can tunnel through this oxide on the gate. Okay. This is a short channel effect which is very very dominant effect. Is that clear to you? This is very very dominant effect. This high energy tunneling going through. Because the barrier is typically of silicon dioxide is known and if your energy is high enough, it can climb the barrier or it can go through the oxide if the oxide is thin by tunneling. This process is called thermionic field emissions. Okay. So a TFE can add to your carriers going into this. What is the problem carriers go into oxide? They will shift the VT charge goes there, sitting right there. Okay. If VT shifts, everything shifts. So I am worried that though tunneling happens. There is a model which one of my student created is called lucky electron model. How do you decide that how many carriers will go? So there is a probability theory which we created then which says that okay this is likelihood to this. This method is used where in ROMs, flash ROMs, E square ROMs or E-Proms, this is exactly what we are trying. We are actually trying to push and we do not want them to come back. So we put another gate and no connection. So let us go there. Okay. So Ford Kardiausko. So that is a flash ROM, a flash of course to erase but ROMs, E-Proms. Okay. So I now do some kind of a, I figure out at the drain end and since transistors are normally symmetric, why they are called symmetric? Source and drain are normally interchangeable. In some structures we now insist it should not be that but otherwise they are normally interchangeable. So whatever source for this device, if I, this will be source, this will be drain. So there is nothing great about it. So you find at the edges, I must have lighter doping. Why I should have lighter doping? Because if a normal p-n junction if you see the fields are, if your doping is smaller, the depletion width spreads because you know depletion width is in inverse proportion 1 upon n. So if n is smaller then the depletion width spreads. So the electric field also spreads. So near the surface electric field is not very maximum. Okay. It actually goes within the depletion there. This is therefore you need drain region, clover to drain area should be lightly doped than the drain itself. That is called LDD, lightly drain doped drains. So this process is LDD creation. Okay. What is LDD? Lightly doped drain. And why do we need it? I want to avoid short channel effects. Okay. I want to avoid short channel effects. In 5 micron process or 3 micron which I worked in 70s, I never used to think this because the channel length was 5 micron, voltages were 5 volt and everything was well within my control. So there is another implant has been done. Now one interesting thing feature you should see, poly is open. Okay. The resist is only on this side. So whatever implant you are going to do now will also get implanted into poly. Poly is open actually for implant. However this is very lightly doped. So poly is not really changing its better probability. It is still highly doped, highly resistive because which is this implant? It should be lighter implant. Why? I want impurities to be smaller in number because I want lightly doped. So I actually make a well N region, P regions here. Okay. Sorry. N regions there which is light because enginant device we are in a P well. So you made an N implant and what is importance is this you must say. Implant will always follow the edges. Okay. Implant will follow always ions. So it will go straight. So they will come here, they will come here. So this is called self alignment. What is the self alignment? Let us say during the last mass when this gate was delineated this shifted left. But the next implant will still follow the edges. So source drain will be always be available to you. Only difference will happen is the region areas may change. But at least transistor will always, in our earlier process we used to first make source drain and then used to make gate on that. So I must overlap my gate on source drain so that otherwise there is some area where there is no gate oxide. So this is called self alignment. Wherever gate is there from the edges impurities will go down. Okay. Ions will go down. So that is the biggest advantage. This process allows, it is called self alignment. There will be registration error. This may shift all of them. But so all the implants still will follow the edges of whatever polytels and therefore it will always, gate will be always aligned with the source drain. Is that clear? What is the biggest advantage that provides the capacitance at the corners is smallest there and parasitic capacitance reduction needs speed improvement. Okay. So that is a very crucial requirement for high speed circuits. Now having done LDD for n channel device, what should I do for now? Use the opposite mask or opposite resistor, whatever it is and do same thing for p channel device in the n well. So there is a thin p regions created which are going to be source drain. But these are lightly doped. What should be the resistance of the or resistivity of the actual source drain? It should be very low because I want a contact resistance to be low. But this is very high. So I cannot use this as a source drain. Is that point clear? This is only lighter doped. The problem start, now this is where that words space are k. I want only at the edges doping to be light. But the rest regions, I want it to be behavior doped, source drains. So I must now protect some regions here where n plus or p plus diffusion implants will not come. I have got the point. This is n, let us say p. So if I protect some part sideways and then do implantation heavy implants, then the small portion which is called spacer below that heavier implant cannot go and below is only lighter implants. So lighter drain or source can be created and the rest regions I can create heavier doped source and drains. This means spacer is required to create an LDD. This may be last light for the day. Then we will come back again. So now I, to create a spacer and from where the spacer should be? From the side wall because you know that is one which will block the implant, next implant. So I want a extra outside covering gate which spacer covers actually gate regions all around in fact, okay. And then when I implant that area will not receive the next implant below that it will be only lightly doped regions, okay. So spacer is required for creation of LDD structures. What is the disadvantage of spacer? Any spacer and when you put a LDD, the resistance of source drain will increase is that clear. So the spacer thickness is very very crucial. How much R I will be tolerating at LDD regions is a very crucial effect because remember channel resistance will be the smallest. Why uniting? You are pushing huge charge on the gate, you are uniting it out. But source drain N plus P plus they are also very low but which is the maximum resistance will come the below region of spacer. So spacer weights are very very crucial in decision of the speeds of the device. Is that clear? Typically if you want I may show you there will be R N plus let us say then R N then R channel then R N and then R N plus. This is drain, this is source. This is very low. These two are also very low, heavily doped, okay. But this LDD parts which is decided by spacer bits, okay. They may decide your actual speed of the circuit, okay. So the spacer has advantage of doing what? The removing short channel effect but it has created compensation of speed, okay. So one has to keep worrying how much speed. That is why that 10 gigahertz is not able. You know if I try something I actually do not reach there. I have to give speed if I want to improve device. First I must have LDD why? Other if device does not work then why are we doing all this? So device has to work. So LDD I need, okay. So something I must do tricky which will reduces the spacer thickness I mean whatever doping there. Can I slightly change this resistance? LDD at the edge I do not want to change but slightly closer or below I can add something. How can I add? I will show you a figure. This is my source drain and this upper portion is LDD. I want the below portion should be heavily doped. That means parallel resistance to above, okay. What can I, if I do a tilted implant I can go below. So halo has to be created, okay. So that is how we can adjust our resistances but halo will require another mask and also another damage at the spacer. Spacer if it does not stop it well then it will also create its own problems, okay. Spacer thickness cannot be uniform. The variation is 10 percent and the 10 percent variation actually changes 100 percent speed variations. See you then next Saturday.