 Hello and welcome to this presentation of the STM32G4 system configuration controller. STM32G4 microcontrollers feature a set of configuration registers located in the CIS CFG module. The system configuration controller gives access to the following features. Remapping memory areas and selecting the memory accessible at address 0. Managing the external interrupt line connected to the GPIOs. Managing robustness feature. Setting CCM, RAM, write protection and software arrays. Configuring FPU interrupts. Enabling and disabling I2C. Fast mode plus driving capability on some IOs and voltage booster for IOs analog switches. This slide describes the memory map of the STM32G474 microcontroller. The differences between the STM32G474 and STM32G431 variants are highlighted later in this presentation. The flash memory size is up to 512 kilobytes in a dual bank configuration. The FB mode bit determines the address mapping of banks 1 and 2 and also selects which bank is aliased to address 0. The SRAM total size is 128 kilobytes. It is split into three parts. The SRAM 1 size is 80 kilobytes starting from address 0x20 million. The SRAM 2 size is 16 kilobytes starting from address 0x20018000. The core coupled memory or CCM SRAM size is 32 kilobytes starting from address 0x10 million. SRAM 1 and SRAM 2 memories are located in the usual ARM V7M memory space dedicated to SRAM while the CCMS SRAM is accessed through decode and icode AHB buses. This architecture enables concurrent accesses to CCM SRAM and SRAM 1 or SRAM 2 memories. The memory remap at address 0 boosts up the code execution performance thanks to the dedicated icode and decode bus accesses instead of using the system bus. The memory remap at address 0 selects the memory accessible at address 0. It could be either the main flash memory or the system flash memory or the FMC bank 1 or the SRAM 1 or the quad SPI. The FMC bank 1 maps external NOR flash or PSRAM memory. The FB mode bit in the system configuration remap register allows the swap in between flash memory banks 1 and 2. This figure represents the STM32G4 bus matrix. The bus masters are at the top of the figure. The Cortex M4 core with its three AHB master interfaces icode, decode and system and the two DMA controllers. The bus slaves are at the right of the figure, internal and external memories and peripherals. The flash memory is read through the accelerator. When the Cortex M4 core accesses data within the code or data address range, the decode bus is used. When the Cortex M4 core accesses instructions with the code or data address range, the icode bus is used. The SRAM 1 is accessed by default through the system bus and can be accessed through the icode bus and decode bus when it is remapped at address 0 in order to increase performance. The CCM SRAM memory is always accessed through the i-bus and d-bus, allowing zero-weight state code execution. The quad SPI and FMC banks can be read and executed through the system bus by default and can be remapped at 0 to increase performance. The two DMA controllers can access all memories and peripherals. This table compares the code execution performance at 150 MHz and 170 MHz while running the EEMBC CoreMark benchmark. The maximum performance is reached when the code is executed in CCM SRAM with data is located in SRAM 1. It is also possible to reach maximum performance with code in SRAM 1 and data in SRAM 2 if the SRAM 1 is remapped at address 0. When executing from flash memory, the maximum CoreMark performance is reached when the ART accelerator is enabled and there is almost no loss of performance due to the flash access time requiring 7 weight states at 150 MHz or 8 weight states at 170 MHz. Enabling the prefetch buffer yields a slightly higher score, 3.36 CoreMark per MHz in case of single bank mode. This slide represents the key differences between the STM32G431 and STM32G474 microcontrollers. The STM32G431 line includes neither quad SPI nor FMC units. The STM32G431 line has smaller SRAM memories, a 16 kilobyte SRAM 1 and a 10 kilobyte CCM SRAM, both supporting party plus a 6 kilobyte SRAM 2. Regarding the mapping, the CCM SRAM is allied at address 0, X, 2000, 5800 to allow continuous RAM address range with SRAM 1 and SRAM 2 memories. At last, the STM32G431 has a unique bank of flash memory. There are three boot modes which are selected by the boot zero pin or the end boot zero bit if the NSW boot zero bit is cleared and by end boot one bit. When the boot zero pin is at a low level, the STM32G4 microcontroller boots from the user flash memory. When the boot zero pin is at a high level, the end boot one bit determines the boot mode. When it is high, the boot is done from the system memory that contains the ST proprietary boot code. The other option is booting from the SRAM 1 memory region. When the boot lock option bit is high, the boot is forced from the main flash memory. Software can dynamically select which memory is visible at address zero by programming the mem mode field in the syscfg memrp register. The default value of this field depends on the boot pin state and related option bytes value boot lock and SW boot zero. The on chip boot loader allows the user to program the flash memory with an image downloaded to the STM32G4 through a serial communication peripheral. The supported protocols are USART, USB, CAN, SPI, and I2C. The 32 kilobytes of CCM SRAM is particularly suitable for performance, integrity, and safety. The CCM SRAM is accessed through the decode and icode buses without any remapping which enables code execution at zero weight states. The CCM SRAM supports parity check. The data bus width is 36 bits because 4 bits are available for parity check i.e. 1 bit per byte in order to increase the memory robustness as required for instance by class B or SIL standards. Class B and SIL are safety standards. Class B is for home appliances and SIL for the safety integrity level. The parity bits are computed and stored when writing into the SRAM. Then they are automatically checked when reading. If at least one bit fails, a non-masculable interrupt or NMI is generated. The same error can also be linked to the break input of the timers and the HR TIM system fault input. Note that the parity check is disabled by default. The lower 32 kilobytes of the SRAM 1 also support parity generation and checking. The CCM SRAM is also suitable for secure applications. It can be write protected with a 1 kilobyte granularity. It can also be read out protected via the RDP option byte. When protected, the CCM SRAM as well as the flash main memory and the backup registers are totally inaccessible in debug mode or when code is running from boot RAM or boot loader. The CCM SRAM is erased when the readout protection is changed from level 1 to level 0. The CCM SRAM can be erased by software by setting the CCMER bit in the CCM SRAM system configuration control and status register. The CCM SRAM can also be erased with the system reset depending on the CCM SRAM RST option bit in the user option bytes. The system configuration register 2 contains the control and status bits related to safety and robustness such as the CCM SRAM parity error flag and the control bits to direct some error detection events to the timers break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events include a flash error code correction event, a power voltage detector event, SRAM 1 and CCM RAM parity error event, and the Cortex M4 hard fault. The floating point unit, or FPU, present in the Cortex M4 core sets the cumulative exception status flag in the FPSCR register as required for each instruction in accordance with the FPV4 architecture. The FPU does not support user mode traps. The exception enable bit in the FPSCR read as 0 and writes are ignored. The processor also has 6 output pins IXC, FC, OFC, DZC, IDC and IOC that each reflects the status of one of the cumulative exception flags. When the corresponding enable bit in the CIS-CFG CFGR1 register is set, an interrupt is requested when the flag is set. The interrupt service routine is in charge of determining which flag or flags have been set. The four I2C controllers embedded in the STM32G4 microcontroller support three speeds. Standard mode, the maximum bit rate is 100 kilobits per second. Fast mode, the maximum bit rate is 400 kilobits per second. Fast mode plus, the maximum bit rate is 1 megabit per second. Fast mode plus requires a high drive capability which is enabled in the CIS-CFG module. Since high drive is controlled at pin level, it is also available for the other alternate functions. Each I2C controller has a control bit in the CIS-CFG CFGR1 register to enable fast mode plus driving capability mode. Each pin PB6, PB7, PB8, PB9 has its own I2C PBFMP control bit to activate the fast mode plus driving capability, whatever the selected alternate function. When FM plus mode is activated on the GPIO pin, the speed configuration of the GPIO programmed in the GPIO XO speed R register is ignored. In some cases, there are two ways to activate the FM plus mode. For instance, the PB8 pin is configured as I2C1SCL supports FM plus when the I2C1FMP or I2CPB8FMP bit is set to 1 in the CIS-CFGCFGR1 register. Two bits from the CIS-CFGCFGR1 register are used to select the power supply of the IO analog switch, boost EN and ANNA SWVDD. They have to be initialized according to the voltage of the VDD and VDDA power supplies. When VDDA voltage is larger than 2.4V, the IO analog switch should be powered by VDDA. When VDDA voltage is lower than 2.4V and VDDA is higher than 2.4V, the IO analog switch should be powered by VDDA. When both VDDA and VDDA voltages are lower than 2.4V, the IO analog switch should be powered by the output of the VDDA booster. A to F are 16 pin wide ports. Port G is 11 pin wide port. Each of the 16 EXTI configurable events related to GPIO ports has an independent multiplexer. The EXTI multiplexer outputs are available independently from any masks defined in the EXTI IMR and EXTI EMR registers. For more details about the system configuration module, refer to the reference manual for STM32G4 microcontrollers. Refer also to these trainings for more information if needed. Extended interrupts and event controller. Arm cortex M4 core. Timers. High resolution timer.