 Hello and welcome to this presentation of the STM32U5 RAM Configuration Controller. The RAM Configuration Controller is in charge of handling the error code correction, or ECC, supported by SRAM2, SRAM3 and backup SRAM, disabling ECC through a software sequence based on a key register, performing global SRAM erasure through a software sequence also based on a key register, protecting SRAM2 against right accesses for each 1 kilobyte chunk, and programming the number of weight states according to the actual frequency when the microcontroller is in voltage range number 4. This table summarizes the features of the internal SRAMs. Let us start with the features supported by all internal SRAMs. Low power background autonomous mode in stop 0 and stop 1 modes. Erasure with the readout protection level is decreased. Software erase. Adjustment of the number of weight states in voltage range 4. Low power background autonomous mode in stop 2 is only supported by SRAM4 because it belongs to the smart run domain. The smart run domain architecture relies on a DMA allowing autonomous operation during low power modes down to stop 2. The contents of SRAM2 and backup SRAM can be retained in standby mode. The contents of backup SRAM can be retained in VBAT mode. SRAM2 and optionally backup SRAM are protected by the tamper detection circuit and are erased by hardware in case of tamper detection. The ECC is supported by SRAM2, SRAM3 and backup SRAM when enabled with the SRAM2 ECC, SRAM3 ECC and BKP SRAM ECC user option bits. The SRAM2 is made of 64 1 kilobyte pages. Each 1 kilobyte page can be write protected by setting its corresponding PXWP bit in configuration registers. SRAM2, SRAM3 and backup SRAM implement a unit capable of detecting and correcting single bit errors and detecting double bit errors thanks to 7 ECC bits that are added per 32 bits of data. For 64 kilobytes blocks of SRAM3 and the 64 kilobytes of SRAM2 are ECC protected. Regarding SRAM3, the ECC codes are stored in a dedicated part of the SRAM, the upper 64 kilobyte part of SRAM3. This area shall not be used by applications when ECC is enabled. Regarding SRAM2, the information which is stored in 39 bit wide, 32 bit data plus 7 bit ECC. Consequently, the entire SRAM2 is always accessible. ECC error detection is reported to the Cortex-M33 as follows. Single error detection and correction cause an interrupt request. Double error detection causes an interrupt or non-mascable interrupt. The failing address is latched in a register. Optionally, the full SRAM2 or 8 kilobytes or 56 kilobytes can be retained in standby in stop 3 modes supplied by the low power regulator. This is called standby with SRAM2 retention mode. ECC can be automatically enabled by programming user option bits in the flash memory. ECC can be disabled by executing a software sequence that writes keys into ECC key registers. Since ECC requires a read-modify-write operation, when writing partial data, byte or half-word, the performance can be measured with and without ECC. When ECC is disabled in SRAM3, the last 64 kilobyte block containing the ECC codes is accessible by masters. This can be used for error injection. When ECC is enabled in SRAM3, this area is reserved and cannot be accessed by masters. To correctly read data from SRAMs, the appropriate number of weight states must be programmed depending on the AHB clock frequency, HCLK and voltage scaling range as shown in this table. Note that one weight state is required in range 4 when the frequency exceeds 12 MHz. The SRAM2 is made of 64 1 kilobyte pages. Each 1 kilobyte page can be write protected by setting its corresponding PXWP bit in the RAM CFG memory to write protection 1 and 2 registers. Two registers are necessary to form a bitmap of 64 bits. The consequence of attempting to write a bitwrite protected page is that the SRAM controller returns an error response to the AHB master. When this master is the Cortex M33 CPU, this error causes a bus fault exception. When this master is a DMA channel, this error is interpreted as a DMA transfer error. SRAM erase can be requested by executing a software sequence based on keys that have to be written to key registers. SRAM busy flag is set in the related SRAM interrupt status register as long as the erase is ongoing. The total duration of each SRAM erase is equal to NHB clock cycles where N is the size of the SRAM in 32-bit word units. If the SRAM is read or written while an erase is ongoing, weight states are inserted on the AHB bus until the end of the erase operation. The RAM configuration controller generates the following interrupt requests. A regular interrupt in the event of a single error detection and correction. The non-mascable interrupt in the event of a double error detection. Status registers provide the current status of these events, the address at which a correctable error has been detected, and the address at which a non-correctable error has been detected. Note that these addresses are locked until software clears the address latch enable bit in the control register. The table indicates the effect of low power modes on the RAM configuration controller. Sleep mode has no effect. RAM CFG interrupts cause the microcontroller to exit the sleep mode. In stop mode, the contents of RAM CFG registers and SRAM contents are kept. The ECC is functional and ECC error interrupt or NMI causes the microcontroller to exit the stop zero and stop one modes. In stop three, no SRAM access is possible. In stop two, only SRAM four remains accessible in the smart run domain by implementing the low power background autonomous mode or LP BAM. So in stop two and stop three, no ECC error can occur because SRAM four is not ECC protected. In standby mode, the RAM CFG module is powered down and must be re-initialized after exiting standby. Thank you for following this online training.