 So, today we will look at several non idealities in capacitance voltage characteristics, but before we do that I just wanted to discuss two important points based on the ideal C v characterization that we discussed in the last lecture. The first one is just to sort of understand how does a C v curve depend on oxide thickness and substrate doping. We have already looked at various other factors such as measurement frequency dependence, temperature dependence and light dependence during the measurement and so on and so forth. All these are external characteristics, but the device itself can have different oxide thicknesses and different doping concentration. So, let us just look at the T ox versus I am sorry T ox and NA dependence of ideal C v and we are still discussing on ideal C v. So, let us just consider high frequency capacitance it would be similar for low frequency as well and you know as you recall from our last discussion if you look at C versus V G for a P type substrate capacitor you know it would look something like this it has a flat band voltage which is 0 and the capacitance voltage curve will essentially look like this and this is where you reach a strong inversion and after that you have a flat characteristics. Let us say this is the case for a particular doping concentration of NA 1 and a particular oxide thickness of T ox 1. First let us consider a situation where T ox 1 is kept constant this is not changed, but this NA 1 is varied. Then let us ask the question you know what would happen to the C v characteristics. Again let us for the time being consider it is an ideal capacitance somehow I have made this capacitor so that V F B is 0. So, the V F B point essentially is out here for all these cases. Now if you let us say increase the substrate doping what you would expect because of that is your threshold voltage should increase as we have discussed in very early lectures of this course. Threshold voltage has a very strong dependence on substrate doping concentration. If your threshold voltage corresponding to NA 1 is out here your threshold voltage corresponding to let us say NA 2 which is higher than NA 1 will certainly move to the right because it will have a higher threshold voltage that is one aspect. In addition to that the other thing that would happen as you can well imagine when you you know reach inversion right the inversion capacitance eventually the minimum so called minimum capacitance that we are talking about you see depends on what is your maximum depletion width. And of course that maximum depletion width will set the minimum semiconductor capacitance that will come in series with the oxide capacitance. And you know eventually you get the equivalent series combination of these two capacitance, but the deciding factor is really the depletion width maximum depletion width. As you could now well imagine as you also increase the substrate doping concentration due to the fact that the depletion width has an inverse square root relation with substrate doping concentration. The depletion width will decrease and hence you would expect the capacitance to increase. So, what it means is that the minimum capacitance should also go up as you start increasing NA 1 right. So, as a result of that you know your curve may look something like this if we say that this is a pivot point here. The maximum capacitance will not change necessarily because maximum capacitance is essentially gone by the oxide thickness we are saying that we are keeping oxide thickness constant we are not changing oxide thickness. But the V t will shift minimum capacitance will also shift. So, your C V curve will probably look something like this this is NA is increasing NA 2 now if you increase NA further you know this will increase further and this will also increase further this should voltage will increase further right. And you know eventually you start seeing the curve which would probably look something like this right. So, notice that two things happen with varying NA V t increases and minimum capacitance also increases right both happens sort of simultaneously. Now, if you were to consider the other situation wherein you keep NA constant right and let us sketch those characteristics as well let us again say that we start with some C V characteristics for certain value of you know NA 1 and T ox 1. Now, I start varying T ox let us say I start increasing T ox. So, now let us see what happens if you increase T ox you would expect because your C ox has relation epsilon ox epsilon naught over T ox right. Your oxide capacitance will start decreasing as you start increasing the oxide thickness and that will certainly have an impact on the maximum capacitance that we will have. Because maximum capacitance is solely governed by oxide capacitance and oxide capacitance starts varying as you vary T ox. Now, let us ask the question what will happen to the minimum capacitance substrate doping does not change as a result of that the maximum depletion width in inversion does not change in silicon and hence the silicon minimum capacitance does not change, but what we measure externally is silicon minimum capacitance in series with oxide capacitance. Because oxide capacitance is decreasing all those silicon minimum capacitance does not change the equivalent series capacitance will decrease right because C ox is also changing right. So, what you would then expect is that if you start increasing the oxide thickness this obviously will come down. Let me just illustrate here and accordingly out here as well because although NA is not changing silicon capacitance is not changing external oxide capacitance has decreased and as a result of that your total capacitance will also go down and when you are started increasing your oxide thickness your threshold voltage also increases. So, what you might actually see is occur which would look something like this right. It starts moving in this direction and it starts moving down and the reason why it happened here is that for threshold condition again as you remember just as threshold voltage increases with increasing substrate doping concentration threshold voltage also increases with increasing oxide thickness. So, this threshold minimum capacitance point shifted to the right and also the minimum capacitance value came down. On the other hand let us say this is for T ox 2 which is greater than T ox 1. Now, if I choose another T ox which is less than this then your mean capacitance here will increase because now I have chosen T ox 3 which is less than T ox 1 you see this will increase and because oxide thickness decrease your V t will also decrease now and hence it will probably look much more steeper and your minimum capacitance will increase now because your oxide capacitance which is coming outside in series with silicon capacitance has gone up now. So, your C v may look something like this it will have a saturation at lower value of V g because your V t has come down at the same time your minimum capacitance increase because your oxide capacitance increase right. So, you know your total capacitance sort of goes up and down because your oxide capacitance is changing as a result of that the capacitance in the entire C v range will go up and down as opposed to this case where only substrate doping was changing. So, these are some very important differences that you may want to keep in mind. In fact in the next lecture we will also discuss once you do a C v measurement how can you start extracting various parameters, but this is something that you know will be useful to remember when we have that discussion. Now, one other point that I wanted to discuss is C v on we have been talking about MOS capacitor, but we also built transistors using these right. So, is there any difference in C v of a capacitor device and a transistor device in other words the question that I am asking here is that you have p type substrate let us say your oxide and you have essentially built an electrode here which is your gate. Now, this is essentially a two terminal capacitance device and you have another device where in you know everything looks same you know you have this similar gate area and all that, but in addition you have also made junctions here n plus n plus and there are contacts to the junctions as well and let us say we have connected all these together. Whereas here this is the low point and this is v g both have the same area. So, you would expect the capacitance should be similar because the capacitance is essentially governed by what is happening here. However, there is one very important difference that you have to keep in mind and that is the behavior under high frequency characteristics. Let us say this is C the low frequency capacitance if you do L F C v measurement on this structure as well as this structure you know you get a curve which will be exactly identical right. Let us say if this is a curve for capacitors then your transistor curve will essentially overlap on top of each other. This is what you expect because anyway the area is same. So, your capacitor that is formed is you know identical really, but your high frequency capacitance in a case of this device as you know will essentially look like this right. In inversion you have the minimum capacitance under high frequency this is your H F C v for capacitor structure. On the other hand if you were to do this on a transistor you see the transistor will give a capacitance voltage characteristic which will look exactly like a low frequency C v. In other words if you are doing the C v measurement on a transistor structure with the connections as shown here whether you do the C v at high frequency low frequency does not matter. They always are identical exactly identical and all look like a low frequency C v. Only in a capacitor structure in inversion your capacitance is quite different from the low frequency capacitance. And if you think about this this is obvious and it is no surprise at all because as we discussed in the last class the very fact why we got a capacitance which is lower is because the electrons were not responding in a capacitance structure. But you see now you have given a huge reservoir of electrons here right this is n plus there are lot of electrons which are available right next to that capacitor. So, you do not have to generate these electrons in a depletion region. So, these electrons will come back and forth instantaneously in this structure because of the fact that just as the majority carrier holes are available in this capacitance and hence you do not see any difference in accumulation region. Now, in inversion region also although you do not have electrons as majority carriers here, but there are two junctions which are sitting right next to it which have electrons as majority carriers. So, you do not need to generate electrons anywhere else in this device these electrons can come back and forth instantaneously. And hence there is no dearth of availability of electrons electrons respond instantaneously and hence your semiconductor capacitance is very large it is no longer the depletion capacitance because you do not need the depletion edge to respond. The inversion charge right here is responding instantaneously as opposed to the depletion edge responding you see and hence you do not see any difference here. This is another important point that you need to that is why we make these junctions right. So, that you know instantaneously we can turn on and turn off this transistor otherwise you would not turn on the transistor at you know terahertz frequency. If you have to wait for these electrons to generate because of the generation that is happening right because we have this source so called source junction, but here both are source junction because both are at ground potential, but in the transistor action one of them is at positive potential that cannot source because you are draining the electrons there, but the source can instantaneously supply electrons into it right and that is how we can switch the transistor at very high frequency ok. Now, let us look at the first thing that we will look at is non zero flat band voltage. So, V F B not equal to 0 what are the contributors for V F B essentially as you may recall V F B is the work function difference between the metal and silicon right. Because in ideals capacitance we said I have chosen a fictitious metal which has the same work function as silicon, but that will never be the case ok. Your capacitors made on p type silicon are likely to be for n channel transistor and they will have their work function on the gate side which is closer to the conduction band of the silicon it will be like n plus on the gate ok and hence there is a phi m s and in addition to that you can also have what is called fixed oxide charge q f here refers to fixed oxide charge meaning oxide is also not perfectly ideal ideal oxide will not have any charge inside it, but a non ideal oxide can have some non zero charge inside it and that would also impact your capacitance voltage curve. So, now let us look at the impact. So, let us say this is my ideal C V curve which has V F B is equal to 0. One important thing that you want to recognize here the capacitance value at any gate voltage is uniquely determined by the surface potential in silicon. In other words when you have the accumulation condition if you recall if I am looking at the p type substrate and if this is my oxide interface and this is my p type substrate what will happen I have a accumulation region which is this if this is F bands are bent up like this you see correct. That is I have more holes here and that is what is called accumulation region and at this condition I have flat band what is flat band you know if this is my oxide interface again my bands are perfectly flat that is psi s is equal to 0. And as I am going in this direction now I start seeing some depletion this bands will start bending like this again you see surface potential has changed surface potential 0 surface potential negative surface potential positive going down is what we treat as positive surface potential. And eventually when you reach inversion these bands are bent so much that your band bending is 2 phi b and you have reached inversion condition. In other words the capacitance value is uniquely determined by psi s right there is a very specific one to one correspondence between the silicon capacitance and the psi s the band bending the value of psi s as long as you have the same psi s you will get same capacitance that is the message because you see it is only the silicon capacitance that is variable oxide capacitance is not variable. So, in other words now when I have a non zero V F B all that it would do is that in order to get a flat band condition under which I should get this capacitance by the way this capacitance is called C F B. Once you fix your device oxide thickness and doping concentration C F B will never change. So, if you have a different phi m s if you have a different phi m s non zero phi m s it will give non zero V F B and similarly if you have a fixed charge it will give non zero V F B all it will do is that it will translate the C V curve along the gate voltage axis. In other words if my V F B let us say is minus 0.5 volt what it means is that in order to get C F B value I need to go to minus 0.5 volt. This is where you know I will get this capacitance value and after that as I start applying more gate voltage you know it will go towards this and then capacitance will start increasing and I start applying positive voltages beyond minus 0.5 band will start bending like this capacitance will start decreasing like this. So, in other words what you will have is really this. So, there is this translation important point. So, V F B due to phi m s and Q F you know translates C V curve translates the ideal C V curve that is you know whatever you got based on your ideal C V characteristic it just you know either to the left or to the right depending on whether your V F B is negative or V F B is positive. In fact as we will see in the next class in fact this is the information that we use to find out what is the fixed charge in the oxide when you actually measure a device. Because once you measure a device I can generate an ideal C V we will talk about it in the next class and then I can compare an ideal C V with the experimentally measured C V and looking at the difference I can generate all these non idealities in a capacitance voltage I mean the MOS capacitor. Now this fix by the way phi m s is very obvious you have different work function this fixed oxide charge is you know essentially attributed in case of silicon oxide at least Q F is always positive. And essentially what is attributed is that if you have this silicon oxide you have to grow this silicon oxide on top of silicon. When you are growing the silicon oxide you are transitioning from silicon to may be silicon oxide as I start growing thicker and thicker oxide. But in this transition region this transition region is really non ideal. In other words you really have something like s i o x you see when x equal to 0 you have silicon when x is equal to 2 you have s i o 2. But here you have really s i o x you know it is not perfect silicon not perfect silicon oxide something in between right. So this is really a non ideal thing. So what is proposed really is that you really have in this was supposed to be silicon oxide within a abrupt transition. But really in this region you have oxygen vacancies that is why your oxygen is no longer 2 it is less than 2 where your x is less than 2 x is less than 2 because you have oxygen vacancies. What I mean by that is that if you were to look at you know the silicon oxide matrix the silicon oxide matrix will essentially look like this ideally. You see silicon has valence of 4 and all that is satisfied oxygen has valence of 2 and that is also satisfied. But let us suppose that this oxygen is not there this is missing then this is what is called a defect side. And this defect side ideally should have one electron from silicon and one electron from this silicon. But it tends to lose one of the electron right because it cannot hold that electron there. And hence this defect side becomes positively charged. So that is a very plausible very simple model that is given and in fact this has also been you know validated by doing lot of structural characterization of silicon oxide right. So invariably whenever you grow a silicon oxide on silicon you have this transition region and this transition region has lot of oxygen deficiency. And that oxygen deficiency results in a missing oxygen atom and a defect side which becomes positively charged right. So invariably whenever you are doing MOS capacitance characterization on a SiO 2 you will invariably see that you know because there is a positive charge the C v will always tend to shift left. This is obvious right if you have positive charge you know your inversion voltage also decreases right. And that is also obvious right you have positive charge this positive charge can attract electrons right. In other words you need to inversion need reach inversion much earlier correct. So if you have a negative charge it will be the opposite it will shift to the right. So Q f is something very important that you need to consider right. So this is essentially one of the non-ideality. The next non-ideality which is also very important is what is called interface traps. It is denoted as Q i t which stands for interface trapped charge or D i t or N i t. There are different ways of so Q i t essentially means interface charge. In other words I am essentially saying coulomb per centimeter square. So much charge is available. N i t means defects or traps density. This is charge density that is why it is per centimeter square. Here it is number per centimeter square. So many 10 power 12 traps per centimeter square. So there is no charge here you multiply N i t with Q you get Q i t. So that is Q i t is Q times N i t. You are converting it into charge and D i t is something is again a density. But its density trap density not just defined in terms of aerial density. Its density in terms of area as well as per unit energy. It becomes clear in a minute what we mean by that. In other words the unit of this is per centimeter square E v and this E v is essentially what I meant. It really tells you per unit value of energy in the band gap what is the density. So first of all what are these interface traps as the name suggests when you have silicon and oxide exactly at this interface. The fixed oxide charge is little away from the interface. Whereas interface state charge that we are talking about is exactly at this location and hence the name interface charge going from silicon into silicon oxide exactly at this interface. Now again if you see at this interface you have lot of non idealities. You have some silicon atoms which is sitting here. The silicon was happily sitting here bonding with four neighboring atoms. But here you do not have a silicon here. So here you have what is called a silicon dangling bond right at the interface. Similarly you may have an oxygen here and that oxygen bond length with silicon may not be perfect as it should have been in silicon oxide. So all these are defects again and these defects are exactly at interface and this is very important and hence because they are exactly at interface their charge state changes. That is the major distinction between the fixed charge that we discussed. Fixed charge is little bit away from the interface not exactly at the interface. This region which is a transition region. This is where the fixed charge is and this being away from the interface it does not interact with the silicon underneath and its change charge state does not change and hence the name fixed charge. Whereas the interface charge its charge state changes. It can either you know get an electron or release an electron. It can be positive charge neutral or negative charge depending on the nature of the defect. Now these defects is what is going to impact your CV characteristics and hence the behavior of the MOS capacitor and transistor very significantly. Now this is in terms of position. Let us look in terms of energetics. Now this is my silicon. Let us just consider flat band condition and this is my oxide which has huge band gap as we have been discussing and you have some gate metal you know it could be anything some let us say N plus polysilicon. Now this is silicon and this is SiO2 and this is gate. Silicon here is perfect band gap EG. There are no allowed energy states here. Oxide again no allowed energy state in between large band gap. But this transition region is non ideal and it has large number of allowed energy states. This is a energy picture of the same phenomenon in terms of the physical defect. The physical defects are exactly at the interface. Those physical defects in turn translate energetically either traps closer to the valence band, traps closer to the conduction band and traps somewhere anywhere in the middle of the band gap. And experimentally you know it has been seen that if you were to really go from conduction valence band edge to the conduction band edge in terms of energy. In terms of your trap density you know you get a distribution which looks something like this. At the middle of the energy which is what is important as for as transistor capacitor operation is concerned. This is a region when we are applying gate bias. This is a region where in we are moving the Fermi level. We are moving the Fermi level from accumulation towards the inversion region. We do not go very close to valence band anyway. We do not go to very close to conduction band anyway. And now this here distribution is what is called DIT because this is given as a function of energy value and per unit area value. Per unit area at a given energy what is the trap density. That is what we call DIT interface trap density in terms of number per centimeter square E v. So, from DIT if you want to get NIT you integrate this over energy range. In other words you know you get NIT as integral from E 1 to E 2. DIT which is of course a function of E D E will give you NIT. Now you see you can sort of make correspondence with all these. So, DIT has a unit of per centimeter square E v because you are integrating over D E. You know E v gets cancelled in terms of dimensional consistency and you get the trap density which is number per centimeter square. So, this is what I meant DIT. You know this is density which is not only aerial density but also energetics. Now what is the impact on the C v? What happens when you are doing C v? When I have flat band condition if it is a p type semiconductor as you know the flat band condition the Fermi level looks like this. Bands are perfectly flat. And in fact if it is inversion accumulation condition then you know these bands will actually bend like this correct. I am just keeping Fermi level as constant. I am not disturbing that. I am just changing the bands to sort of see what happened what is happening. Now you see when you have the Fermi level here again based on the Fermi Dirac statistics you can say that everything above the Fermi level is empty. There are no carriers there no electrons there. Everything below the Fermi level is filled with electrons that is how we define Fermi level in the easiest manifestation of the Fermi level definition. What happens on the inversion? If I go into inversion the bands as you know will bend downwards you see correct. As you know the Fermi level comes closer to the conduction band that is why it is unlike now because it is inverted now. And here in accumulation it was very close to valence band it was very heavily p like right. So, now the bands here the traps that we are looking at these are the interface traps you see. Now what happens when I sweep the gate voltage from accumulation to inversion the location of the Fermi level with respect to band is changing at the surface or the bands are bending with respect to Fermi level you know one and the same. So, in other words what has happened here you see in accumulation most of the traps were empty and inversion most of the traps are filled. So, when I am sweeping the gate voltage from one extreme to the other extreme the charge state is changing and hence it is not fixed charge it is a variable charge. The variable charge the exact quantity depends on the exact value of gate voltage because exact value of gate voltage in turn depends on in turn dictates what is your band bending and that in turn dictates how many traps are empty how many traps are filled. So, now you know the conclusion based on this discussion is that the Q i t is not fixed in other words changes with respect to psi s. Psi s is changing as a result of that you know you will also have this variation. Now the next question to ask is that now we have understood at least the charge should be changing now is it going to be positive charge negative charge now how is the charge going to change. Now that depends on the nature of the interface traps and based on all the experimental studies again and lot of theoretical studies as well a fairly good model for interface state traps has been you know evolved and that essentially states that if you have traps in silicon you know distributed from the conduction band all the way to valence band edge right. The model says that the traps you know above mid gap behave as acceptor like traps you will see what it means by that. And the traps below mid gap right behave as donor like traps. Now the donor and acceptor like essentially sort of used here you know the actual donor if you are talking of phosphorus as a donor you know donor is very close to conduction band correct it donates an electron. So obviously the traps are not good donors right because they behave as donor like but they are below the mid gap they cannot really donate if there are any electrons they can catch the electrons but they cannot really give out electrons you see. Similarly acceptor and ideal acceptor boron you know it is energy level should be very close to valence band only then it acts as a very good acceptor it donates holes but here these so called acceptor like traps are above mid gap. So they are certainly not going to donate you any holes ok. So these traps are not going to give you any extra free carriers but they actually instead take out the free carriers. Now when they trap these carriers the question is whether they will have positive charge and neutral or neutral and negative charge ok because you can only change between two states right you can go from neutral to positive or you can go from neutral to negative you cannot go from negative to positive unless it captures multiple carriers that does not happen. In other words let us consider arsenic atom arsenic atom can either be neutral or when it donates an electron it becomes positive but it cannot become negative right because when it has all the electrons filled it does not have any tendency to get an extra electron over there you see. So arsenic atom in silicon can either be positively charged or neutral similarly a boron atom in silicon can either be neutral or negatively charged correct but it cannot be positively charged. So the meaning of this is only that if it is a acceptor like trap it can either be neutral or it can be negatively charged ok. If it is donor like it can be either neutral or positively charged. So that is how these states behave more particularly if you have an acceptor like state if it is filled with electron you know you know then that will have a negative charge ok on the other hand if you have a donor like state if it is filled with electron it will be neutral ok. A donor like state which is empty of electron will be positively charged ok. So and again acceptor like state which is filled with electron will be neutral ok. So in other words what you essentially have if we again look at this band picture I mention let us consider this is EI ok then this is ECEV and we just said that all these above mid gap this is mid gap above mid gap are acceptor like and all these you know below mid gap are donor like. In other words when my Fermi level is exactly at mid gap if Fermi level is exactly at mid gap what does it mean all these donor like states are filled with electron they have not donated electron these traps and hence they will all be neutral ok. And all these acceptor like impurities are empty of electrons they are not filled with electrons if acceptor like states are empty of electrons again they are neutral. In other words when you have the mid gap condition when the surface potential in silicon corresponds to the mid gap condition then interface traps do not correspond do not give any extra charge. So that one point which will act as a pivot point will be exactly same with Q i t is equal to 0 or meaning D i t is equal to 0 or D i t non-zero that will be the same point ok. When this starts coming down you see when this starts coming down these acceptor states continue to be neutral because they are empty they continue to be empty. But some of these donor states are now getting uncovered they will leave out an electron. Now lot of donor more particularly when this you know comes all the way down that is what happens in a accumulation condition in an accumulation condition bands are bending at the surface Fermi level is very close to valence band meaning most of the traps are empty ok. So anyway acceptor traps which were anyway empty are not going to give charge. But all these donor like charges will now give positive charge ok. So more particularly now when you have accumulation condition this is your accumulation condition correct this is Fermi level this is E v this is E c you see all these traps are empty most of the traps are empty. And these acceptors do not give any charge but you have net positive charge here opposite thing happens in inversion in inversion the bands will start bending down the donor like traps are all filled down in invert anyway whenever they are filled they do not give you any charge. But acceptor like traps as soon as they start getting filled they start giving you a negative charge ok. So in other words if you see here this is how you will have your correct. So now most of the traps are filled because now the E c has come very close to Fermi level. So most of the traps below Fermi level are all filled donor like traps are not going to give anything extra to me mid gap is somewhere here ok. But these traps which are acceptor like traps you see they are all filled with the electron they give negative charge ok. So when I am going towards inversion I get so as I go closer and closer to the inversion I am filling more and more negative charge and the charge magnitude is increasing towards more and more negative. At mid gap 0 as I start going towards accumulation the charge magnitude will again start becoming more and more negative as we discussed here because more and more donor states are getting uncovered. So if this is what is going to result in a phenomenon called stretch out of a CV curve ok. What it means is the following right. So now again let us look at the capacitance voltage curve. Let us say this is my ideal CV with V F B is 0. If V F B is non-zero this will probably have a parallel shift. Now in case of interface states right what will happen ok. So somewhere here this is V F B this is all flat band right somewhere here I have a mid gap condition you see this is flat band this is deep accumulation this is deep inversion and somewhere here I have a mid gap condition. At mid gap condition there are no extra charges because of interface states ok. So which means you know your capacitance value will be exactly here for this gate voltage. But now as I start going towards this direction I start getting more and more positive charge. Positive charge will tend to shift the capacitance to the left remember but it is not fixed positive charge. The positive charge starts increasing as I start going away and away. So in other words this curve starts looking like this. You see this shift that shift is due to positive charge and because the positive charge is increasing this shift is also increasing it is not a parallel shift you see. Similarly in this direction I start having negative charge. Negative charge will tend to shift the CV to the right and again more and more negative charge starts coming up and hence the CV comes up like this. So in other words you see this is what we call stretch out CV it is as if you have taken that CV and you have stretched it out you see. So that it takes much larger voltage span to go from accumulation to inversion condition as compared to a much shorter voltage span to go from accumulation to inversion. So now if you have higher and higher trap density that is interface trap density your stretch out will be more and more. If let us say this is for D I T 1 and now you have D I T 2 which is even higher than this then the stretch out is even much more you will probably get a stretch out which will look like this. This could be D I T 2 which is much greater than D I T 1. Again at this point you may not have any charge you know as I start going to the left more and more positive charge continues to increase and in this direction more and more negative charge continues to increase as it increase this is essentially the stretch out phenomenon. This is as far as high frequency capacitance is concerned. Now there is something interesting and that is this interface states is traps or states you know we use it interchangeably also impacts CLF low frequency capacitance. Now that is a little bit interesting thing to look at. If I have this C versus V G let us say that you know I actually do the measurement instead of being very sharp ideal CV high frequency CV you know let us say this is high frequency and accordingly the low frequency will probably like this correct. And now because of the interface state density let us say that the CV curve actually looks something like this. Now based on this discussion I mean we have not discussed what else will happen to low frequency CV. The minimum that you would expect is that because high frequency looks like this the low frequency at least should come up like this and go up here. Even the low frequency should be stretched out just as high frequency get stretched out. But very interestingly that is not the only effect for low frequency there is another effect for low frequency curve and that is in the region between flat band to inversion that is in the depletion region. Your low frequency capacitance you know your low frequency capacitance will be higher than little higher than the high frequency capacitance and of course eventually it will go up like this and indeed low frequency is also stretched out just as high frequency is also stretched out. But earlier in the presence of ideal condition meaning no DIT the low and high frequency not only super imposed on each other at accumulation but also throw out depletion and then they started departing. But here even in depletion the low frequency capacitance is higher than high frequency capacitance and this is essentially because the low frequency capacitance value is also increased because of trap capacitance. In fact we model this as CIT which stands for interface trap capacitance. In other words more specifically remember the equivalent model that we had I had C ox I had C silicon here correct this is my equivalent and now I have something called CIT. Now what is the CIT? Just as C s is defined as you know how do you define that C s minus D Q s by D psi s correct. Whenever I try to change the surface potential there is a corresponding change in semiconductor charge that constitutes a semiconductor capacitance precisely on the same definition as I am trying to change the surface potential traps are also changing the charge states. There is certain charge in the traps which we call Q i t and this Q i t is changing correct is precisely what we discussed I am trying to change the surface potential and that changes the charge in the traps and hence we define this term called C i t which is minus D Q i t by D psi s. That is when I go from one surface potential certain band bending in silicon to a second surface potential that is D psi s I not only will generate some charge in silicon but I will also change the charge in traps correct. So, there is a change in voltage and there is a corresponding change in charge and that is capacitance for you right and that is now a trap capacitance or C i t. And this is a total charge that when I put a gate charge accordingly this is the total charge that is responding in silicon partly at the interface and partly in the rest of the silicon and that is why we say that these two are in parallel. Now as you would imagine if this is a case then your semiconductor capacitance would be increasing you see if I try to measure the capacitance C ox in series with C s in parallel with something else you would expect capacitance to change because of C i t and that is precisely what happens in this region for low frequency but not at high frequency very interestingly. Why is that? Again exactly what we discussed at high frequency I am changing the signal very fast and hence these charges which are trapped in these defects they need some time to you know empty or fill I am not giving enough time for these two empty and fill because my measurement frequency is so fast and hence when I am doing high frequency measurement I do not get that extra capacitance when I am doing low frequency measurement my frequency is so low that I am giving enough time to fill these traps empty these traps as a result of that the C i t will come in only at low frequency and hence this is what you see. So, C i t at L f but not at H f right make sense and hence at any given point here at this point you do not see the difference anyway because all your capacitance is dictated by C ox and again here you know this is you know as expected this is dictated by the maximum depletion with minimum capacitance and again this is governed by you know whatever you have in terms of the oxide capacitance but here where they were supposed to be exactly identical on top of each other you see this difference and this difference you know whatever you have in this depletion region is due to C i t and that is what you see. So, this is a very interesting impact on low frequency in addition to the stretch out. Now, why did the stretch out happen again you must understand this when I went from this gate bias to this gate bias remember exactly what the discussion we had in high frequency I am giving enough time I am giving enough time for that to settle down. So, when I go from this point to this point I have given enough time to fill and empty these traps that is why there is a stretch out because in order to generate that many charges in silicon to get that band bending first I need to take care of the trap stat charges. So, that is why the C v is getting stretched out I need to put in more charge on the gate because there is more charge that needs to be generated in silicon not only for that you know the usual depletion charge but also the trap charge and because I am doing slow step the stretch out is responding to the slow variation slow ramp that I have but at any gate voltage my measurement frequency is too fast or too slow. So, for that measurement frequency only when it is low frequency I have higher capacitance at high frequency I do not see that capacitance you know due to interface traps because frequency is too fast. So, let us just recap then what we discussed we looked at the ideal C v re looked at it and studied the impact on impact of oxide thickness and doping concentration and recognize the fact that transistor structure if you do capacitance voltage measurement no matter whether you do a measurement at high or low frequency you always get a curve which looks like a low frequency curve because of the fact that you have this reservoir of electrons and then subsequently we started looking at the non idealities and the V F B non zero V F B comes because of work function difference or the fixed oxide charge if the fixed oxide charge is positive the C v will always shift to the left if the fixed oxide charge is negative not in silicon oxide but in some dielectrics it could be then the C v could shift to the right but this is always a parallel translation no stretch out compared to ideal capacitance voltage characteristics. On the other hand when we talk of interface trades these are exactly at the silicon silicon oxide transition and hence they communicate with the channel charge depending on holes electrons whatever is there you know they can easily go back and forth and hence you have a varying charge and the D I T is defined as a function of what is the density in the band gap and because this is distributed in the band gap the charge state varies depending on the location of the formula and given that if we go with this model that above mid gap is acceptor and below mid gap is donor like you know then the C v will essentially stretch out with the pivot point being out here C v will always stretch out in place of interface trades where is the pivot point depends on where is the charge neutral condition here we have said charge neutral condition is at mid gap. And then finally low frequency capacitance also gets impacted because of D I T and that is simply because there is also a trap capacitance in fact C I T is given as Q D I T this is how we define this definition will translate to this definition they are equivalent definitions we will stop here and in the next class we will continue discussion on other non idealities and the actual measurement and extraction of parameters.