 Welcome to the session Principles of Sequential Logic Circuit. At the end of this session, students will be able to explain the concepts of sequential logic circuit and explain the working of basic memory element and a latch. In this session, we are going to see sequential logic circuit, its types, then basic memory element and types of latches and flip-lops. Sequential logic circuit. You know that in the last session, we have completed a combination logic circuit. So, to proceed with sequential logic circuit, you first recall and explain what is a combination logic circuit. So, in combination logic circuit, output depends upon the input given at that instant and output does not depend upon the past values and output does not matter where the inputs are given in a particular sequence. But in case of sequential logic circuit, it is having a combination logic circuit with that it is having a memory element. From memory element, it is giving feedback, which is given again to the combination logic circuit. So, output depends upon not only on the present input as well as past values. So, let us see the properties of sequential logic circuit, where sequential logic circuit output depends not only on the its current input, but also on the past values. In other words, sequential logic circuit must be able to remember the past values in order to produce the present value, which is feedback to the combination logic circuit. And then only we can have the present output. One more thing about sequential logic circuit is, it has to remember the past values, so it has to have a memory element. And also output in case of sequential logic circuit depends upon the inputs in which sequence these are applied. For example, the sequential logic circuits are resistors, shift resistors, counters, sequence generators. Now, let us see type of sequential circuits. Sequential logic circuits are classified as Synchronous sequential circuits, and Ur-Synchronous Sequential Circuits. Synchronous sequential circuits are easy to design, whereas Ur-Synchronous sequential circuits are difficult to design. In the case of a synchronous sequential circuit, memory element used are clocked pliplops. Where as Ur-Synchronous sequential circuit uses unclocked pliplop or sometimes these are known as laches. or time delays. As synchronous sequential circuits are using clocked flip-flops these are slower because when clock is present then only it produces the output whereas in case of asynchronous sequential circuit these are faster as because we are using latches where these are not depending upon the particular clock. So one more difference is that in case of synchronous sequential circuit the state of memory element is affected only at active edge of clock with respect to input whereas in asynchronous sequential circuit the state of memory element changes at any time when input is present. So let us see the block diagram of synchronous sequential circuit where we have already discussed this sequential circuit but in case of synchronous sequential circuit we have clock to the storage element or memory element. So whenever there is a clock given to the storage element then only it produces the output and which is given as a feedback to the combinational lock circuit and depending upon the present input and present state you can find out the next state which is nothing but output of synchronous sequential circuit. In case of asynchronous sequential circuit it is having all the things same but memory element is not having a clock. So output depends upon the input coming from the memory element which is continuously provided and the external inputs. So this is what difference between synchronous and asynchronous sequential circuits. Now let us see a basic memory element which can be constructed by using two node gates or also called as inverters with a feedback loop from a static memory element. This memory element holds the data as long as power has supplied. So this is what a basic memory element where we are using two node gates. Now let us have an example where 0 is given as input to the first node gate at time t whereas it produces output as 1 at t plus delta time and this output is given as input to the second node gate and which produces output 0 at t plus 2 delta and this 0 is get feedback to the first node gate. So in this way 0 is converted to 1, 1 is converted to 0, again 0 is looped back to the first node gate. So 0 is get stored. In other way you can give 1 to store the data then 1 is converted to 0, 0 is given input to the second node gate and 0 is converted to 1. So in this way 1 is get feedback which goes into the loop for the infinite time till power is supplied. So finally you will get the stored data which are you are giving as a input. Now let us see how to store a new data in the memory element. For that you have to have a switch in the feedback path and one more switch at the input path. So let us consider switch 1 is in the input path and switch 2 at the feedback path. So when you want to change the data simply give the data then turn on the switch 1. So 0 will be applied to the first node gate then it converts 1 then it produces output 0. It will be get feedback when you are closing the switch 2. So in this way 0 is get rotated at the time open the switch 1 so that there will be no new data entered and 0 is get stored for particular a time period. So in this way 0 is get rotated in the loop and stored for a finite time. Now let us see latches and flip-lops. The most popular types of memory elements are latches and flip-lops. The latches are level sensitive storage element whereas flip-lops are a-striggered storage elements. It means that latches gives output whenever there is a level of a clock pulse and flip-lops gives output whenever there is a age. Now age may be positive age or negative age. So positive a-striggered flip-lops are working whenever there is a transition from 0 to 1 and negative a-striggered flip-lops are working whenever there is a 1 to 0 transition. Examples of latches are sr latch, s bar r bar latch, d latch, jk latch, t latch. Examples of flip-lops are again sr flip-lop, d flip-lop, jk flip-lop, t flip-lop. Now let us have one example sr latch. The latch using node gate, two node gates. So if you replace these two node gates by NOR gate, what you can get is a latch made by universal logic gate. So here as you know that NOR gate having two inputs, one input is coming from the feedback to each NOR gate and one new input is given to each NOR gate. For example, let us consider first input is r. So second input is coming from the second NOR gate and to the second NOR gate, the first input is s and second input is coming from the first NOR gate's output. So here you can see feedback path. Now for example, let us consider input argument as 0, 0, r0, s0. So to find out what will be the output, we have to consider some output here. So let us consider q0, obviously q bar will be 1. So q and q bar never be same. So this should be complement of each other. So for this input, we have considered output as 0, 1. So this 1 is 0 is applied here and this 0 is applied to the s and then 1 is get feedback to the first NOR gate where 0, 1 input to the first NOR gate produces output as 0. So this 0 is get applied to the second NOR gate and second NOR gate having 0, 0 as input. So due to 0, 0 input, it produces output as 1. So whenever input r0, 0, s and r are 0, 0, there will be no change. The next state will be same as that of present state. So here you can find out in a truth table that when s and r are 0, 0, there will be no change for q and q bar. So this state is known as a no change or lost state because the present state is same as per the last state. Now you follow the same method to find out the output by giving such input like 1, 0, 0, 1, 1, 1. So when you are giving 1, 0, you will get output q as 1 and q bar as 0. So this condition is known as a set. Whenever output is 1, it is called as a set. And when you are giving s and r input as 0 and 1, you will get output q as 0 and q bar as 1. So this state is known as a reset state. When both inputs are 1, 1, then you will get output both same. But the q and q bar are always opposite to each other, complement of each other. So this condition or state is known as an invalid state or not allowed state. So in this way, you can find out the output for a particular input by following the procedure which we have found and you can find out the state of the flip log. These are references. Thank you.