 Let's have a look at the first hands-on. We will execute CoreMark on STM32-L5 discovery kit, and we'll do that at two various frequencies, at the maximum 110 MHz and then at 24 MHz. The goal is to see that the CoreMark score is linear with frequency, which is thanks to the fact that there is a low number of weight states on the internal flash, and thanks to the eye-cache that accelerates the code execution at higher frequencies. The application output some useful information on the ST-Link virtual comport that we will display on the terminal window, in this case the data term. I'm going to use STM32-L5 discovery kit that has the version of L5 with the integrated SMPS. On the board you'll also find ST-Link V3 power shield to do power consumption measurement, and various other components such as external memories, Bluetooth module, etc. To display some runtime messages during the CoreMark execution we will use the virtual comport of the ST-Link, and in the next hands-on we'll also use the cube monitor power to measure the consumption during the execution of CoreMark. In the link underneath this video you will find all the materials to be able to reproduce everything that you see in this hands-on. Throughout the video I will only use binaries, but you are free to have a look inside the source code later on. Please make sure that you unzip the folder in the path with no spaces. This is especially important because of the batch script that opens the charter window. Let's start by connecting USB cable to ST-Link V3 connector. Then we should make sure the jumpers and switches are in the correct position. The jumper at the bottom right should be in the rightmost position, in the position 5V from the ST-Link. The switch in the middle of the board should be in the right position also, on the VDD. This will make sure that the target microcontroller is properly supplied from the ST-Link. Then go to the hands-on folder and start the terra-term script. This will launch the standalone terra-term that is included inside the tools folder. If you have troubles doing that, just open your preferred terminal window and set up the connection parameters as highlighted in the slide. The USB cable is now plugged into the ST-Link. We can connect to the target and flash the two binaries. I have pre-compiled one binary for CoreMark running at 110 MHz and a second one running at 24 MHz. ST-Link enumerates also as a master reach, so the easiest way to flash a binary is simply drag and drop it to the ST-Link master reach. So in just a moment, you see the binary was flashed and the CoreMark is immediately executed. If I press the reset, it will start from the beginning. So the CoreMark needs to run for at least 10 seconds to get a valid result. So let's wait a bit. Okay, and here we go. You see the code ran for 11 seconds, which is fine. It ran 5000 iterations. So the CoreMark score is 443 iterations per second. I used RMC-Link v6.14 as a compiler and set the flags to optimize for speed. The code is of course running from flash and at the very bottom we see the confirmation of the frequency, which is 110 MHz. So let's now run the second binary. I will just flash it in. Again, we need to wait at least 10 seconds to get a valid result. And here we go. The CoreMark score is 98.3 iterations per second. So if we divide the CoreMark score with the frequency, we get approximately 4 for both cases, which is a proof that the relationship is in fact linear. Here you see another comparison of STM32L5 with one of our competitor that is also based on Cortex M33. To make this comparison fair, we are using the same compiler and the same compiler flags. This is also the reason why the result for 110 MHz is few percent less than in the demonstration that we have just did with RMC-Link. L5 scores at 80 MHz just few points less than the other device at 150. So to summarize, the system-level architecture of a chip is extremely important factor that affects not only the performance but also power efficiency, as you will see in the next demonstration.