 So this is a different talk and mostly a tutorial to learn about hardware design and maybe more precisely FPGA design. So this is EDA and OpenHour room, so we talk about hardware. And in particular for this talk we are talking about how to design a chip. Not about PCBs, our other talk later for PCB design. And it's not about analog chip, which is mostly part of new carp and cubes, but it's about digital chip. I would say in the real life designing a real digital chip is very, very complex and it's done only by very large company. You need to invest a lot of money for the software, for the manufacturing. So we will do something a little bit different. So this is some of tool you need to build a chip, very expensive. Hopefully some chip are completely programmable. Most of the chip I would say fixed have only one purpose and there are few chips named FPGA that are completely programmable, which means that you can see them a little bit like the software. You define what you want to do with the chip and it's almost exclusively digital chip. So what is inside programmable chip, which is almost always called FPGA. So you have the inputs and outputs on the side. You have some cells that are programmable and that define a particular function. And you have a lot of nets that can be configured as a root. So you can program the chip to connect for example this part to this input of this cell. So there is a lot of extra features in the chip just to be able to configure the chip, which means that the chip is slow and somewhat expensive compared to a fully custom chip. So digital is about 0 and 1 and here I assume you know a little bit about digital computation. That means the basic operations that are used in almost every digital chip are end-up. So this is the basic building blocks of a chip. And the purpose of digital design is to combine these basic blocks to do something more complex. So for example, if you associate gates like this, you get the XOR function using only AND, not an OR gate. And the AND at the output of the gate, that means it's an inverter, so you get the NOT of AND in this case. So you can combine gates to create new gates. Here we create the XOR and if you combine them in a meaningful way, you can even do some math. For example, the XOR, here is the output for all the possible inputs. In fact, XOR is just for one bit, same as an addition. So if you have one input, you get one AND the result. And if you have two AND, you should get two, but because it's only the lowest bit of the output, you get zero. So this is what is called, I would say, half an adder. And so adding only one bit is not very interesting, but if you get a full adder with output AND carry, you do something a little bit more interesting to do math. So this is the circuit of a full adder with two inputs AND carry input AND the output AND the carry of the output. And this is the block schematic for the full adder. Just using the basic blocks we have defined before. And what is interesting with a full adder is to combine them to create an adder for, for example, four bits. So here you really have more interesting, I would say, mathematical computation using only the basic blocks. And if you combine a full adder, you can also do multiplication. So it's even more powerful. This is an example of a four-bit by four-bit multiplication. It's not very efficient, it's not very, also very, you know, very efficient in time of area, but it does work. So if you continue to combine gates, you can do, I would say, almost whatever you want from input and do any computation to create output. The problem with this kind of circuit is that it's, I would say, either too simple or not very powerful. And you get only power from mathematics if you do feedback or recursion. That means you use the output to compute the next input. This works well in maths, but unfortunately it doesn't work at all like this in hardware design. The reason is that you have, I would say, some physical constraints. If you set value to input, you get value on the output side, but necessarily not at the same time. So for example, you may get some before the carry. And if you re-enject directly the output to the input, it will compute something that is not correct because it will use the sum, the real sum, but the wrong carry. So at the end you will get something that is completely wrong and completely unstable. So that's where we need to synchronize signals. And this is a very important notion in old digital circuit. You need a clock to create synchronization, which means to define a time at which the inputs are stable and at which the outputs, so maybe generally the next clock will be stable. And this is not only for dealing with propagation, but also to deal with variation of process. I mean, not circuit are created equal. There might be some difference between two chips that are created from the same manufacturer for many reasons. And to deal with this variation of process, the easiest way was to use a clock and to synchronize with a correct frequency. So this is the other important element of the digital circuit, which is flip-flop. And it has an additional input, the clock. And the important point of the clock is that when the clock is rising, so this is, we are using rising edge clocks, it defines a particular time at which the inputs are, from the input of the flip-flop should be stable and it memorize the input and so writes the input to the output for the next cycle. So during this period, the output of the clock will be computable. So the computation part could be able to do the computation and the output of the computation should be ready for the next cycle, just before the next cycle. So at the end, I would say a digital design is a mix of computation logic gates and memorization element flip-flops. That's the basic notion of how to do digital design, at least the theoretical part. So it is possible to write the gates using improved schematic editor, but it's very reduced and it doesn't scale very well. So that was how it was done in the early 80s. And during the 80s, people created hardware description language, which is language, I would say, like C, that could be used to describe a complete circuit. And I will show a little bit how it works. So we will use this little board which contains a programmable circuit. So it was from Lattice and it's an I-stick board. And we will use 22 euro, very expensive. And we will use some open source and free tools. So JHDL for the VHDL front-end uses to create the net list, our ACNIP pair and ACNIP pair to create the bit stream for the file that should be sent to this to program this FPGA, and iStorm, which is a tool to actually write the bit stream on this d-chip. So what is the look of the VHDL file? So in VHDL circuit is composed in two parts. There is entity and architecture. So entity defies the interfaces. This is the interface. We need a clock and there is five outputs, which will correspond to the LED. So if the output is set to one, the LED is on and if the output is set to zero, the LED is off. Very simple. This is the interface of the circuit. And there is a comment that describes how the LED are placed on the circuit. So they are here and it's not of use to know which one corresponds to which LED, which wire corresponds to which LED. And this is the internal of the circuit. It has, I would say, one main process, which is some computation here within a flip flop. So if rising edge means that we will do the computation only on the rising edge of the clock. And the computation is just a counter and when it reach 3 million, it is reset to zero and the LED is flipped. So this is just a way to make LED blink. Not too quickly, otherwise you can see this thing. And not too slow, otherwise you can't wait until it flips. So this is a very simple example. And this is, I would say, the one possible way to do the whole work to program at the end of the FPGA. So first for VHDL, this is a little bit particular to VHDL, you need to analyze the sources so that the system knows about the files. And this is done using VHDL and then we do synthesis. So we create a netlist, so the list of gates that is derived from the description, the textual description we have seen just before. So we use VHDL as a plugin for creating the netlist. And we say we want to synthesize for this particular circuit. So it creates LED.VIF, which is the netlist, which is called the netlist. Then we use ARCHNIPAIR to assign and place the values gates to the FPGA. And for these tools, we need also to define where the LEDs are placed on the pad. You cannot be guessed by the tool. So you need to specify the input that was created by users. You need to specify the place file for the pads. And it generates an ASCII file that is then used by iSPAC to create a binary and then by iSPOC to send the binary directly to the chip. So it was already done directly for this card. In fact, the binary file is stored in a flash on this board. So it will work directly when I will power up. And I have something a little bit more complex than just blinking. It also rotates. So this is a list of tools we have used. So the entities are used by users via the front end, which is my tool. And ARCHNIPAIR to place and route on the chip. And the whole IC40 tools set from T4, which is ISTOM. Any question? Yes. Q&A about the state and feature of the HDL. So first, the HDL, at least at the beginning, was a simulator. Yeah, yeah, yeah. So at the beginning, the main purpose of the HDL is to do simulation, which means just not creating a circuit, but testing the circuit just on your computer. This part is, I would say, well-advanced. It supports, as far as I know, everything from the 93 standard and many features from the 2008 standard. For synthesis, which means using the HDL to create a circuit, it's a very, very, very work-in-progress tool, which is what I have named it, dash-beta. And it only supports, well, it's only a proof of concept. It only supports, I would say, basic features, but it doesn't really support, for example, bus or not well supported things like that. It's a proof of concept. I have to put more work and time on it. For software people doing their first FPGA debugging. Haha, debugging. It's easier to learn to write it than to debug it. Okay, the question is how to debug? Usually, you don't debug. It's like first time. That's the possibility. You can get right first time. It's okay. What you usually do is you do simulation. So you do run with a simulator, your HDL design, or debug design, and you debug it like software. And then when you try, when you program, it should be almost okay. There are some possibilities, for example, to use a pad to sort an internal signal and use oscilloscope or tools like that to debug, but it's very difficult to do debugging on hardware. Okay, you. There are not tools that are g-tag or something like that. You know, because it feels like a bit like an Arduino or something. Okay, the question is about debugging using g-tag. The first purpose of g-tag is to do hardware testing, which is not debugging. Just testing that the chip works correctly. Then there are some extensions, for example, to read a particular wire or state of a particular flip-flop within a circuit which could be used to debug your circuit. But it depends on whether it is supported by a particular chip or not. But it is a usual interface to do that, yes. Yeah, you go, go, go. The question is about the limitation of this 22 euro chip board. Okay, the main limitation is the size and the number of inputs and outputs for this chip. Actually, it is already quite large. You can implement some processor in this chip with a memory with simple graphical output. So it's not that small. If you want to do something that is very more complex, for example, if you want to interface with the PCI card, this chip is not powerful enough to do that. You need to buy a larger chip and a more expensive one. We have time for two more questions. Okay. I didn't see a timing constraint in the overall work. So timing constraint for clock and... Okay, the question is about there was no timing constraint. The point is that this is a very simple design and it needs only three megahertz. So it's way below any constraint. With this tool set, I don't think so. I may be wrong, but I don't think so. The question is about other chip supported by the tool chain. So for a full tool chain, I think it's not the only chip, but it's the only family that is completely supported. So why you can use a full open source tool chain? There are some efforts. I have heard to support also Xilinx devices, but it's far from being done yet. But you're welcome to join. Okay. Directly. I say you can use RISC-5, a small RISC-5 processor in this chip. It's possible. It has been done. Maybe not to run Linux, but at least an embedded program, yes, it's possible. Okay, yes. Thanks, Tristan, again. Thank you.